SMSC LPC47S42x Technical data

LPC47S42x

Enhanced Super I/O with LPC Interface for

Server Applications

FEATURES

• 3.3 Volt Operation (5V Tolerant)

• Floppy Disk Controller (Supports Two FDCs)

• Multi-Mode Parallel Port

• Two UARTs

• 8042 Keyboard Controller

• SMBus Controller

• X-Bus Interface

• Programmable Wakeup Event Interface

(nIO_PME Pin)

• SMI Support (nIO_SMI Pin)

• GPIOs (39)

• Fan Speed Control Output

• Fan Tachometer Input

• ISA IRQ to Serial IRQ Conversion

• XNOR Chain

• PC99 and ACPI 1.0 Compliant

• ISA Plug-and-Play Compatible Register Set

• Intelligent Auto Power Management

• 2.88MB Super I/O Floppy Disk Controller

- Licensed CMOS 765B Floppy Disk Controller

- Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core

- Configurable Open Drain/Push-Pull Output Drivers

- Supports Vertical Recording Format

- 16-Byte Data FIFO

- 100% IBM

- Detects All Overrun and Underrun

Conditions

- Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown

Compatibility

• Enhanced Digital Data Separator

• Keyboard Controller

• Serial Ports

• Multi-Mode Parallel Port with ChiProtect™

Modes for Reduced Power Consumption

- DMA Enable Logic

- Data Rate and Drive Control Registers

- 480 Address, up to 15 IRQ and Three

DMA Options

- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates

- Programmable Precompensation Modes

- 8042 Software Compatible

- 8-Bit Microcomputer

- 2k Bytes of Program ROM

- 256 Bytes of Data RAM

- Four Open Drain Outputs Dedicated for

Keyboard/Mouse Interface

- Asynchronous Access to Two Data Registers and One Status Register

- Supports Interrupt and Polling Access

- 8-Bit Counter Timer

- Port 92 Support

- Fast Gate A20 and KRESET Outputs

- Two Full Function Serial Ports

- High Speed NS16C550 Compatible

UARTs with Send/Receive 16-Byte FIFOs

- Supports 230k and 460k Baud

- Programmable Baud Rate Generator

- Modem Control Circuitry

- 480 Address and 15 IRQ Options

- IrDA 1.0, HP-SIR, ASK IR Support

- Standard Mode IBM PC/XT

and PS/2™ Compatible Bidirectional Parallel Port

- Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)

- IEEE 1284 Compliant Enhanced Capabilities Port (ECP)

- ChiProtect Circuitry for Protection Against Damage Due to Printer PowerOn

LPC47S422QFP for 100 pin QFP package

LPC47S422-MS for 100 pin QFP package (green, lead-free)

, PC/AT®,

- 480 Address, up to 15 IRQ and 3 DMA Options

- Multiplexed Command, Address and Data Bus

- 8-Bit I/O Transfers

- 8-Bit DMA Transfers

- 16-Bit Address Qualification

- Serial IRQ Interface Compatible with

Serialized IRQ Support for PCI Systems

- Power Management Event (PME) Interface Pin

• 100 Pin QFP package; green, lead-free package also available

ORDERING INFORMATION

Order Number(s):

GENERAL DESCRIPTION

The LPC47S42x* is a 3.3V PC99 compliant Super I/O controller. The LPC47S42x implements the LPC interface, a pin reduced ISA interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. The part provides 39 GPIO pins, an SMBus controller, a fan speed control output, a fan tachometer input, four ISA IRQs that can be routed to any of the serial IRQs, and an X-Bus interface.

The LPC47S42x incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP, and Intelligent Power Management. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates

*The “x” in the part number is a designator that changes depending upon the particular BIOS used inside the specific chip. “2” denotes AMI Keyboard BIOS and “7” denotes Phoenix 42i Keyboard BIOS.

SMSC's patented data separator technology, allowing for ease of testing and use. The on-chip UARTs are compatible with the NS16C550. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The LPC47S42x incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes.

The LPC47S42x supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the recommended functionality to support Windows '95/’98 and PC99. The I/O Address, DMA Channel and Hardware IRQ of each logical device in the LPC47S42x may be reprogrammed through the internal configuration registers. There are 480 I/O address location options, a Serialized IRQ interface, and three DMA channels.

TABLE OF CONTENTS

FEATURES ............................................................................................................................................. 1

GENERAL DESCRIPTION...................................................................................................................... 3

PIN CONFIGURATION............................................................................................................................ 6

DESCRIPTION OF PIN FUNCTIONS...................................................................................................... 7

Buffer Type Descriptions .....................................................................................................................12

Pins That Require External Pullup Resistors.......................................................................................13

3.3 VOLT OPERATION / 5 VOLT TOLERANCE ...................................................................................14

POWER FUNCTIONALITY ....................................................................................................................14

VCC Power .........................................................................................................................................14

VTR Support .......................................................................................................................................14

Internal PWRGOOD............................................................................................................................14

32.768 kHz Trickle Clock Input............................................................................................................14

Indication of 32kHz Clock....................................................................................................................14

Trickle Power Functionality .................................................................................................................15

Maximum Current Values....................................................................................................................17

Power Management Events (PME/SCI) ..............................................................................................17

FUNCTIONAL DESCRIPTION ...............................................................................................................18

Super I/O Registers.............................................................................................................................18

Host Processor Interface (LPC) ..........................................................................................................18

FLOPPY DISK CONTROLLER ..............................................................................................................23

FDC Internal Registers........................................................................................................................23

Command Set/Descriptions.................................................................................................................41

Instruction Set .....................................................................................................................................45

SERIAL PORT (UART) ..........................................................................................................................73

INFRARED INTERFACE........................................................................................................................88

PARALLEL PORT..................................................................................................................................90

POWER MANAGEMENT .....................................................................................................................113

SERIAL IRQ .........................................................................................................................................117

Routable IRQ to Serial IRQ Conversion Capability ...........................................................................121

8042 KEYBOARD CONTROLLER DESCRIPTION .............................................................................122

Keyboard Interface............................................................................................................................122

External Keyboard and Mouse Interface ...........................................................................................124

Keyboard Power Management..........................................................................................................124

Interrupts ...........................................................................................................................................125

Memory Configurations .....................................................................................................................125

Register Definitions ...........................................................................................................................125

External Clock Signal ........................................................................................................................125

Default Reset Conditions...................................................................................................................126

Latches On Keyboard and Mouse IRQs............................................................................................129

Keyboard and Mouse PME Generation.............................................................................................131

GENERAL PURPOSE I/O....................................................................................................................132

GPIO Pins .........................................................................................................................................132

Description ........................................................................................................................................133

GPIO Control.....................................................................................................................................136

GPIO Operation ................................................................................................................................137

GPIO PME and SMI Functionality .....................................................................................................138

Either Edge Triggered Interrupts .......................................................................................................140

LED Functionality ..............................................................................................................................140

WATCH DOG TIMER ...........................................................................................................................140

SYSTEM MANAGEMENT INTERRUPT (SMI).....................................................................................141

SMI Registers....................................................................................................................................142

ACPI Support Register for SMI Generation.......................................................................................142

PME Support .......................................................................................................................................143

Wake On Specific Key Option ...........................................................................................................144

FAN SPEED CONTROL AND MONITORING......................................................................................145

Fan Speed Control ............................................................................................................................145

Fan Tachometer Input .......................................................................................................................147

SECURITY FEATURE..........................................................................................................................151

GPIO Device Disable Register Control..............................................................................................151

Device Disable Register ....................................................................................................................151

SMBus CONTROLLER........................................................................................................................151

Overview ...........................................................................................................................................151

Configuration Registers.....................................................................................................................152

Runtime Registers.............................................................................................................................152

Pin Multiplexing .................................................................................................................................159

SMBus Timeouts...............................................................................................................................159

X-BUS INTERFACE .............................................................................................................................160

X-Bus Chip Select Base I/O Address Registers ................................................................................163

X-Bus Configuration Register............................................................................................................163

RUNTIME REGISTERS........................................................................................................................164

Runtime Registers Block Summary...................................................................................................164

Runtime Registers Block Description ................................................................................................168

CONFIGURATION ...............................................................................................................................199

OPERATIONAL DESCRIPTION ..........................................................................................................228

Maximum Guaranteed Ratings..........................................................................................................228

DC Electrical Characteristics.............................................................................................................228

TIMING DIAGRAMS.............................................................................................................................232

ECP Parallel Port Timing...................................................................................................................243

X-Bus Timing.....................................................................................................................................252

PACKAGE OUTLINE ...........................................................................................................................260

APPENDIX - TEST MODES .................................................................................................................261

Board Test Mode...............................................................................................................................261

GP40/DRVDEN0

GP41/DRVDEN1/nXCS0

nDSKCHG

nWDATA nWGATE

nHDSEL

nINDEX

nWRTPRT

nRDATA

GP42/nIO_PME

CLOCKI

nLFRAME

nPCI_RESET

nLPCPD

GP43/DDRC/nXCS1

PCI_CLK

SER_IRQ

nMTR0

nDS0

CLKI32

VSS

nDIR

nSTEP

nTRK0

VTR

LAD0 LAD1 LAD2 LAD3

nLDRQ

PIN CONFIGURATION

GP57/nDTR2

GP56/nCTS2

GP55/nRTS2

GP54/nDSR2

GP53/TXD2/IRTX

GP52/RXD2/I RRX

GP51/nDCD2

VCC

GP50/nRI2

nDCD1

nRI1

nDTR1

nCTS1

nRTS1

nDSR1

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31323334353637383940414243444546474849

LPC47S42x

100 PIN QFP

VSS

GP10/XD0

GP11/XD1

GP12/XD2

GP13/XD3

GP14/XD4

GP15/XD5

GP16/XD6

GP17/XD7

GP20/P17/nDS1

GP62/P17/IRQINC

GP23/IRQIND

GP21/P16/P12

GP24/SYSOPT

GP22/P12/nMTR1

TXD1

RXD1

nSTROBE

nALF

nERROR

nACK

BUSY

SLCT

VSS

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

nSLCTIN

nINIT

VCC

GP37/nA20M

GP36/nKBDRST

GP35/IRQINB

GP34/IRQINA

VSS

MCLK

MDAT

KCLK

KDAT

GP33/FAN/XA1

GP32/SDAT/XA0

VCC

GP31/FAN_TACH/nXCS3/XA3

GP30/SCLK/nXCS2/XA2

GP60/LED1

GP61/LED2

GP25/nXRD

GP26/nXWR

GP27/nIO_SMI

DESCRIPTION OF PIN FUNCTIONS

Note: There are no internal pullups on any of the pins in the LPC47S42x.

PIN #

3 4 5 8

9 10 11 12 13 14 15 16

24 25 26 27 29 30

GP40/DRVDEN0 General Purpose I/O/Drive

GP41/DRVDEN1/ nXCS0

nMTR0 Motor On 0 O12 (O12/OD12) nDSKCHG Disk Change IS IS nDS0 Drive Select 0 O12 (O12/OD12) nDIR Step Direction O12 (O12/OD12) nSTEP Step Pulse O12 (O12/OD12) nWDATA Write Disk Data O12 (O12/OD12) nWGATE Write Gate O12 (O12/OD12) nHDSEL Head Select O12 (O12/OD12) nINDEX Index Pulse Input IS IS nTRK0 Track 0 IS IS nWRTPRT Write Protected IS IS nRDATA Read Disk Data IS IS

LAD0 Multiplexed Command Address

LAD1 Multiplexed Command Address

LAD2 Multiplexed Command Address

LAD3 Multiplexed Command Address

nLFRAME Frame PCI_I PCI_I nLDRQ Encoded DMA Request PCI_O PCI_O nPCI_RESET PCI Reset PCI_I PCI_I nLPCPD Power Down (Note 2) PCI_I PCI_I PCI_CLK PCI Clock PCI_ICLK PCI_ICLK SER_IRQ Serial IRQ PCI_IO PCI_IO

GP42/nIO_PME General Purpose I/O/Power

GP43/DDRC/nXCS1 General Purpose I/O/Device

GP10/XD0 General Purpose I/O/X-Bus Data

NAME

FUNCTION

FDD INTERFACE

Density Select 0 General Purpose I/O/Drive Density Select 1/X-Bus Chip Select 0

LPC INTERFACE

and Data 0

and Data 1

and Data 2

and Data 3

GENERAL PURPOSE I/O PINS

Management Event Output

Disable Reg. Control/X-Bus Chip Select 1

Bit 0

BUFFER

TYPE

IO12 (I/O12/OD12)/

PCI_IO PCI_IO

IO12 (I/O12/OD12)/

IO8 (I/O8/OD8)/I/O8

IO8 (I/O8/OD8)/IO8

BUFFER TYPE PER FUNCTION (NOTE 1)

(O12/OD12)

(O12/OD12)/O12

(O12/OD12)

PIN #

NAME

GP11/XD1

General Purpose I/O/X-Bus Data

FUNCTION

BUFFER

TYPE

IO8 (I/O8/OD8)/IO8

BUFFER TYPE PER

FUNCTION (NOTE 1)

Bit 1

GP12/XD2

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 2

GP13/XD3

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 3

GP14/XD4

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 4

GP15/XD5

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 5

GP16/XD6

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 6

GP17/XD7

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 7

GP62/P17/IRQINC General Purpose I/O/P17/

IO8 (I/O8/OD8)/IO8/I

IRQ Input C

GP20/P17/nDS1 General Purpose I/O/P17 /Drive

Select 1

GP21/P16/P12 General Purpose I/O/P16/P12 IO8 (I/O8/OD8)/IO8/

IO12 (I/O12/OD12)/

IO12/(O12/OD12)

IO8

GP22/P12/nMTR1 General Purpose I/O/P12/Motor

On 1

GP23/IRQIND General Purpose I/O/IRQ Input D IO8 (I/O8/OD8)/I

GP24/SYSOPT General Purpose I/O/System

IO12 (I/O12/OD12)/

IO12/(O12/OD12)

IO8 (I/O8/OD8)

Option (Note 7)

GP25/nXRD General Purpose I/O/X-Bus Read

IO8 (I/O8/OD8)/O8

Strobe (Note 10)

GP26/nXWR General Purpose I/O/X-Bus Write

IO8 (I/O8/OD8)/O8

Strobe (Note 10)

GP60/LED1 General Purpose I/O/LED1 (Note

GP61/LED2 General Purpose I/O/LED2 (Note

GP27/nIO_SMI General Purpose I/O/nIO_SMI IO12 (I/O12/OD12)/

IO12 (I/O12/OD12)/

(O12/OD12)

IO12 (I/O12/OD12)/

(O12/OD12)

GP34/IRQINA General Purpose I/O/IRQ Input A IO12 (I/O21/OD12)/I

GP35/IRQINB General Purpose I/O/IRQ Input B IO12 (I/O12/OD12)/I

SMBUS PINS

PIN #

NAME

GP30/SCLK/ nXCS2/XA2

FUNCTION

General Purpose I/O/SMBus Clock/X-Bus Chip Select 2/X-Bus

BUFFER

TYPE

IO12 (I/O12/OD12)/

BUFFER TYPE PER

FUNCTION (NOTE 1)

IOD12/O12/O12

Address 2

GP32/SDAT/XA0 General Purpose I/O/SMBus

Data/X-Bus Address 0

IO12 (I/O12/OD12)/

IOD12/O12

FAN CONTROL PINS

GP31/FAN_TACH/ nXCS3/XA3

General Purpose I/O/Fan Tachometer Input/X-Bus Chip

IO8 (I/O8/OD8)/I/O8/

Select 3/X-Bus Address 3

GP33 /FAN/XA1 General Purpose I/O /Fan

Control/X-Bus Address 1 (Note 4)

IO12 (I/O12/OD12)/

(O12/OD12)/O12

KEYBOARD/MOUSE

KDAT Keyboard Data IOD16 IOD16

KCLK Keyboard Clock IOD16 IOD16

MDAT Mouse Data IOD16 IOD16

MCLK Mouse Clock IOD16 IOD16

GP36/nKBDRST General Purpose I/O /Keyboard

IO8 (I/O8/OD8)/O8

Reset (Note 8)

GP37/A20M General Purpose I/O /Gate A20

IO8 (I/O8/OD8)/O8

(Note 8)

PARALLEL PORT INTERFACE

nINIT/nDIR Initiate Output/FDC Direction

Control

nSLCTIN/nSTEP Printer Select Input/FDC Step

Pulse

PD0/nINDEX Port Data 0/FDC Index IS/OP14 IOP14/IS

PD1/nTRK0 Port Data 1/FDC Track 0 IS/OP14 IOP14/IS

PD2/nWRTPRT Port Data 2/FDC Write Protected IS/OP14 IOP14/IS

PD3/nRDATA Port Data 3/FDC Read Disk Data IS/OP14 IOP14/IS

PD4/nDSKCHG Port Data 4/FDC Disk Change IS/OP14 IOP14/IS

PD5 Port Data 5 IOP14 IOP14

PD6/nMTR0 Port Data 6/FDC Motor On 0 IOP14 IOP14/OD14

PD7 Port Data 7 IOP14 IOP14

SLCT/nWGATE

Printer Selected Status/FDC Write

OP14 (OD14/OP14)/

OD14

OP14 (OD14/OP14)/

OD14

IO12 I/OD12

Gate

PE/nWDATA Paper End/FDC Write Data IO12 I/OD12

BUSY/nMTR1 Busy/FDC Motor On IO12 I/OD12

nACK/nDS1 Acknowledge/FDC Drive Select 1 IO12 I/OD12

nERROR/nHDSEL Error/FDC Head Select IO12 I/OD12

nALF/nDRVDEN0

Autofeed Output/FDC Density Select

OP14

(OD14/OP14)/ OD14

PIN #

NAME

FUNCTION

BUFFER

TYPE

nSTROBE/nDS0 Strobe Output/FDC Drive Select OP14

BUFFER TYPE PER

FUNCTION (NOTE 1)

(OD14/OP14)/ OD14

SERIAL PORT 1 INTERFACE

RXD1 Receive Data 1 IS IS

TXD1 Transmit Data 1 O12 O12

nDSR1 Data Set Ready 1 I I

nRTS1 Request to Send 1 O8 O8

nCTS1 Clear to Send 1 I I

nDTR1 Data Terminal Ready 1 O6 O6

nRI1 Ring Indicator 1 I I

nDCD1 Data Carrier Detect 1 I I

SERIAL PORT 2 INTERFACE

GP50/nRI2 General Purpose I/O/Ring

IO8 (I/O8/OD8)/I

Indicator 2

GP51/nDCD2 General Purpose I/O/Data Carrier

IO8 (I/O8/OD8)/I

Detect 2

GP52/RXD2/IRRX General Purpose I/O/Receive

IS/O8 (IS/O8/OD8)/IS/IS

Data 2/IRRX

GP53/TXD2/IRTX General Purpose I/O/Transmit

Data 2/IRTX

IO12 (I/O12/OD12)/O12/

O12

(Note 5, 6)

GP54/nDSR2 General Purpose I/O/Data Set

IO8 (I/O8/OD8)/I

Ready 2

GP55/nRTS2 General Purpose I/O/Request to

IO8 (I/O8/OD8)/O8

Send 2

GP56/nCTS2 General Purpose I/O/Clear to

IO8 (I/O8/OD8)/I

Send 2

100

GP57/nDTR2 General Purpose I/O/Data

IO8 (I/O8/OD8)/O8

Terminal Ready 2

POWER PINS

53,

VCC +3.3 Volt Supply Voltage

65, 93

VTR +3.3 Volt Standby Supply Voltage

(Note 6)

7, 31,

VSS Ground

60, 76

CLOCK PINS

CLKI32 32.768kHz Standby Clock Input

IS IS

(Note 3)

CLOCKI 14.318MHz Clock Input IS IS

Note: The "n" as the first letter of a signal name indicates an "Active Low" signal. Note 1: Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in

parenthesis represent multiple buffer types for a single pin function.

Note 2: The nLPCPD pin may be tied high. The LPC interface will function properly if the

nPCI_RESET signal follows the protocol defined for the nLRESET signal in the “Low Pin Count Interface Specification”.

Note 3: If the 32kHz input clock is not used the CLKI32 pin must be grounded. There is a bit in the

configuration register at 0xF0 in Logical Device A that indicates whether or not the 32KHz clock is connected. This bit determines the clock source for the fan tachometer, LED and “wake on specific key” logic. Set this bit to ‘1’ if the clock is not connected.

Note 4: The fan control pin (FAN) comes up as output and low following a VCC POR and Hard Reset.

This pin reverts to its non-inverting General Purpose I/O output function when VCC is removed from the part.

Note 5: The GP53/TXD2/IRTX pin is an output and low when the part is under VTR power (VCC=0).

The pin comes up as output and low following a VCC POR and Hard Reset. Note 6: VTR can be connected to VCC if no wakeup functionality is required. Note 7: The GP24/SYSOPT pin requires an external pulldown resistor to put the base I/O address for

configuration at 0x02E. An external pullup resistor is required to move the base I/O address

for configuration to 0x04E. Note 8: External pullups must be placed on the nKBDRST and A20M pins. These pins are General

Purpose I/Os that are inputs after an initial power-up (VTR POR). If the nKBDRST and A20M

functions are to be used, the system must ensure that these pins are high. See Section “Pins

That Require External Pullup Resistor”. Note 9: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under

VTR power. The GP61 pin defaults to the LED function active (blinking at a 1Hz rate, 50%

duty cycle) on initial power up (as long as the 32 kHz clock input is active). Note 10: External pullups are required on the nXRD and nXWR pins.

Buffer Type Descriptions

IO12 Input/Output, 12mA sink, 6mA source. IS/O12 Input with Schmitt Trigger/Output, 12mA sink, 6mA source. O12 Output, 12mA sink, 6mA source. OD12 Open Drain Output, 12mA sink. O6 Output, 6mA sink, 3mA source. O8 Output, 8mA sink, 4mA source. OD8 Open Drain Output, 8mA sink. IO8 Input/Output, 8mA sink, 4mA source. IS/O8 Input with Schmitt Trigger/Output, 8mA sink, 4mA source. OD14 Open Drain Output, 14mA sink. OP14 Output, 14mA sink, 14mA source. IOP14 Input/Output, 14mA sink, 14mA source. Backdrive protected. IOD16 Input/Output (Open Drain), 16mA sink. O4 Output, 4mA sink, 2mA source. I Input TTL Compatible. IS Input with Schmitt Trigger. PCI_IO Input/Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_O Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_OD Open Drain Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_I Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_ICLK Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing.

(Note 2)

Note 1. See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. Note 2. See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. and 4.2.3.

Pins That Require External Pullup Resistors

The following pins require external pullup resistors:

• KDAT

• KCLK

• MDAT

• MCLK

• GP36/KBDRST if KBDRST function is used

• GP37/A20M if A20M function is used

• GP20/P17/nDS1 If P17 function is used

• GP21/P16/P12 if P16 or P12 function is used

• GP22/P12/nMTR1 if P12 function is used

• GP27/nIO_SMI if nIO_SMI function is used as Open Collector Output

• GP42/nIO_PME if nIO_PME function is used as Open Collector Output

• SER_IRQ

• GP40/DRVDEN0 if DRVDEN0 function is used as Open Collector Output

• GP41/DRVDEN1/XCS0 if DRVDEN1 function is used as Open Collector Output

• GP23, GP 34, GP35 and GP62 if IRQINx function is used

• nMTR0 if used as Open Collector Output

• nDS0 if used as Open Collector Output

• nDIR if used as Open Collector Output

• nSTEP if used as Open Collector Output

• nWDATA if used as Open Collector Output

• nWGATE if used as Open Collector Output

• nHDSEL if used as Open Collector Output

• nINDEX

• nTRK0

• nWRTPRT

• nRDATA

• nDSKCHG

• nXRD

• nXWR

3.3 VOLT OPERATION / 5 VOLT TOLERANCE

The LPC47S42x is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected.

The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are:

• LAD[3:0]

• nLFRAME

• nLDRQ

• nLPCPD

The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins:

• nPCI_RESET

• PCI_CLK

• SER_IRQ

• nIO_PME

POWER FUNCTIONALITY

The LPC47S42x has two power planes: VCC and VTR.

VCC Power

The LPC47S42x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the Operational Description Section and the Maximum Current Values subsection.

VTR Support

The LPC47S42x requires a trickle supply (V

) to provide sleep current for the programmable wake-up events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle Power Functionality subsection and the Maximum Current Values subsection. If the LPC47S42x is not intended to provide wake-up capabilities on standby current,

VTR can be connected to VCC. The VTR pin generates a V

Power-on-Reset signal to

initialize these components.

Note: If V wake-up events when V

is to be used for programmable

is removed, VTR must

be at its full minimum potential at least 10 µs before V and V

begins a power-on cycle. When VTR

are fully powered, the potential

difference between the two supplies must not exceed 500mV.

Internal PWRGOOD

An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as V

cycles on

and off. When the internal PWRGOOD signal is “1” (active), V

> 2.3V (nominal), and the

LPC47S42x host interface is active. When the internal PWRGOOD signal is “0” (inactive), V

2.3V (nominal), and the LPC47S42x host interface is inactive; that is, LPC bus reads and writes will not be decoded.

The LPC47S42x device pins nIO_PME, CLOCKI32, KDAT, MDAT, IRRX, nRI1, nRI2, RXD2 and most GPIOs (as input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive, provided V

is powered. The

GP53/TXD2/IRTX, GP60/LED1 and GP61/LED2 pins also remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. See Trickle Power Functionality section.

32.768 kHz Trickle Clock Input

The LPC47S42x utilizes a 32.768 kHz trickle clock input to supply a clock signal for the fan tachometer logic, WDT, LED blink and wake on specific key function. See the following section for more information.

Indication of 32kHz Clock

There is a bit to indicate whether or not the 32kHz clock input is connected to the

≤

LPC47S42x. This bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR POR.

Bit[0] (CLK32_PRSN) is defined as follows: 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded).

Bit 0 controls the source of the 32kHz (nominal) clock for the CIR wakeup, fan tachometer logic, the LED blink logic, the WDT and the “wake on specific key” logic. When the external 32kHz clock is connected, that will be the source for the fan tachometer, LED, WDT and “wake on specific key” logic. When the external 32kHz clock is not connected, an internal 32kHz clock source will be derived from the 14MHz clock for the fan tachometer, LED, WDT and “wake on specific key” logic.

The following functions will not work under VTR power (VCC removed) if the external 32kHz clock is not connected. These functions will work under VCC power even if the external 32kHz clock is not connected.

• Fan tachometer

• Wake on specific key

• LED blink

• WDT

Trickle Power Functionality

When the LPC47S42x is running under VTR only, the PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The following lists the wakeup events:

• UART 1 Ring Indicator

• UART 2 Ring Indicator

• Keyboard data

• Mouse data

• Wake on Specific Key Logic

• Fan Tachometer (Note)

• GPIOs for wakeup. See below.

Note. The Fan Tachometer can generate a PME when VCC=0. Clear the enable bits for the fan tachometers before removing fan power.

The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.

• I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.

• I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by VTR. This means they will, at a minimum, source their specified current from VTR even when VCC is present.

The GPIOs that are used for PME wakeup inputs are GP10-GP17, GP20-GP27, GP30-GP37, GP41, GP43, GP50-GP57, GP60, GP61. These GPIOs function as follows (with the exception of GP53, GP60 and GP61 - see below):

• Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR.

All GPIOs listed above are for PME wakeup as a GPIO function (or alternate function). Note that GP33 cannot be used for wakeup under VTR power (VCC=0) since this is the fan control pin which comes up as output and low following a VCC POR and Hard Reset. GP53 cannot be used for wakeup under VTR power since this has the IRTX function and comes up as output and low following a VTR POR, a VCC POR and Hard Reset. Also, GP33 reverts to its non-inverting GPIO output function when VCC is removed from the part. GP43 reverts to the basic GPIO function when VCC is removed form the part, but its programmed input/output, invert/non-invert output buffer type is retained.

The other GPIOs function as follows:

GP40, GP62:

• Buffers powered by VCC, but in the absence of VCC they are backdrive protected. These pins do not have input buffers into the wakeup logic that are powered by VTR.

These pins are not used for wakeup.

GP42, GP53, GP60, GP61:

• Buffers powered by VTR.

GP42 is the nIO_PME pin. GP53 has IRTX as the alternate function and its output buffer is powered by VTR so that the pin is always forced low on VTR POR, VCC POR and Hard Reset. The IRTX pin (GP53/TXD2/IRTX) is powered by VTR so that it is driven low when VCC = 0V with VTR = 3.3V. This pin is driven low on VTR POR, VCC POR and Hard Reset regardless of the selected pin function and regardless of the state of internal PWRGOOD (i.e., when VCC=3.3V and when

VCC=0V with VTR=3.3V). The GP53/TXD2/IRTX pin will remain low following a VCC POR until the IRTX function is selected and the serial port is enabled by setting the activate bit, at which time the pin will reflect the state of the IR transmit output of the IR block. If the TXD2 function is selected for the pin, it will remain low following a VCC POR until the serial port is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the serial port. If the GPIO output function is selected, the pin will reflect the state of the data bit.

GP60 and GP61 are used for the LED functions.

See the Table in the GPIO section for more information.

The following list summarizes the blocks, registers and pins that are powered by VTR.

• PME interface block

• Runtime register block (includes all PME, SMI, GPIO and other miscellaneous registers)

• Wake on Specific Key logic

• LED control logic

• Pins for PME Wakeup:

- GP42/nIO_PME (output, buffer powered by VTR)

- nRI1 (input)

- GP50/nRI2 (input)

- GP52/RXD2/IRRX (input)

- KDAT (input)

- MDAT (input)

- GPIOs (GP10-GP17, GP20-GP27, GP30-GP37, GP41, GP43, GP50-GP57, GP60, GP61) –

all input-only except GP53, GP60, GP61. See below.

• Other Pins

- GP53/TXD2/IRTX (output, buffer powered by VTR)

- GP60/LED1 (output, buffer powered by VTR)

- GP61/LED2 (output, buffer powered by VTR)

Maximum Current Values

Refer to the “Operational Description” section for the maximum current values.

The maximum VTR current, I

, is given with all outputs open (not loaded). The total maximum current

for the part is the unloaded value PLUS the maximum current sourced by all pins that are driven by VTR. The pins that are powered by VTR are as follows: GP42/nIO_PME, GP53/TXD2/IRTX, GP60/LED1, GP61/LED2. These pins, if configured as push-pull outputs, will source a minimum of 6mA at 2.4V when driving.

The maximum VCC current, ICC, is given with all outputs open (not loaded).

Power Management Events (PME/SCI)

The LPC47S42x offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal on pin 17. See the “PME Support” section.

FUNCTIONAL DESCRIPTION

Super I/O Registers

The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game port and configuration register block can be moved via the configuration registers. Some addresses are used to access more than one register.

Table 1 - Super I/O Block Addresses

ADDRESS

Base+(0-5) and +(7) Floppy Disk 0 Base+(0-7) Serial Port Com 1 4 Base+(0-7) Serial Port Com 2 5 IR Support

Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) 60, 64 KYBD 7 60 - 67 X-Bus 8 Base + (0-6C) Runtime Registers A Base+(0-3) SMBus B Base + (0-1) Configuration

Note 1: Refer to the configuration register descriptions for setting the base address.

BLOCK NAME

Parallel Port SPP EPP ECP ECP+EPP+SPP

Host Processor Interface (LPC)

The host processor communicates with the LPC47S42x through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table

1. Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.

LOGICAL

DEVICE

NOTES

LPC Interface

The following sub-sections specify the implementation of the LPC bus.

LPC Interface Signal Definition

The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal characteristics.

SIGNAL NAME TYPE DESCRIPTION

LAD[3:0] I/O LPC address/data bus. Multiplexed command, address and data

bus.

nLFRAME Input Frame signal. Indicates start of new cycle and termination of broken

cycle nPCI_RESET Input PCI Reset. Used as LPC Interface Reset. nLDRQ Output Encoded DMA/Bus Master request for the LPC interface. nIO_PME OD Power Mgt Event signal. Allows the LPC47S42x to request wakeup. nLPCPD Input Powerdown Signal. Indicates that the LPC47S42x should prepare

for power to be shut on the LPC interface. SER_IRQ I/O Serial IRQ. PCI_CLK Input PCI Clock.

LPC Cycles

The following cycle types are supported by the LPC protocol.

CYCLE TYPE TRANSFER SIZE

I/O Write 1 Byte Transfer

I/O Read 1 Byte Transfer DMA Write 1 Byte DMA Read 1 Byte

The LPC47S42x ignores cycles that it does not support.

Field Definitions

The data transfers are based on specific fields that are used in various combinations, depending on the cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the LPC bus between the host and the LPC47S42x. See the Low Pin Count (LPC) Interface Specification Revision 1.0 from Intel, Section 4.2 for definition of these fields.

nLFRAME Usage

nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal is to be used by the LPC47S42x to know when to monitor the bus for a cycle.

This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the LPC47S42x monitors the bus to determine whether the cycle is intended for it. The use of nLFRAME allows the LPC47S42x to enter a lower power state internally. There is no need for the LPC47S42x to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks.

When the LPC47S42x samples nLFRAME active, it immediately stops driving the LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information.

The nLFRAME signal functions as described in the Low Pin Count (LPC) Interface Specification Reference.

I/O Read and Write Cycles

The LPC47S42x is the target for I/O cycles.

I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times.

Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it up into 8-bit transfers.

See the Low Pin Count (LPC) Interface Specification Reference, Section 5.2, for the sequence of cycles for the I/O Read and Write cycles.

DMA Read and Write Cycles

DMA read cycles involve the transfer of data from the host (main memory) to the LPC47S42x. DMA write cycles involve the transfer of data from the LPC47S42x to the host (main memory). Data will be coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47S42x are 1 byte.

See the Low Pin Count (LPC) Interface Specification Reference, Section 6.4, for the field definitions and the sequence of the DMA Read and Write cycles.

DMA Protocol

DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47S42x and special encodings on LAD[3:0] from the host.

The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Interface Specification Reference.

Power Management

CLOCKRUN Protocol

The nCLKRUN pin is not implemented in the LPC47S42x. See the Low Pin Count (LPC) Interface Specification Reference, Section 8.1.

LPCPD Protocol

See the Low Pin Count (LPC) Interface Specification Reference, Section 8.2.

SYNC Protocol

See the Low Pin Count (LPC) Interface Specification Reference, Section 4.2.1.8 for a

table of valid SYNC values.

Typical Usage

The SYNC pattern is used to add wait states. For read cycles, the LPC47S42x immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47S42x needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The LPC47S42x will choose to assert 0101 or 0110, but not switch between the two patterns.

The data (or wait state SYNC) will immediately follow the 0000 or 1001 value.

The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The LPC47S42x uses a SYNC of 0101 for all wait states in a DMA transfer.

The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47S42x uses a SYNC of 0110 for all wait states in an I/O transfer.

The SYNC value is driven within 3 clocks.

SYNC Timeout

The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it will abort the cycle.

The LPC47S42x does not assume any particular timeout. When the host is driving SYNC, it may have to insert a very large number of wait states, depending on PCI latencies and retries.

SYNC Patterns and Maximum Number of SYNCS

If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is

If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47S42x has protection mechanisms to complete the cycle. This is used for EPP data transfers and will utilize the same timeout protection that is in EPP.

SYNC Error Indication

The LPC47S42x reports errors via the LAD[3:0] = 1010 SYNC encoding.

If the host was reading data from the LPC47S42x, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47S42x. If the host was writing data to the LPC47S42x, the data had already been transferred.

In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not be transferred.

I/O and DMA START Fields I/O and DMA cycles use a START field of 0000.

Reset Policy The following rules govern the reset policy:

1) When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus.

2) When nPCI_RESET goes active (low): a) The host drives the nLFRAME signal

high, tristates the LAD[3:0] signals, and ignores the nLDRQ signal.

b) The LPC47S42x ignores nLFRAME,

tristate the LAD[3:0] pins and drive the nLDRQ signal inactive (high).

LPC Transfers

Wait State Requirements

I/O Transfers

The LPC47S42x inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would normally be deasserted in an ISA transfer (i.e., EPP) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us).

DMA Transfers

The LPC47S42x inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of 0101 is used for all DMA transfers.

Refer to example timing for the LPC cycles in the “Timing Diagrams” section.

FLOPPY DISK CONTROLLER

The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection.

The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.

Table 2 - Status, Data and Control Registers

(Shown with base addresses of 3F0 and 370)

PRIMARY

ADDRESS

3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7

Status Register A (SRA)

Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0.

PS/2 Mode

7 6 5 4 3 2 1 0 INT

RESET COND.

BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction.

SECONDARY

ADDRESS

370 371 372 373 374 374 375 376 377 377

nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR

PENDING

0 1 0 N/A 0 N/A N/A 0

FDC Internal Registers

The Floppy Disk Controller contains eight internal registers that facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected.

R/W

R R/W R/W

R/W

Status Register A (SRA) Status Register B (SRB) Digital Output Register (DOR) Tape Drive Register (TDR) Main Status Register (MSR) Data Rate Select Register (DSR) Data (FIFO) Reserved Digital Input Register (DIR) Configuration Control Register (CCR)

BIT 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected.

BIT 2 nINDEX Active low status of the INDEX disk interface input.

BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side

BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input.

BIT 5 STEP Active high status of the STEP output disk interface output pin.

BIT 6 nDRV2 This function is not supported. This bit is always read as “1”.

BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output.

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0 INT

PENDING RESET COND.

BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction.

BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected.

BIT 2 INDEX Active high status of the INDEX disk interface input.

0 0 0 N/A 1 N/A N/A 1

DRQ STEP

F/F

TRK0 nHDSEL INDX WP nDIR

BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side

BIT 4 TRACK 0 Active high status of the TRK0 disk interface input.

BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset.

BIT 6 DMA REQUEST Active high status of the DMA request pending.

BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt.

Status Register B (SRB)

Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1.

PS/2 Mode

7 6 5 4 3 2 1 0 1 1 DRIVE

SEL0 RESET COND.

BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 2 WRITE GATE Active high status of the WGATE disk interface output.

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

1 1 0 0 0 0 0 0

WDATA

TOGGLE

RDATA

TOGGLE

WGATE MOT

EN1

MOT

EN0

BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset.

BIT 6 RESERVED Always read as a logic "1".

BIT 7 RESERVED Always read as a logic "1".

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0 nDRV2 nDS1 nDS0 WDATA

F/F RESET COND.

BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported.

BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported.

BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register.

BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register.

BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output.

BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported. Digital Output Register (DOR)

Address 3F2 READ/WRITE

N/A 1 1 0 0 0 1 1

RDATA

F/F

WGATE

F/F

nDS3 nDS2

The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time.

7 6 5 4 3 2 1 0 MOT

EN3

RESET

COND.

BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time.

BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and interrupt functions. This bit is a logic "0" after a reset and in these modes.

PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic "0".

BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported.

BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported.

Tape Drive Register (TDR)

Address 3F3 READ/WRITE

MOT

EN2

0 0 0 0 0 0 0 0

MOT

EN1

DRIVE DOR VALUE

0 1

MOT

EN0

DMAEN nRESET DRIVE

1CH 2DH

SEL1

DRIVE

SEL0

The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 3 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset.

Table 3 - Tape Select Bits

TAPE SEL1

(TDR.1)

0 0 1 1

Table 4 - Internal 2 Drive Decode - Normal

DIGITAL OUTPUT

Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X 1 0 0 1 0 nBIT 5 nBIT 4

1 X 0 1 0 1 nBIT 5 nBIT 4

0 0 X X 1 1 nBIT 5 nBIT 4

Table 5 - Internal 2 Drive Decode - Drives 0 and 1 Swapped

DIGITAL OUTPUT

Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X 1 0 0 0 1 nBIT 4 nBIT 5

1 X 0 1 1 0 nBIT 4 nBIT 5

0 0 X X 1 1 nBIT 4 nBIT 5

TAPE SEL0

(TDR.0)

0 1 0 1

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

DRIVE SELECTED

None

1 2 3

MOTOR ON OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Normal Floppy Mode

Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are ‘0’.

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 0 0 0 0 0 0 tape sel1 tape sel0

Enhanced Floppy Mode 2 (OS2)

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive tape sel1 tape sel0

Table 6 - Drive Type ID

DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID

Bit 1 Bit 0 Bit 5 Bit 4

0 0 L0-CRF2 - B1 L0-CRF2 - B0 0 1 L0-CRF2 - B3 L0-CRF2 - B2 1 0 L0-CRF2 - B5 L0-CRF2 - B4 1 1 L0-CRF2 - B7 L0-CRF2 - B6

Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.

Data Rate Select Register (DSR)

Address 3F4 WRITE ONLY

This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps.

7 6 5 4 3 2 1 0 S/W

RESET RESET COND.

BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7 shows the precompensation values for the combination of these bits settings. Track 0 is

POWER

DOWN

0 0 0 0 0 0 1 0

0 PRE-

COMP2

PRE-

COMP1

PRE-

COMP0

DRATE

SEL1

DRATE

SEL0

the default starting track number to start precompensation. This starting track number can be changed by the configure command.

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register.

BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.

Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the runtime register block.

Table 7 - Precompensation Delays

PRECOMP

432

<2Mbps 2Mbps

111 001 010 011 100 101 110 000

Default: See Table 10

PRECOMPENSATION

DELAY (nsec)

0.00

41.67

83.34

125.00

166.67

208.33

250.00 Default

20.8

41.7

62.5

83.3

104.2 125

Default

+ 234 hidden pages

SMSC LPC47S42x Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual