SMSC LPC47S42x Technical data

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LPC47S42x

Enhanced Super I/O with LPC Interface for

Server Applications

FEATURES

• 3.3 Volt Operation (5V Tolerant)

• Floppy Disk Controller (Supports Two FDCs)

• Multi-Mode Parallel Port

• Two UARTs

• 8042 Keyboard Controller

• SMBus Controller

• X-Bus Interface

• Programmable Wakeup Event Interface

(nIO_PME Pin)

• SMI Support (nIO_SMI Pin)

• GPIOs (39)

• Fan Speed Control Output

• Fan Tachometer Input

• ISA IRQ to Serial IRQ Conversion

• XNOR Chain

• PC99 and ACPI 1.0 Compliant

• ISA Plug-and-Play Compatible Register Set

• Intelligent Auto Power Management

• 2.88MB Super I/O Floppy Disk Controller

- Licensed CMOS 765B Floppy Disk Controller

- Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core

- Configurable Open Drain/Push-Pull Output Drivers

- Supports Vertical Recording Format

- 16-Byte Data FIFO

- 100% IBM

- Detects All Overrun and Underrun

Conditions

- Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown

Compatibility

• Enhanced Digital Data Separator

• Keyboard Controller

• Serial Ports

• Multi-Mode Parallel Port with ChiProtect™

Modes for Reduced Power Consumption

- DMA Enable Logic

- Data Rate and Drive Control Registers

- 480 Address, up to 15 IRQ and Three

DMA Options

- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates

- Programmable Precompensation Modes

- 8042 Software Compatible

- 8-Bit Microcomputer

- 2k Bytes of Program ROM

- 256 Bytes of Data RAM

- Four Open Drain Outputs Dedicated for

Keyboard/Mouse Interface

- Asynchronous Access to Two Data Registers and One Status Register

- Supports Interrupt and Polling Access

- 8-Bit Counter Timer

- Port 92 Support

- Fast Gate A20 and KRESET Outputs

- Two Full Function Serial Ports

- High Speed NS16C550 Compatible

UARTs with Send/Receive 16-Byte FIFOs

- Supports 230k and 460k Baud

- Programmable Baud Rate Generator

- Modem Control Circuitry

- 480 Address and 15 IRQ Options

- IrDA 1.0, HP-SIR, ASK IR Support

- Standard Mode IBM PC/XT

and PS/2™ Compatible Bidirectional Parallel Port

- Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)

- IEEE 1284 Compliant Enhanced Capabilities Port (ECP)

- ChiProtect Circuitry for Protection Against Damage Due to Printer PowerOn

LPC47S422QFP for 100 pin QFP package

LPC47S422-MS for 100 pin QFP package (green, lead-free)

, PC/AT®,

- 480 Address, up to 15 IRQ and 3 DMA Options

- Multiplexed Command, Address and Data Bus

- 8-Bit I/O Transfers

- 8-Bit DMA Transfers

- 16-Bit Address Qualification

- Serial IRQ Interface Compatible with

Serialized IRQ Support for PCI Systems

- Power Management Event (PME) Interface Pin

• 100 Pin QFP package; green, lead-free package also available

ORDERING INFORMATION

Order Number(s):

GENERAL DESCRIPTION

The LPC47S42x* is a 3.3V PC99 compliant Super I/O controller. The LPC47S42x implements the LPC interface, a pin reduced ISA interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. The part provides 39 GPIO pins, an SMBus controller, a fan speed control output, a fan tachometer input, four ISA IRQs that can be routed to any of the serial IRQs, and an X-Bus interface.

The LPC47S42x incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP, and Intelligent Power Management. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates

*The “x” in the part number is a designator that changes depending upon the particular BIOS used inside the specific chip. “2” denotes AMI Keyboard BIOS and “7” denotes Phoenix 42i Keyboard BIOS.

SMSC's patented data separator technology, allowing for ease of testing and use. The on-chip UARTs are compatible with the NS16C550. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The LPC47S42x incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes.

The LPC47S42x supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the recommended functionality to support Windows '95/’98 and PC99. The I/O Address, DMA Channel and Hardware IRQ of each logical device in the LPC47S42x may be reprogrammed through the internal configuration registers. There are 480 I/O address location options, a Serialized IRQ interface, and three DMA channels.

TABLE OF CONTENTS

FEATURES ............................................................................................................................................. 1

GENERAL DESCRIPTION...................................................................................................................... 3

PIN CONFIGURATION............................................................................................................................ 6

DESCRIPTION OF PIN FUNCTIONS...................................................................................................... 7

Buffer Type Descriptions .....................................................................................................................12

Pins That Require External Pullup Resistors.......................................................................................13

3.3 VOLT OPERATION / 5 VOLT TOLERANCE ...................................................................................14

POWER FUNCTIONALITY ....................................................................................................................14

VCC Power .........................................................................................................................................14

VTR Support .......................................................................................................................................14

Internal PWRGOOD............................................................................................................................14

32.768 kHz Trickle Clock Input............................................................................................................14

Indication of 32kHz Clock....................................................................................................................14

Trickle Power Functionality .................................................................................................................15

Maximum Current Values....................................................................................................................17

Power Management Events (PME/SCI) ..............................................................................................17

FUNCTIONAL DESCRIPTION ...............................................................................................................18

Super I/O Registers.............................................................................................................................18

Host Processor Interface (LPC) ..........................................................................................................18

FLOPPY DISK CONTROLLER ..............................................................................................................23

FDC Internal Registers........................................................................................................................23

Command Set/Descriptions.................................................................................................................41

Instruction Set .....................................................................................................................................45

SERIAL PORT (UART) ..........................................................................................................................73

INFRARED INTERFACE........................................................................................................................88

PARALLEL PORT..................................................................................................................................90

POWER MANAGEMENT .....................................................................................................................113

SERIAL IRQ .........................................................................................................................................117

Routable IRQ to Serial IRQ Conversion Capability ...........................................................................121

8042 KEYBOARD CONTROLLER DESCRIPTION .............................................................................122

Keyboard Interface............................................................................................................................122

External Keyboard and Mouse Interface ...........................................................................................124

Keyboard Power Management..........................................................................................................124

Interrupts ...........................................................................................................................................125

Memory Configurations .....................................................................................................................125

Register Definitions ...........................................................................................................................125

External Clock Signal ........................................................................................................................125

Default Reset Conditions...................................................................................................................126

Latches On Keyboard and Mouse IRQs............................................................................................129

Keyboard and Mouse PME Generation.............................................................................................131

GENERAL PURPOSE I/O....................................................................................................................132

GPIO Pins .........................................................................................................................................132

Description ........................................................................................................................................133

GPIO Control.....................................................................................................................................136

GPIO Operation ................................................................................................................................137

GPIO PME and SMI Functionality .....................................................................................................138

Either Edge Triggered Interrupts .......................................................................................................140

LED Functionality ..............................................................................................................................140

WATCH DOG TIMER ...........................................................................................................................140

SYSTEM MANAGEMENT INTERRUPT (SMI).....................................................................................141

SMI Registers....................................................................................................................................142

ACPI Support Register for SMI Generation.......................................................................................142

PME Support .......................................................................................................................................143

Wake On Specific Key Option ...........................................................................................................144

FAN SPEED CONTROL AND MONITORING......................................................................................145

Fan Speed Control ............................................................................................................................145

Fan Tachometer Input .......................................................................................................................147

SECURITY FEATURE..........................................................................................................................151

GPIO Device Disable Register Control..............................................................................................151

Device Disable Register ....................................................................................................................151

SMBus CONTROLLER........................................................................................................................151

Overview ...........................................................................................................................................151

Configuration Registers.....................................................................................................................152

Runtime Registers.............................................................................................................................152

Pin Multiplexing .................................................................................................................................159

SMBus Timeouts...............................................................................................................................159

X-BUS INTERFACE .............................................................................................................................160

X-Bus Chip Select Base I/O Address Registers ................................................................................163

X-Bus Configuration Register............................................................................................................163

RUNTIME REGISTERS........................................................................................................................164

Runtime Registers Block Summary...................................................................................................164

Runtime Registers Block Description ................................................................................................168

CONFIGURATION ...............................................................................................................................199

OPERATIONAL DESCRIPTION ..........................................................................................................228

Maximum Guaranteed Ratings..........................................................................................................228

DC Electrical Characteristics.............................................................................................................228

TIMING DIAGRAMS.............................................................................................................................232

ECP Parallel Port Timing...................................................................................................................243

X-Bus Timing.....................................................................................................................................252

PACKAGE OUTLINE ...........................................................................................................................260

APPENDIX - TEST MODES .................................................................................................................261

Board Test Mode...............................................................................................................................261

GP40/DRVDEN0

GP41/DRVDEN1/nXCS0

nDSKCHG

nWDATA nWGATE

nHDSEL

nINDEX

nWRTPRT

nRDATA

GP42/nIO_PME

CLOCKI

nLFRAME

nPCI_RESET

nLPCPD

GP43/DDRC/nXCS1

PCI_CLK

SER_IRQ

nMTR0

nDS0

CLKI32

VSS

nDIR

nSTEP

nTRK0

VTR

LAD0 LAD1 LAD2 LAD3

nLDRQ

PIN CONFIGURATION

GP57/nDTR2

GP56/nCTS2

GP55/nRTS2

GP54/nDSR2

GP53/TXD2/IRTX

GP52/RXD2/I RRX

GP51/nDCD2

VCC

GP50/nRI2

nDCD1

nRI1

nDTR1

nCTS1

nRTS1

nDSR1

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31323334353637383940414243444546474849

LPC47S42x

100 PIN QFP

VSS

GP10/XD0

GP11/XD1

GP12/XD2

GP13/XD3

GP14/XD4

GP15/XD5

GP16/XD6

GP17/XD7

GP20/P17/nDS1

GP62/P17/IRQINC

GP23/IRQIND

GP21/P16/P12

GP24/SYSOPT

GP22/P12/nMTR1

TXD1

RXD1

nSTROBE

nALF

nERROR

nACK

BUSY

SLCT

VSS

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

nSLCTIN

nINIT

VCC

GP37/nA20M

GP36/nKBDRST

GP35/IRQINB

GP34/IRQINA

VSS

MCLK

MDAT

KCLK

KDAT

GP33/FAN/XA1

GP32/SDAT/XA0

VCC

GP31/FAN_TACH/nXCS3/XA3

GP30/SCLK/nXCS2/XA2

GP60/LED1

GP61/LED2

GP25/nXRD

GP26/nXWR

GP27/nIO_SMI

DESCRIPTION OF PIN FUNCTIONS

Note: There are no internal pullups on any of the pins in the LPC47S42x.

PIN #

3 4 5 8

9 10 11 12 13 14 15 16

24 25 26 27 29 30

GP40/DRVDEN0 General Purpose I/O/Drive

GP41/DRVDEN1/ nXCS0

nMTR0 Motor On 0 O12 (O12/OD12) nDSKCHG Disk Change IS IS nDS0 Drive Select 0 O12 (O12/OD12) nDIR Step Direction O12 (O12/OD12) nSTEP Step Pulse O12 (O12/OD12) nWDATA Write Disk Data O12 (O12/OD12) nWGATE Write Gate O12 (O12/OD12) nHDSEL Head Select O12 (O12/OD12) nINDEX Index Pulse Input IS IS nTRK0 Track 0 IS IS nWRTPRT Write Protected IS IS nRDATA Read Disk Data IS IS

LAD0 Multiplexed Command Address

LAD1 Multiplexed Command Address

LAD2 Multiplexed Command Address

LAD3 Multiplexed Command Address

nLFRAME Frame PCI_I PCI_I nLDRQ Encoded DMA Request PCI_O PCI_O nPCI_RESET PCI Reset PCI_I PCI_I nLPCPD Power Down (Note 2) PCI_I PCI_I PCI_CLK PCI Clock PCI_ICLK PCI_ICLK SER_IRQ Serial IRQ PCI_IO PCI_IO

GP42/nIO_PME General Purpose I/O/Power

GP43/DDRC/nXCS1 General Purpose I/O/Device

GP10/XD0 General Purpose I/O/X-Bus Data

NAME

FUNCTION

FDD INTERFACE

Density Select 0 General Purpose I/O/Drive Density Select 1/X-Bus Chip Select 0

LPC INTERFACE

and Data 0

and Data 1

and Data 2

and Data 3

GENERAL PURPOSE I/O PINS

Management Event Output

Disable Reg. Control/X-Bus Chip Select 1

Bit 0

BUFFER

TYPE

IO12 (I/O12/OD12)/

PCI_IO PCI_IO

IO12 (I/O12/OD12)/

IO8 (I/O8/OD8)/I/O8

IO8 (I/O8/OD8)/IO8

BUFFER TYPE PER FUNCTION (NOTE 1)

(O12/OD12)

(O12/OD12)/O12

(O12/OD12)

PIN #

NAME

GP11/XD1

General Purpose I/O/X-Bus Data

FUNCTION

BUFFER

TYPE

IO8 (I/O8/OD8)/IO8

BUFFER TYPE PER

FUNCTION (NOTE 1)

Bit 1

GP12/XD2

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 2

GP13/XD3

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 3

GP14/XD4

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 4

GP15/XD5

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 5

GP16/XD6

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 6

GP17/XD7

General Purpose I/O/X-Bus Data

IO8 (I/O8/OD8)/IO8

Bit 7

GP62/P17/IRQINC General Purpose I/O/P17/

IO8 (I/O8/OD8)/IO8/I

IRQ Input C

GP20/P17/nDS1 General Purpose I/O/P17 /Drive

Select 1

GP21/P16/P12 General Purpose I/O/P16/P12 IO8 (I/O8/OD8)/IO8/

IO12 (I/O12/OD12)/

IO12/(O12/OD12)

IO8

GP22/P12/nMTR1 General Purpose I/O/P12/Motor

On 1

GP23/IRQIND General Purpose I/O/IRQ Input D IO8 (I/O8/OD8)/I

GP24/SYSOPT General Purpose I/O/System

IO12 (I/O12/OD12)/

IO12/(O12/OD12)

IO8 (I/O8/OD8)

Option (Note 7)

GP25/nXRD General Purpose I/O/X-Bus Read

IO8 (I/O8/OD8)/O8

Strobe (Note 10)

GP26/nXWR General Purpose I/O/X-Bus Write

IO8 (I/O8/OD8)/O8

Strobe (Note 10)

GP60/LED1 General Purpose I/O/LED1 (Note

GP61/LED2 General Purpose I/O/LED2 (Note

GP27/nIO_SMI General Purpose I/O/nIO_SMI IO12 (I/O12/OD12)/

IO12 (I/O12/OD12)/

(O12/OD12)

IO12 (I/O12/OD12)/

(O12/OD12)

GP34/IRQINA General Purpose I/O/IRQ Input A IO12 (I/O21/OD12)/I

GP35/IRQINB General Purpose I/O/IRQ Input B IO12 (I/O12/OD12)/I

SMBUS PINS

PIN #

NAME

GP30/SCLK/ nXCS2/XA2

FUNCTION

General Purpose I/O/SMBus Clock/X-Bus Chip Select 2/X-Bus

BUFFER

TYPE

IO12 (I/O12/OD12)/

BUFFER TYPE PER

FUNCTION (NOTE 1)

IOD12/O12/O12

Address 2

GP32/SDAT/XA0 General Purpose I/O/SMBus

Data/X-Bus Address 0

IO12 (I/O12/OD12)/

IOD12/O12

FAN CONTROL PINS

GP31/FAN_TACH/ nXCS3/XA3

General Purpose I/O/Fan Tachometer Input/X-Bus Chip

IO8 (I/O8/OD8)/I/O8/

Select 3/X-Bus Address 3

GP33 /FAN/XA1 General Purpose I/O /Fan

Control/X-Bus Address 1 (Note 4)

IO12 (I/O12/OD12)/

(O12/OD12)/O12

KEYBOARD/MOUSE

KDAT Keyboard Data IOD16 IOD16

KCLK Keyboard Clock IOD16 IOD16

MDAT Mouse Data IOD16 IOD16

MCLK Mouse Clock IOD16 IOD16

GP36/nKBDRST General Purpose I/O /Keyboard

IO8 (I/O8/OD8)/O8

Reset (Note 8)

GP37/A20M General Purpose I/O /Gate A20

IO8 (I/O8/OD8)/O8

(Note 8)

PARALLEL PORT INTERFACE

nINIT/nDIR Initiate Output/FDC Direction

Control

nSLCTIN/nSTEP Printer Select Input/FDC Step

Pulse

PD0/nINDEX Port Data 0/FDC Index IS/OP14 IOP14/IS

PD1/nTRK0 Port Data 1/FDC Track 0 IS/OP14 IOP14/IS

PD2/nWRTPRT Port Data 2/FDC Write Protected IS/OP14 IOP14/IS

PD3/nRDATA Port Data 3/FDC Read Disk Data IS/OP14 IOP14/IS

PD4/nDSKCHG Port Data 4/FDC Disk Change IS/OP14 IOP14/IS

PD5 Port Data 5 IOP14 IOP14

PD6/nMTR0 Port Data 6/FDC Motor On 0 IOP14 IOP14/OD14

PD7 Port Data 7 IOP14 IOP14

SLCT/nWGATE

Printer Selected Status/FDC Write

OP14 (OD14/OP14)/

OD14

OP14 (OD14/OP14)/

OD14

IO12 I/OD12

Gate

PE/nWDATA Paper End/FDC Write Data IO12 I/OD12

BUSY/nMTR1 Busy/FDC Motor On IO12 I/OD12

nACK/nDS1 Acknowledge/FDC Drive Select 1 IO12 I/OD12

nERROR/nHDSEL Error/FDC Head Select IO12 I/OD12

nALF/nDRVDEN0

Autofeed Output/FDC Density Select

OP14

(OD14/OP14)/ OD14

PIN #

NAME

FUNCTION

BUFFER

TYPE

nSTROBE/nDS0 Strobe Output/FDC Drive Select OP14

BUFFER TYPE PER

FUNCTION (NOTE 1)

(OD14/OP14)/ OD14

SERIAL PORT 1 INTERFACE

RXD1 Receive Data 1 IS IS

TXD1 Transmit Data 1 O12 O12

nDSR1 Data Set Ready 1 I I

nRTS1 Request to Send 1 O8 O8

nCTS1 Clear to Send 1 I I

nDTR1 Data Terminal Ready 1 O6 O6

nRI1 Ring Indicator 1 I I

nDCD1 Data Carrier Detect 1 I I

SERIAL PORT 2 INTERFACE

GP50/nRI2 General Purpose I/O/Ring

IO8 (I/O8/OD8)/I

Indicator 2

GP51/nDCD2 General Purpose I/O/Data Carrier

IO8 (I/O8/OD8)/I

Detect 2

GP52/RXD2/IRRX General Purpose I/O/Receive

IS/O8 (IS/O8/OD8)/IS/IS

Data 2/IRRX

GP53/TXD2/IRTX General Purpose I/O/Transmit

Data 2/IRTX

IO12 (I/O12/OD12)/O12/

O12

(Note 5, 6)

GP54/nDSR2 General Purpose I/O/Data Set

IO8 (I/O8/OD8)/I

Ready 2

GP55/nRTS2 General Purpose I/O/Request to

IO8 (I/O8/OD8)/O8

Send 2

GP56/nCTS2 General Purpose I/O/Clear to

IO8 (I/O8/OD8)/I

Send 2

100

GP57/nDTR2 General Purpose I/O/Data

IO8 (I/O8/OD8)/O8

Terminal Ready 2

POWER PINS

53,

VCC +3.3 Volt Supply Voltage

65, 93

VTR +3.3 Volt Standby Supply Voltage

(Note 6)

7, 31,

VSS Ground

60, 76

CLOCK PINS

CLKI32 32.768kHz Standby Clock Input

IS IS

(Note 3)

CLOCKI 14.318MHz Clock Input IS IS

Note: The "n" as the first letter of a signal name indicates an "Active Low" signal. Note 1: Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in

parenthesis represent multiple buffer types for a single pin function.

Note 2: The nLPCPD pin may be tied high. The LPC interface will function properly if the

nPCI_RESET signal follows the protocol defined for the nLRESET signal in the “Low Pin Count Interface Specification”.

Note 3: If the 32kHz input clock is not used the CLKI32 pin must be grounded. There is a bit in the

configuration register at 0xF0 in Logical Device A that indicates whether or not the 32KHz clock is connected. This bit determines the clock source for the fan tachometer, LED and “wake on specific key” logic. Set this bit to ‘1’ if the clock is not connected.

Note 4: The fan control pin (FAN) comes up as output and low following a VCC POR and Hard Reset.

This pin reverts to its non-inverting General Purpose I/O output function when VCC is removed from the part.

Note 5: The GP53/TXD2/IRTX pin is an output and low when the part is under VTR power (VCC=0).

The pin comes up as output and low following a VCC POR and Hard Reset. Note 6: VTR can be connected to VCC if no wakeup functionality is required. Note 7: The GP24/SYSOPT pin requires an external pulldown resistor to put the base I/O address for

configuration at 0x02E. An external pullup resistor is required to move the base I/O address

for configuration to 0x04E. Note 8: External pullups must be placed on the nKBDRST and A20M pins. These pins are General

Purpose I/Os that are inputs after an initial power-up (VTR POR). If the nKBDRST and A20M

functions are to be used, the system must ensure that these pins are high. See Section “Pins

That Require External Pullup Resistor”. Note 9: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under

VTR power. The GP61 pin defaults to the LED function active (blinking at a 1Hz rate, 50%

duty cycle) on initial power up (as long as the 32 kHz clock input is active). Note 10: External pullups are required on the nXRD and nXWR pins.

Buffer Type Descriptions

IO12 Input/Output, 12mA sink, 6mA source. IS/O12 Input with Schmitt Trigger/Output, 12mA sink, 6mA source. O12 Output, 12mA sink, 6mA source. OD12 Open Drain Output, 12mA sink. O6 Output, 6mA sink, 3mA source. O8 Output, 8mA sink, 4mA source. OD8 Open Drain Output, 8mA sink. IO8 Input/Output, 8mA sink, 4mA source. IS/O8 Input with Schmitt Trigger/Output, 8mA sink, 4mA source. OD14 Open Drain Output, 14mA sink. OP14 Output, 14mA sink, 14mA source. IOP14 Input/Output, 14mA sink, 14mA source. Backdrive protected. IOD16 Input/Output (Open Drain), 16mA sink. O4 Output, 4mA sink, 2mA source. I Input TTL Compatible. IS Input with Schmitt Trigger. PCI_IO Input/Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_O Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_OD Open Drain Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_I Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_ICLK Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing.

(Note 2)

Note 1. See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. Note 2. See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. and 4.2.3.

Pins That Require External Pullup Resistors

The following pins require external pullup resistors:

• KDAT

• KCLK

• MDAT

• MCLK

• GP36/KBDRST if KBDRST function is used

• GP37/A20M if A20M function is used

• GP20/P17/nDS1 If P17 function is used

• GP21/P16/P12 if P16 or P12 function is used

• GP22/P12/nMTR1 if P12 function is used

• GP27/nIO_SMI if nIO_SMI function is used as Open Collector Output

• GP42/nIO_PME if nIO_PME function is used as Open Collector Output

• SER_IRQ

• GP40/DRVDEN0 if DRVDEN0 function is used as Open Collector Output

• GP41/DRVDEN1/XCS0 if DRVDEN1 function is used as Open Collector Output

• GP23, GP 34, GP35 and GP62 if IRQINx function is used

• nMTR0 if used as Open Collector Output

• nDS0 if used as Open Collector Output

• nDIR if used as Open Collector Output

• nSTEP if used as Open Collector Output

• nWDATA if used as Open Collector Output

• nWGATE if used as Open Collector Output

• nHDSEL if used as Open Collector Output

• nINDEX

• nTRK0

• nWRTPRT

• nRDATA

• nDSKCHG

• nXRD

• nXWR

3.3 VOLT OPERATION / 5 VOLT TOLERANCE

The LPC47S42x is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected.

The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are:

• LAD[3:0]

• nLFRAME

• nLDRQ

• nLPCPD

The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins:

• nPCI_RESET

• PCI_CLK

• SER_IRQ

• nIO_PME

POWER FUNCTIONALITY

The LPC47S42x has two power planes: VCC and VTR.

VCC Power

The LPC47S42x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the Operational Description Section and the Maximum Current Values subsection.

VTR Support

The LPC47S42x requires a trickle supply (V

) to provide sleep current for the programmable wake-up events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle Power Functionality subsection and the Maximum Current Values subsection. If the LPC47S42x is not intended to provide wake-up capabilities on standby current,

VTR can be connected to VCC. The VTR pin generates a V

Power-on-Reset signal to

initialize these components.

Note: If V wake-up events when V

is to be used for programmable

is removed, VTR must

be at its full minimum potential at least 10 µs before V and V

begins a power-on cycle. When VTR

are fully powered, the potential

difference between the two supplies must not exceed 500mV.

Internal PWRGOOD

An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as V

cycles on

and off. When the internal PWRGOOD signal is “1” (active), V

> 2.3V (nominal), and the

LPC47S42x host interface is active. When the internal PWRGOOD signal is “0” (inactive), V

2.3V (nominal), and the LPC47S42x host interface is inactive; that is, LPC bus reads and writes will not be decoded.

The LPC47S42x device pins nIO_PME, CLOCKI32, KDAT, MDAT, IRRX, nRI1, nRI2, RXD2 and most GPIOs (as input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive, provided V

is powered. The

GP53/TXD2/IRTX, GP60/LED1 and GP61/LED2 pins also remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. See Trickle Power Functionality section.

32.768 kHz Trickle Clock Input

The LPC47S42x utilizes a 32.768 kHz trickle clock input to supply a clock signal for the fan tachometer logic, WDT, LED blink and wake on specific key function. See the following section for more information.

Indication of 32kHz Clock

There is a bit to indicate whether or not the 32kHz clock input is connected to the

≤

LPC47S42x. This bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR POR.

Bit[0] (CLK32_PRSN) is defined as follows: 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded).

Bit 0 controls the source of the 32kHz (nominal) clock for the CIR wakeup, fan tachometer logic, the LED blink logic, the WDT and the “wake on specific key” logic. When the external 32kHz clock is connected, that will be the source for the fan tachometer, LED, WDT and “wake on specific key” logic. When the external 32kHz clock is not connected, an internal 32kHz clock source will be derived from the 14MHz clock for the fan tachometer, LED, WDT and “wake on specific key” logic.

The following functions will not work under VTR power (VCC removed) if the external 32kHz clock is not connected. These functions will work under VCC power even if the external 32kHz clock is not connected.

• Fan tachometer

• Wake on specific key

• LED blink

• WDT

Trickle Power Functionality

When the LPC47S42x is running under VTR only, the PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The following lists the wakeup events:

• UART 1 Ring Indicator

• UART 2 Ring Indicator

• Keyboard data

• Mouse data

• Wake on Specific Key Logic

• Fan Tachometer (Note)

• GPIOs for wakeup. See below.

Note. The Fan Tachometer can generate a PME when VCC=0. Clear the enable bits for the fan tachometers before removing fan power.

The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.

• I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.

• I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by VTR. This means they will, at a minimum, source their specified current from VTR even when VCC is present.

The GPIOs that are used for PME wakeup inputs are GP10-GP17, GP20-GP27, GP30-GP37, GP41, GP43, GP50-GP57, GP60, GP61. These GPIOs function as follows (with the exception of GP53, GP60 and GP61 - see below):

• Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR.

All GPIOs listed above are for PME wakeup as a GPIO function (or alternate function). Note that GP33 cannot be used for wakeup under VTR power (VCC=0) since this is the fan control pin which comes up as output and low following a VCC POR and Hard Reset. GP53 cannot be used for wakeup under VTR power since this has the IRTX function and comes up as output and low following a VTR POR, a VCC POR and Hard Reset. Also, GP33 reverts to its non-inverting GPIO output function when VCC is removed from the part. GP43 reverts to the basic GPIO function when VCC is removed form the part, but its programmed input/output, invert/non-invert output buffer type is retained.

The other GPIOs function as follows:

GP40, GP62:

• Buffers powered by VCC, but in the absence of VCC they are backdrive protected. These pins do not have input buffers into the wakeup logic that are powered by VTR.

These pins are not used for wakeup.

GP42, GP53, GP60, GP61:

• Buffers powered by VTR.

GP42 is the nIO_PME pin. GP53 has IRTX as the alternate function and its output buffer is powered by VTR so that the pin is always forced low on VTR POR, VCC POR and Hard Reset. The IRTX pin (GP53/TXD2/IRTX) is powered by VTR so that it is driven low when VCC = 0V with VTR = 3.3V. This pin is driven low on VTR POR, VCC POR and Hard Reset regardless of the selected pin function and regardless of the state of internal PWRGOOD (i.e., when VCC=3.3V and when

VCC=0V with VTR=3.3V). The GP53/TXD2/IRTX pin will remain low following a VCC POR until the IRTX function is selected and the serial port is enabled by setting the activate bit, at which time the pin will reflect the state of the IR transmit output of the IR block. If the TXD2 function is selected for the pin, it will remain low following a VCC POR until the serial port is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the serial port. If the GPIO output function is selected, the pin will reflect the state of the data bit.

GP60 and GP61 are used for the LED functions.

See the Table in the GPIO section for more information.

The following list summarizes the blocks, registers and pins that are powered by VTR.

• PME interface block

• Runtime register block (includes all PME, SMI, GPIO and other miscellaneous registers)

• Wake on Specific Key logic

• LED control logic

• Pins for PME Wakeup:

- GP42/nIO_PME (output, buffer powered by VTR)

- nRI1 (input)

- GP50/nRI2 (input)

- GP52/RXD2/IRRX (input)

- KDAT (input)

- MDAT (input)

- GPIOs (GP10-GP17, GP20-GP27, GP30-GP37, GP41, GP43, GP50-GP57, GP60, GP61) –

all input-only except GP53, GP60, GP61. See below.

• Other Pins

- GP53/TXD2/IRTX (output, buffer powered by VTR)

- GP60/LED1 (output, buffer powered by VTR)

- GP61/LED2 (output, buffer powered by VTR)

Maximum Current Values

Refer to the “Operational Description” section for the maximum current values.

The maximum VTR current, I

, is given with all outputs open (not loaded). The total maximum current

for the part is the unloaded value PLUS the maximum current sourced by all pins that are driven by VTR. The pins that are powered by VTR are as follows: GP42/nIO_PME, GP53/TXD2/IRTX, GP60/LED1, GP61/LED2. These pins, if configured as push-pull outputs, will source a minimum of 6mA at 2.4V when driving.

The maximum VCC current, ICC, is given with all outputs open (not loaded).

Power Management Events (PME/SCI)

The LPC47S42x offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal on pin 17. See the “PME Support” section.

FUNCTIONAL DESCRIPTION

Super I/O Registers

The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game port and configuration register block can be moved via the configuration registers. Some addresses are used to access more than one register.

Table 1 - Super I/O Block Addresses

ADDRESS

Base+(0-5) and +(7) Floppy Disk 0 Base+(0-7) Serial Port Com 1 4 Base+(0-7) Serial Port Com 2 5 IR Support

Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) 60, 64 KYBD 7 60 - 67 X-Bus 8 Base + (0-6C) Runtime Registers A Base+(0-3) SMBus B Base + (0-1) Configuration

Note 1: Refer to the configuration register descriptions for setting the base address.

BLOCK NAME

Parallel Port SPP EPP ECP ECP+EPP+SPP

Host Processor Interface (LPC)

The host processor communicates with the LPC47S42x through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table

1. Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.

LOGICAL

DEVICE

NOTES

LPC Interface

The following sub-sections specify the implementation of the LPC bus.

LPC Interface Signal Definition

The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal characteristics.

SIGNAL NAME TYPE DESCRIPTION

LAD[3:0] I/O LPC address/data bus. Multiplexed command, address and data

bus.

nLFRAME Input Frame signal. Indicates start of new cycle and termination of broken

cycle nPCI_RESET Input PCI Reset. Used as LPC Interface Reset. nLDRQ Output Encoded DMA/Bus Master request for the LPC interface. nIO_PME OD Power Mgt Event signal. Allows the LPC47S42x to request wakeup. nLPCPD Input Powerdown Signal. Indicates that the LPC47S42x should prepare

for power to be shut on the LPC interface. SER_IRQ I/O Serial IRQ. PCI_CLK Input PCI Clock.

LPC Cycles

The following cycle types are supported by the LPC protocol.

CYCLE TYPE TRANSFER SIZE

I/O Write 1 Byte Transfer

I/O Read 1 Byte Transfer DMA Write 1 Byte DMA Read 1 Byte

The LPC47S42x ignores cycles that it does not support.

Field Definitions

The data transfers are based on specific fields that are used in various combinations, depending on the cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the LPC bus between the host and the LPC47S42x. See the Low Pin Count (LPC) Interface Specification Revision 1.0 from Intel, Section 4.2 for definition of these fields.

nLFRAME Usage

nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal is to be used by the LPC47S42x to know when to monitor the bus for a cycle.

This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the LPC47S42x monitors the bus to determine whether the cycle is intended for it. The use of nLFRAME allows the LPC47S42x to enter a lower power state internally. There is no need for the LPC47S42x to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks.

When the LPC47S42x samples nLFRAME active, it immediately stops driving the LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information.

The nLFRAME signal functions as described in the Low Pin Count (LPC) Interface Specification Reference.

I/O Read and Write Cycles

The LPC47S42x is the target for I/O cycles.

I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times.

Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it up into 8-bit transfers.

See the Low Pin Count (LPC) Interface Specification Reference, Section 5.2, for the sequence of cycles for the I/O Read and Write cycles.

DMA Read and Write Cycles

DMA read cycles involve the transfer of data from the host (main memory) to the LPC47S42x. DMA write cycles involve the transfer of data from the LPC47S42x to the host (main memory). Data will be coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47S42x are 1 byte.

See the Low Pin Count (LPC) Interface Specification Reference, Section 6.4, for the field definitions and the sequence of the DMA Read and Write cycles.

DMA Protocol

DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47S42x and special encodings on LAD[3:0] from the host.

The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Interface Specification Reference.

Power Management

CLOCKRUN Protocol

The nCLKRUN pin is not implemented in the LPC47S42x. See the Low Pin Count (LPC) Interface Specification Reference, Section 8.1.

LPCPD Protocol

See the Low Pin Count (LPC) Interface Specification Reference, Section 8.2.

SYNC Protocol

See the Low Pin Count (LPC) Interface Specification Reference, Section 4.2.1.8 for a

table of valid SYNC values.

Typical Usage

The SYNC pattern is used to add wait states. For read cycles, the LPC47S42x immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47S42x needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The LPC47S42x will choose to assert 0101 or 0110, but not switch between the two patterns.

The data (or wait state SYNC) will immediately follow the 0000 or 1001 value.

The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The LPC47S42x uses a SYNC of 0101 for all wait states in a DMA transfer.

The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47S42x uses a SYNC of 0110 for all wait states in an I/O transfer.

The SYNC value is driven within 3 clocks.

SYNC Timeout

The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it will abort the cycle.

The LPC47S42x does not assume any particular timeout. When the host is driving SYNC, it may have to insert a very large number of wait states, depending on PCI latencies and retries.

SYNC Patterns and Maximum Number of SYNCS

If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is

If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47S42x has protection mechanisms to complete the cycle. This is used for EPP data transfers and will utilize the same timeout protection that is in EPP.

SYNC Error Indication

The LPC47S42x reports errors via the LAD[3:0] = 1010 SYNC encoding.

If the host was reading data from the LPC47S42x, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47S42x. If the host was writing data to the LPC47S42x, the data had already been transferred.

In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not be transferred.

I/O and DMA START Fields I/O and DMA cycles use a START field of 0000.

Reset Policy The following rules govern the reset policy:

1) When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus.

2) When nPCI_RESET goes active (low): a) The host drives the nLFRAME signal

high, tristates the LAD[3:0] signals, and ignores the nLDRQ signal.

b) The LPC47S42x ignores nLFRAME,

tristate the LAD[3:0] pins and drive the nLDRQ signal inactive (high).

LPC Transfers

Wait State Requirements

I/O Transfers

The LPC47S42x inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would normally be deasserted in an ISA transfer (i.e., EPP) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us).

DMA Transfers

The LPC47S42x inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of 0101 is used for all DMA transfers.

Refer to example timing for the LPC cycles in the “Timing Diagrams” section.

FLOPPY DISK CONTROLLER

The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection.

The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.

Table 2 - Status, Data and Control Registers

(Shown with base addresses of 3F0 and 370)

PRIMARY

ADDRESS

3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7

Status Register A (SRA)

Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0.

PS/2 Mode

7 6 5 4 3 2 1 0 INT

RESET COND.

BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction.

SECONDARY

ADDRESS

370 371 372 373 374 374 375 376 377 377

nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR

PENDING

0 1 0 N/A 0 N/A N/A 0

FDC Internal Registers

The Floppy Disk Controller contains eight internal registers that facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected.

R/W

R R/W R/W

R/W

Status Register A (SRA) Status Register B (SRB) Digital Output Register (DOR) Tape Drive Register (TDR) Main Status Register (MSR) Data Rate Select Register (DSR) Data (FIFO) Reserved Digital Input Register (DIR) Configuration Control Register (CCR)

BIT 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected.

BIT 2 nINDEX Active low status of the INDEX disk interface input.

BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side

BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input.

BIT 5 STEP Active high status of the STEP output disk interface output pin.

BIT 6 nDRV2 This function is not supported. This bit is always read as “1”.

BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output.

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0 INT

PENDING RESET COND.

BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction.

BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected.

BIT 2 INDEX Active high status of the INDEX disk interface input.

0 0 0 N/A 1 N/A N/A 1

DRQ STEP

F/F

TRK0 nHDSEL INDX WP nDIR

BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side

BIT 4 TRACK 0 Active high status of the TRK0 disk interface input.

BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset.

BIT 6 DMA REQUEST Active high status of the DMA request pending.

BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt.

Status Register B (SRB)

Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1.

PS/2 Mode

7 6 5 4 3 2 1 0 1 1 DRIVE

SEL0 RESET COND.

BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 2 WRITE GATE Active high status of the WGATE disk interface output.

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

1 1 0 0 0 0 0 0

WDATA

TOGGLE

RDATA

TOGGLE

WGATE MOT

EN1

MOT

EN0

BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset.

BIT 6 RESERVED Always read as a logic "1".

BIT 7 RESERVED Always read as a logic "1".

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0 nDRV2 nDS1 nDS0 WDATA

F/F RESET COND.

BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported.

BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported.

BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register.

BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register.

BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output.

BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported. Digital Output Register (DOR)

Address 3F2 READ/WRITE

N/A 1 1 0 0 0 1 1

RDATA

F/F

WGATE

F/F

nDS3 nDS2

The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time.

7 6 5 4 3 2 1 0 MOT

EN3

RESET

COND.

BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time.

BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and interrupt functions. This bit is a logic "0" after a reset and in these modes.

PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic "0".

BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported.

BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported.

Tape Drive Register (TDR)

Address 3F3 READ/WRITE

MOT

EN2

0 0 0 0 0 0 0 0

MOT

EN1

DRIVE DOR VALUE

0 1

MOT

EN0

DMAEN nRESET DRIVE

1CH 2DH

SEL1

DRIVE

SEL0

The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 3 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset.

Table 3 - Tape Select Bits

TAPE SEL1

(TDR.1)

0 0 1 1

Table 4 - Internal 2 Drive Decode - Normal

DIGITAL OUTPUT

Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X 1 0 0 1 0 nBIT 5 nBIT 4

1 X 0 1 0 1 nBIT 5 nBIT 4

0 0 X X 1 1 nBIT 5 nBIT 4

Table 5 - Internal 2 Drive Decode - Drives 0 and 1 Swapped

DIGITAL OUTPUT

Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X 1 0 0 0 1 nBIT 4 nBIT 5

1 X 0 1 1 0 nBIT 4 nBIT 5

0 0 X X 1 1 nBIT 4 nBIT 5

TAPE SEL0

(TDR.0)

0 1 0 1

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

DRIVE SELECTED

None

1 2 3

MOTOR ON OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Normal Floppy Mode

Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are ‘0’.

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 0 0 0 0 0 0 tape sel1 tape sel0

Enhanced Floppy Mode 2 (OS2)

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive tape sel1 tape sel0

Table 6 - Drive Type ID

DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID

Bit 1 Bit 0 Bit 5 Bit 4

0 0 L0-CRF2 - B1 L0-CRF2 - B0 0 1 L0-CRF2 - B3 L0-CRF2 - B2 1 0 L0-CRF2 - B5 L0-CRF2 - B4 1 1 L0-CRF2 - B7 L0-CRF2 - B6

Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.

Data Rate Select Register (DSR)

Address 3F4 WRITE ONLY

This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps.

7 6 5 4 3 2 1 0 S/W

RESET RESET COND.

BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7 shows the precompensation values for the combination of these bits settings. Track 0 is

POWER

DOWN

0 0 0 0 0 0 1 0

0 PRE-

COMP2

PRE-

COMP1

PRE-

COMP0

DRATE

SEL1

DRATE

SEL0

the default starting track number to start precompensation. This starting track number can be changed by the configure command.

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register.

BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.

Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the runtime register block.

Table 7 - Precompensation Delays

PRECOMP

432

<2Mbps 2Mbps

111 001 010 011 100 101 110 000

Default: See Table 10

PRECOMPENSATION

DELAY (nsec)

0.00

41.67

83.34

125.00

166.67

208.33

250.00 Default

20.8

41.7

62.5

83.3

104.2 125

Default

Table 8 - Data Rates

DRIVE RATE DATA RATE DATA RATE

DENSEL

DRT1 DRT0 SEL1 SEL0 MFM FM 1 0

0 0 1 1 1Meg --- 1 1 1 0 0 0 0 500 250 1 0 0 0 0 0 1 300 150 0 0 1 0 0 1 0 250 125 0 1 0

0 1 1 1 1Meg --- 1 1 1 0 1 0 0 500 250 1 0 0 0 1 0 1 500 250 0 0 1 0 1 1 0 250 125 0 1 0

1 0 1 1 1Meg --- 1 1 1 1 0 0 0 500 250 1 0 0 1 0 0 1 2Meg --- 0 0 1 1 0 1 0 250 125 0 1 0

Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive 10 = 2 Meg Tape Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.

Table 9 - DRVDEN Mapping0

DT1 DT0 DRVDEN1 (1) DRVDEN0 (1) DRIVE TYPE

0 0 DRATE0 DENSEL 4/2/1 MB 3.5"

2/1 MB 5.25" FDDS

2/1.6/1 MB 3.5" (3-MODE) 1 0 DRATE0 DRATE1 0 1 DRATE0 nDENSEL PS/2 1 1 DRATE1 DRATE0

Table 10 - Default Precompensation Delays

DATA RATE

2 Mbps

1 Mbps 500 Kbps 300 Kbps 250 Kbps

PRECOMPENSATIO

N DELAYS

20.8 ns

41.67 ns 125 ns 125 ns 125 ns

DRATE(1)

Main Status Register

Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer.

7 6 5 4 3 2 1 0

RQM

BIT 0 - 1 DRV x BUSY These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates.

BIT 4 COMMAND BUSY This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte.

BIT 5 NON-DMA This mode is selected in the SPECIFY command and will be set to a 1 during the execution phase of a command. This is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes.

BIT 6 DIO Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.

BIT 7 RQM Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.

Data Register (FIFO)

Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register.

Data transfers are governed by the RQM and DIO bits in the Main Status Register.

The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 11 gives several examples of the delays with a FIFO.

The data is based upon the following formula:

Threshold # 1

DIO

x 8

- 1.5 µs = DELAY

NON DMA

CMD

BUSY Reserved Reserved

DRV1 BUSY

DRV0

BUSY

x DATA

RATE

At the start of a command, the FIFO action is always disabled and command parameters are sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred.

An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered.

Table 11 - FIFO Service Delay

FIFO THRESHOLD

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

FIFO THRESHOLD

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

FIFO THRESHOLD

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

Digital Input Register (DIR)

Address 3F7 READ ONLY This register is read-only in all modes.

MAXIMUM DELAY TO SERVICING AT

2 Mbps DATA RATE

1 x 4 µs - 1.5 µs = 2.5 µs 2 x 4 µs - 1.5 µs = 6.5 µs 8 x 4 µs - 1.5 µs = 30.5 µs 15 x 4 µs - 1.5 µs = 58.5 µs

MAXIMUM DELAY TO SERVICING AT

1 Mbps DATA RATE

1 x 8 µs - 1.5 µs = 6.5 µs 2 x 8 µs - 1.5 µs = 14.5 µs 8 x 8 µs - 1.5 µs = 62.5 µs 15 x 8 µs - 1.5 µs = 118.5 µs

MAXIMUM DELAY TO SERVICING AT

500 Kbps DATA RATE

1 x 16 µs - 1.5 µs = 14.5 µs 2 x 16 µs - 1.5 µs = 30.5 µs 8 x 16 µs - 1.5 µs = 126.5 µs 15 x 16 µs - 1.5 µs = 238.5 µs

PC-AT Mode

7 6 5 4 3 2 1 0 DSK

CHG RESET COND.

BIT 0 - 6 UNDEFINED The data bus outputs D0 - 6 are read as ‘0’.

BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).

PS/2 Mode

7 6 5 4 3 2 1 0 DSK

RESET COND.

BIT 0 nHIGH DENS This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected.

BITS 1 - 2 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BITS 3 - 6 UNDEFINED Always read as a logic "1"

Model 30 Mode

7 6 5 4 3 2 1 0 DSK

RESET

COND.

BITS 0 - 1 DATA RATE SELECT

N/A N/A N/A N/A N/A N/A N/A N/A

CHG

N/A N/A N/A N/A N/A N/A N/A 1

CHG

N/A 0 0 0 0 0 1 0

0 0 0 0 0 0 0

1 1 1 1 DRATE

SEL1

0 0 0 DMAEN NOPREC DRATE

DRATE

SEL0

SEL1

nHIGH

nDENS

DRATE

SEL0

These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BIT 2 NOPREC This bit reflects the value of NOPREC bit set in the CCR register.

BIT 3 DMAEN This bit reflects the value of DMAEN bit set in the DOR register bit 3.

BITS 4 - 6 UNDEFINED Always read as a logic "0"

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).

Configuration Control Register (CCR)

Address 3F7 WRITE ONLY PC/AT and PS/2 Modes

7 6 5 4 3 2 1 0 0 0 0 0 0 0 DRATE

SEL1 RESET COND.

BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values.

BIT 2 - 7 RESERVED Should be set to a logical "0".

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0 0 0 0 0 0 NOPREC DRATE

RESET

COND.

BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values.

N/A N/A N/A N/A N/A N/A 1 0

SEL1

DRATE

SEL0

DRATE

SEL0

BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset.

BIT 3 - 7 RESERVED Should be set to a logical "0"

Table 9 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets.

Status Register Encoding

During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed.

Table 12 - Status Register 0

BIT NO. SYMBOL NAME DESCRIPTION

7,6 IC Interrupt Code 00 - Normal termination of command. The specified

command was properly executed and completed without error. 01 - Abnormal termination of command. Command execution was started, but was not successfully completed. 10 - Invalid command. The requested command could not be executed. 11 - Abnormal termination caused by Polling.

5 SE Seek End The FDC completed a Seek, Relative Seek or

Recalibrate command (used during a Sense Interrupt Command).

4 EC Equipment

Check

3 Unused. This bit is always "0". 2 H Head Address The current head address.

1,0 DS1,0 Drive Select The current selected drive.

The TRK0 pin failed to become a "1" after:

1. 80 step pulses in the Recalibrate command.

2. The Relative Seek command caused the FDC to step outward beyond Track 0.

Table 13 - Status Register 1

BIT NO. SYMBOL NAME DESCRIPTION

7 EN End of

Cylinder

6 Unused. This bit is always "0". 5 DE Data Error The FDC detected a CRC error in either the ID field or

4 OR Overrun/

Underrun

3 Unused. This bit is always "0". 2 ND No Data Any one of the following:

1 NW Not Writeable WP pin became a "1" while the FDC is executing a Write

0 MA Missing

Address Mark

The FDC tried to access a sector beyond the final sector of the track (255D). Will be set if TC is not issued after Read or Write Data command.

the data field of a sector. Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in data overrun or underrun.

1. Read Data, Read Deleted Data command - the FDC did not find the specified sector.

2. Read ID command - the FDC cannot read the ID field without an error.

3. Read A Track command - the FDC cannot find the proper sector sequence.

Data, Write Deleted Data, or Format A Track command. Any one of the following:

1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the nINDEX pin twice.

2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track.

Table 14 - Status Register 2

BIT NO. SYMBOL NAME DESCRIPTION

7 Unused. This bit is always "0". 6 CM Control Mark Any one of the following:

Read Data command - the FDC encountered a deleted data address mark. Read Deleted Data command - the FDC encountered a data address mark.

5 DD Data Error in

Data Field

4 WC Wrong

Cylinder 3 Unused. This bit is always "0". 2 Unused. This bit is always "0". 1 BC Bad Cylinder The track address from the sector ID field is different

0 MD Missing Data

Address Mark

Table 15- Status Register 3

BIT NO. SYMBOL NAME DESCRIPTION

7 Unused. This bit is always "0". 6 WP Write

Protected 5 Unused. This bit is always "1". 4 T0 Track 0 Indicates the status of the TRK0 pin. 3 Unused. This bit is always "1". 2 HD Head Address Indicates the status of the HDSEL pin.

1,0 DS1,0 Drive Select Indicates the status of the DS1, DS0 pins.

RESET There are three sources of system reset on the FDC: the nPCI_RESET pin, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state.

All operations are terminated upon a nPCI_RESET, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC.

On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command.

The FDC detected a CRC error in the data field.

The track address from the sector ID field is different from the track address maintained inside the FDC.

from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. The FDC cannot detect a data address mark or a deleted data address mark.

Indicates the status of the WRTPRT pin.

nPCI_RESET Pin (Hardware Reset) The nPCI_RESET pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state.

DOR Reset vs. DSR Reset (Software Reset) These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state.

MODES OF OPERATION The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the state of the Interface Mode bits in LD0-CRF0[3,2].

PC/AT mode The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is an active high signal.

PS/2 mode This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care". The DMA and interrupt functions are always enabled, and DENSEL is active low.

Model 30 mode This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is active low.

DMA Transfers DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a DMA request cycle. DMA read, write and verify cycles are supported. The FDC supports two DMA transfer modes: single Transfer and Burst Transfer. Burst mode is enabled via Logical Device 0-CRF0-Bit[1] (LD0CRF0[1]).

Controller Phases For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections.

Command Phase After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Please refer to Table 16 for the command set descriptions). These bytes of data must be transferred in the order prescribed.

Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next phase as defined by the command definition.

The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" condition.

Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or nonDMA mode as indicated in the Specify command.

After a reset, the FIFO is disabled. Each data byte is transferred by a read/write or DMA cycle depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value.

The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold> is defined as the number of bytes available to the FDC when service is requested from the host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to

15.

A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for use with a "fast" system.

A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests.

Non-DMA Mode - Transfers from the FIFO to the Host

The interrupt and RQM bit in the Main Status Register are activated when the FIFO contains (16<threshold>) bytes or the last bytes of a full sector have been placed in the FIFO. The interrupt can be used for interrupt-driven systems, and RQM can be used for polled systems. The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. The FDC will deactivate the interrupt and RQM bit when the FIFO becomes empty.

Non-DMA Mode - Transfers from the Host to the FIFO

The interrupt and RQM bit in the Main Status Register are activated upon entering the execution phase of data transfer commands. The host must respond to the request by writing data into the FIFO. The interrupt and RQM bit remain true until the FIFO becomes full. They are set true again when the FIFO has <threshold> bytes remaining in the FIFO. The FDC enters the result phase after the last byte is taken by the FDC from the FIFO (i.e. FIFO empty condition).

DMA Mode - Transfers from the FIFO to the Host The FDC generates a DMA request cycle when the FIFO contains (16 - <threshold>) bytes, or the last byte of a full sector transfer has been placed in the FIFO. The DMA controller responds to the request by reading data from the FIFO. The FDC will deactivate the DMA request when the FIFO becomes empty by generating the proper sync for the data transfer.

DMA Mode - Transfers from the Host to the FIFO.

The FDC generates a DMA request cycle when entering the execution phase of the data transfer commands. The DMA controller responds by placing data in the FIFO. The DMA request remains active until the FIFO becomes full. The DMA request cycle is reasserted when the FIFO has <threshold> bytes

remaining in the FIFO. The FDC will terminate the DMA cycle after a TC, indicating that no more data is required.

Data Transfer Termination The FDC supports terminal count explicitly through the TC cycle and implicitly through the underrun/overrun and end-of-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer.

If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector as if a TC cycle was received. The only difference between these implicit functions and TC cycle is that they return "abnormal termination" result status. Such status indications can be ignored if they were expected.

Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay.

Result Phase The generation of the interrupt determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start.

RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command.

Command Set/Descriptions

Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer to Table 16 for explanations of the various symbols used. Table 17 lists the required parameters and the results associated with each command that the FDC is capable of performing.

SYMBOL NAME DESCRIPTION C Cylinder Address The currently selected address; 0 to 255. D Data Pattern The pattern to be written in each sector data field during formatting. D0, D1 Drive Select 0-1 Designates which drives are perpendicular drives on the

DIR Direction Control If this bit is 0, then the head will step out from the spindle during a

Table 16 - Description of Command Symbols

Perpendicular Mode Command. A "1" indicates a perpendicular drive.

relative seek. If set to a 1, the head will step in toward the spindle.

Table 16 - Description of Command Symbols

SYMBOL NAME DESCRIPTION

DS0, DS1 Disk Drive Select DS1 DS0 DRIVE

0 0 Drive 0 0 1 Drive 1

DTL Special Sector

Size

EC Enable Count When this bit is "1" the "DTL" parameter of the Verify command

EFIFO Enable FIFO This active low bit when a 0, enables the FIFO. A "1" disables the

EIS Enable Implied

Seek

EOT End of Track The final sector number of the current track. GAP Alters Gap 2 length when using Perpendicular Mode. GPL Gap Length The Gap 3 size. (Gap 3 is the space between sectors excluding the

H/HDS Head Address Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID

HLT Head Load Time The time interval that FDC waits after loading the head and before

HUT Head Unload

Time

LOCK Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of

MFM MFM/FM Mode

Selector

MT Multi-Track

Selector

By setting N to zero (00), DTL may be used to control the number of bytes transferred in disk read/write commands. The sector size (N =

0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX.

becomes SC (number of sectors per track).

FIFO (default). When set, a seek operation will be performed before executing any read or write command that requires the C parameter in the command phase. A "0" disables the implied seek.

VCO synchronization field).

field.

initializing a read or write operation. Refer to the Specify command for actual delays. The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command for actual delays.

the CONFIGURE COMMAND can be reset to their default values by a "software Reset". (A reset caused by writing to the appropriate bits of either the DSR or DOR) A one selects the double density (MFM) mode. A zero selects single density (FM) mode. When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0.

Table 16 - Description of Command Symbols

SYMBOL NAME DESCRIPTION

N Sector Size Code This specifies the number of bytes in a sector. If this parameter is

"00", then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive. N SECTOR SIZE 00 128 Bytes 01 256 Bytes 02 512 Bytes 03 1024 Bytes … … 07 16K Bytes

NCN New Cylinder

Number

ND Non-DMA Mode

Flag

OW Overwrite The bits D0-D3 of the Perpendicular Mode Command can only be

PCN Present Cylinder

Number

POLL Polling Disable When set, the internal polling routine is disabled. When clear, polling

PRETRK Precompensation

Start Track Number

R Sector Address The sector number to be read or written. In multi-sector transfers,

RCN Relative Cylinder

Number

SC Number of

Sectors Per Track

SK Skip Flag When set to 1, sectors containing a deleted data address mark will

SRT Step Rate Interval The time interval between step pulses issued by the FDC.

The desired cylinder number.

When set to 1, indicates that the FDC is to operate in the non-DMA mode. In this mode, the host is interrupted for each data transfer. When set to 0, the FDC operates in DMA mode.

modified if OW is set to 1. OW id defined in the Lock command. The current position of the head at the completion of Sense Interrupt Status command.

is enabled. Programmable from track 00 to FFH.

this parameter specifies the sector number of the first sector to be read or written. Relative cylinder offset from present cylinder as used by the Relative Seek command. The number of sectors per track to be initialized by the Format command. The number of sectors per track to be verified during a Verify command when EC is set.

automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to "0", the sector is read or written the same as the read and write commands.

Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to the SPECIFY command for actual delays.

Table 16 - Description of Command Symbols

SYMBOL NAME DESCRIPTION

ST0 ST1 ST2 ST3 WGATE Write Gate Alters timing of WE to allow for pre-erase loads in perpendicular

Status 0 Status 1 Status 2 Status 3

Registers within the FDC which store status information after a command has been executed. This status information is available to the host during the result phase after command execution.

drives.

Instruction Set

READ DATA

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 0 1 1 0 Command Codes W 0 0 0 0 0 HDS DS1 DS0 W ──────── C ──────── Sector ID information prior to

W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ─────── DTL ─────── Execution Data transfer between the

Result R ─────── ST0 ─────── Status information after Com-

R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information after

R ──────── H ──────── R ──────── R ──────── R ──────── N ────────

Table 17 - Instruction Set

DATA BUS

Command execution.

FDD and system.

mand execution.

Command execution.

READ DELETED DATA

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 1 1 0 0 Command Codes W 0 0 0 0 0 HDS DS1 DS0 W ──────── C ──────── Sector ID information prior to

Result R ─────── ST0 ─────── Status information after Com-

R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information after

R ──────── H ──────── R ──────── R ──────── R ──────── N ────────

DATA BUS

Command execution.

FDD and system.

mand execution.

Command execution.

WRITE DATA

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 0 1 0 1 Command Codes W 0 0 0 0 0 HDS DS1 DS0 W ──────── C ──────── Sector ID information prior to

Result R ─────── ST0 ─────── Status information after Com-

R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information after

R ──────── H ──────── R ──────── R ──────── R ──────── N ────────

DATA BUS

Command execution.

FDD and system.

mand execution.

Command execution.

WRITE DELETED DATA

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 1 0 0 1 Command Codes W 0 0 0 0 0 HDS DS1 DS0 W ──────── C ──────── Sector ID information

W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ─────── DTL ─────── Execution Data transfer between

Result R ─────── ST0 ─────── Status information after

R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information

R ──────── H ──────── R ──────── R ──────── R ──────── N ────────

DATA BUS

prior to Command execution.

the FDD and system.

Command execution.

after Command execution.

READ A TRACK

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 0 0 1 0 Command Codes W 0 0 0 0 0 HDS DS1 DS0 W ──────── C ──────── Sector ID information

Result R ─────── ST0 ─────── Status information after

R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information

R ──────── H ──────── R ──────── R ──────── R ──────── N ────────

DATA BUS

prior to Command execution.

the FDD and system. FDC reads all of cylinders' contents from index hole to EOT.

Command execution.

after Command execution.

VERIFY

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 1 0 1 1 0 Command Codes W EC 0 0 0 0 HDS DS1 DS0 W ──────── C ──────── Sector ID information

W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ────── DTL/SC ────── Execution No data transfer takes

Result R ─────── ST0 ─────── Status information after

R ─────── ST1 ─────── R ─────── ST2 ─────── R ──────── C ──────── Sector ID information

R ──────── H ──────── R ──────── R ──────── R ──────── N ────────

VERSION

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 0 0 Command Code Result R 1 0 0 1 0 0 0 0 Enhanced Controller

DATA BUS

prior to Command execution.

place.

Command execution.

after Command execution.

FORMAT A TRACK

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 1 0 1 Command Codes W 0 0 0 0 0 HDS DS1 DS0 W ──────── N ──────── Bytes/Sector W ──────── SC ──────── Sectors/Cylinder W ─────── GPL ─────── Gap 3 W ──────── D ──────── Filler Byte

Execution for Each Sector Repeat: W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── FDC formats an entire

Result R ─────── ST0 ─────── Status information after

R ─────── ST1 ─────── R ─────── ST2 ─────── R ────── Undefined ────── R ────── Undefined ────── R ────── Undefined ────── R ────── Undefined ──────

W ──────── C ──────── Input Sector Parameters

DATA BUS

cylinder

Command execution

RECALIBRATE

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 1 1 1 Command Codes W 0 0 0 0 0 0 DS1 DS0 Execution Head retracted to Track 0

SENSE INTERRUPT STATUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 0 0 0 Command Codes Result R ─────── ST0 ─────── Status information at the end

R ─────── PCN ───────

SPECIFY

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 0 1 1 Command Codes W ─── SRT ─── ─── HUT ─── W ────── HLT ────── ND

DATA BUS

Interrupt.

of each seek operation.

SENSE DRIVE STATUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 1 0 0 Command Codes W 0 0 0 0 0 HDS DS1 DS0 Result R ─────── ST3 ─────── Status information about

SEEK

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 1 1 1 Command Codes W 0 0 0 0 0 HDS DS1 DS0 W ─────── NCN ─────── Execution Head positioned over

CONFIGURE

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 1 1 Configure

W 0 0 0 0 0 0 0 0 W 0 EIS EFIFO POLL ─── FIFOTHR ─── Execution W ───────── PRETRK ─────────

DATA BUS

FDD

proper cylinder on diskette.

Information

RELATIVE SEEK

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 1 DIR 0 0 1 1 1 1 W 0 0 0 0 0 HDS DS1 DS0 W ─────── RCN ───────

DUMPREG

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 1 1 0 *Note:

Execution Result R ────── PCN-Drive 0 ─────── R ────── PCN-Drive 1 ─────── R ────── PCN-Drive 2 ─────── R ────── PCN-Drive 3 ─────── R ──── SRT ──── ─── HUT ─── R ─────── HLT ─────── ND R ─────── SC/EOT ─────── R LOCK 0 D3 D2 D1 D0 GAP WGATE R 0 EIS EFIFO POLL ── FIFOTHR ── R ──────── PRETRK ────────

DATA BUS

Registers placed in FIFO

READ ID

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 0 1 0 Commands W 0 0 0 0 0 HDS DS1 DS0 Execution The first correct ID

Result R

R R R R R R

──────── ST0 ────────

DATA BUS

ST1 ST2

C H R N

information on the Cylinder is stored in Data Register Status information after Command execution.

PERPENDICULAR MODE

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 1 0 Command Codes OW 0 D3 D2 D1 D0 GAP WGATE

INVALID CODES

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W ───── Invalid Codes ───── Invalid Command Codes

Result R ─────── ST0 ─────── ST0 = 80H

LOCK

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W LOCK 0 0 1 0 1 0 0 Command Codes Result R 0 0 0 LOCK 0 0 0 0

SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write.

Note: These bits are used internally only. They are not reflected in the Drive Select pins. It is the user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).

DATA BUS

(NoOp - FDC goes into Standby State)

Data Transfer Commands All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte.

An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of the command. If the seek portion fails, it is reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed.

Read Data A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette matches with the sector address specified in the command, the FDC reads the sector's data field and transfers the data to the FIFO.

After completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO. This continuous read function is called "Multi-Sector Read Operation". Upon receipt of the TC cycle, or an implied TC (FIFO overrun/underrun), the FDC stops sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read Data Command.

N determines the number of bytes per sector (see Table 18 below). If N is set to zero, the sector size is set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred.

Table 18 - Sector Sizes N SECTOR SIZE

00 01 02 03

The amount of data which can be handled with a single command to the FDC depends upon MT (multitrack) and N (number of bytes/sector).

The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1.

If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 19.

128 bytes 256 bytes 512 bytes

1024 bytes

...

16 Kbytes

At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads.

If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the ND bit in Status Register 1 to "1" indicating a sector not found, and terminates the Read Data Command. After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or data field, the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the DE bit flag in Status Register 1 to "1", sets the DD bit in Status Register 2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 21 describes the effect of the SK bit on the Read Data command execution and results. Except where noted in Table 20, the C or R value of the sector address is automatically incremented (see Table 22).

Table 19 - Effects of MT and N Bits

MT N

0 1 0 1 0 1

Table 20 - Skip Bit vs Read Data Command

SK BIT

VALUE

SECTOR

0 Normal Data Yes No Normal

0 Deleted Data Yes Yes Address not

1 Normal Data Yes No Normal

1 Deleted Data No Yes Normal

Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field.

Table 21 describes the effect of the SK bit on the Read Deleted Data command execution and results.

DATA ADDRESS

ENCOUNTERED

MAXIMUM TRANSFER

CAPACITY

256 x 26 = 6,656

256 x 52 = 13,312

512 x 15 = 7,680

512 x 30 = 15,360

1024 x 8 = 8,192

1024 x 16 = 16,384

MARK TYPE

READ?

FINAL SECTOR READ

FROM DISK

26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1

RESULTS

CM BIT OF

ST2 SET?

DESCRIPTION OF

RESULTS

termination.

incremented. Next sector not searched for.

termination.

termination. Sector not read ("skipped").

Except where noted in Table 21, the C or R value of the sector address is automatically incremented (see Table 22).

Table 21 - Skip Bit vs. Read Deleted Data Command

SK BIT

VALUE

SECTOR

Read A Track This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. The FDC compares the ID information read from each sector with the specified value in the command and sets the ND flag of Status Register 1 to a “1” if there no comparison. Multi-track or skip operations are not allowed with this command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be set to "0".

This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the nINDEX pin, then it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command.

DATA ADDRESS

MARK TYPE

ENCOUNTERED

Normal Data

Deleted Data

Normal Data

Deleted Data

READ?

Yes

CM BIT OF

ST2 SET?

RESULTS

Yes

DESCRIPTION OF

RESULTS

Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read ("skipped"). Normal termination.

Table 22 - Result Phase

0 0 Less than EOT NC NC R + 1 NC

Equal to EOT C + 1 NC 01 NC

1 Less than EOT NC NC R + 1 NC

Equal to EOT C + 1 NC 01 NC

1 0 Less than EOT NC NC R + 1 NC

Equal to EOT NC LSB 01 NC

1 Less than EOT NC NC R + 1 NC

Equal to EOT C + 1 LSB 01 NC

NC: No Change, the same value as the one at the beginning of command execution.

LSB: Least Significant Bit, the LSB of H is complemented.

Write Data After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via the FIFO and writes it to the sector's data field.

After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of the sector transfer. The Sector Number stored in "R" is incremented by one, and the FDC continues writing to the next data field. The FDC continues this "Multi-Sector Write Operation". Upon receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the DE bit of Status Register 1 to "1", and terminates the Write Data command.

The Write Data command operates in much the same manner as the Read Data command. The following items are the same. Please refer to the Read Data Command for details:

Transfer Capacity EN (End of Cylinder) bit ND (No Data) bit Head Load, Unload Time Interval ID information when the host terminates the command

Definition of DTL when N = 0 and when N does not = 0 Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk.

Verify

HEAD

FINAL SECTOR

TRANSFERRED TO

HOST C H R N

ID INFORMATION AT RESULT PHASE

The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the previously-stored value.

Because data is not transferred to the host, the TC cycle cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to "0" and the EOT value equal to the final sector to be checked. If EC is set to "0", DTL/SC should be programmed to 0FFH. Refer to Table 22 and Table 23 for information concerning the values of MT and EC versus SC and EOT value.

Definitions:

# Sectors Per Side = Number of formatted sectors per each side of the disk.

# Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to "1".

Table 23 - Verify Command Result Phase

MT EC SC/EOT VALUE TERMINATION RESULT

0 0 SC = DTL

EOT ≤ # Sectors Per Side

0 0 SC = DTL

EOT > # Sectors Per Side

0 1

0 1 SC > # Sectors Remaining OR

1 0 SC = DTL

1 1

1 1 SC > # Sectors Remaining OR

Note: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on

Side 0, verifying will continue on Side 1 of the disk.

Format A Track The Format command allows an entire track to be formatted. After a pulse from the nINDEX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled by the values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively).

After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the nINDEX pin again and it terminates the command.

Table 24 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics.

SC ≤ # Sectors Remaining AND EOT ≤ # Sectors Per Side

EOT > # Sectors Per Side

EOT ≤ # Sectors Per Side

EOT > # Sectors Per Side SC ≤ # Sectors Remaining AND EOT ≤ # Sectors Per Side

EOT > # Sectors Per Side

Success Termination Result Phase Valid

Unsuccessful Termination Result Phase Invalid Successful Termination Result Phase Valid

Unsuccessful Termination Result Phase Invalid

FORMAT FIELDS

SYSTEM 34 (DOUBLE DENSITY) FORMAT

IDAM C

SYNC

12x

SYSTEM 3740 (SINGLE DENSITY) FORMAT

SYNC

6x 00

SYNC

12x

Y L

IDAM C

Y L

PERPENDICULAR FORMAT

IDAM C

Y L

SYNC

GAP4a

80x

GAP4a

SYNC

40x

FC FE FB or

GAP4a

SYNC

80x

12x

6x 00

12x

IAM GAP1

50x

FC 3xA1FE 3xA1FBF8

IAM GAP1

26x

IAM GAP1

50x

FC 3xA1FE 3xA1FBF8

E C

C R C

GAP2

22x

GAP2

11x

GAP2

41x

SYNC

12x

SYNC

6x 00

SYNC

12x

DATA

GAP3

R C

C R

GAP3

C R

GAP3

GAP 4b

Table 24 - Typical Values for Formatting

FORMAT SECTOR SIZE N SC GPL1 GPL2

5.25"

Drives

3.5"

Drives

GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. NOTE: All values except sector size are in hex.

MFM

128 128

512 1024 2048 4096

... 256 256

512* 1024 2048 4096

... 128 256 512 256

512**

1024

00 00 02 03 04 05

... 01 01 02 03 04 05

...

0 1 2 1 2 3

12 10 08 04 02 01

12 10 09 04 02 01

09 05

07 10 18

46 C8 C8

20 2A

80 C8 C8

0F 1B 0E 1B

09 19 30

87 FF FF

F0 FF FF

1B 2A 3A

Control Commands

Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt.

Read ID

The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command.

The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost.

Recalibrate

This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter and checks the status of the nTRK0 pin from the FDD. As long as the nTRK0 pin is low, the DIR pin remains 0 and step pulses are issued. When the nTRK0 pin goes high, the SE bit in Status Register 0 is set to "1" and the command is terminated. If the nTRK0 pin is still low after 79 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to "1" and terminates the command. Disks capable of handling more than 80 tracks per side may require more than one Recalibrate command to return the head back to physical Track 0.

The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after the Recalibrate command to effectively terminate it and to provide verification of the head position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once. Upon power up, the software must issue a Recalibrate command to properly initialize all drives and the controller.

Seek

The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a difference:

PCN < NCN: Direction signal to drive set to "1" (step in) and issues step pulses. PCN > NCN: Direction signal to drive set to "0" (step out) and issues step pulses.

The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to "1" and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the

NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once.

Note that if implied seek is not enabled, the read and write commands should be preceded by:

1) Seek command - Step to the proper track

2) Sense Interrupt Status command - Terminate the Seek command

3) Read ID - Verify head is on proper track

4) Issue Read/Write command.

The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense Interrupt Status command is issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that the user service all pending interrupts through the Sense Interrupt Status command.

Sense Interrupt Status

An interrupt signal is generated by the FDC for one of the following reasons:

1. Upon entering the Result Phase of: a. Read Data command b. Read A Track command c. Read ID command d. Read Deleted Data command e. Write Data command f. Format A Track command g. Write Deleted Data command h. Verify command

2. End of Seek, Relative Seek, or Recalibrate command

3. FDC requires a data transfer during the execution phase in the non-DMA mode

The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt.

Table 25 - Interrupt Identification

SE IC INTERRUPT DUE TO

0 1

1 The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit in ST0 will always return a "0". If a Sense Interrupt Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command.

Sense Drive Status

Polling

Normal termination of Seek or Recalibrate command Abnormal termination of Seek

or Recalibrate command

Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information.

Specify The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT (Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. The values change with the data rate speed selection and are documented in Table 26. The values are the same for MFM and FM.

The choice of DMA or non-DMA operations is made by the ND bit. When this bit is "1", the non-DMA mode is selected, and when ND is "0", the DMA mode is selected. In DMA mode, data transfers are signaled by the DMA request cycles. Non-DMA mode uses the RQM bit and the interrupt to signal data transfers.

Configure The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements.

Table 26 - Drive Control Delays (ms)

256

.. 224 240

HUT

128

1 2

.. 126 127

426

26.7 ..

373 400

512

.. 448 480

256

2 4

.. 252 254

3.75 ..

0.5

0.25

7.5 .. 1

0.5

HLT

426

3.3

6.7

420 423

2M 1M 500K 300K 250K 2M 1M 500K 300K 250K

64 1 ..

56 F

00 01 02

7F 7F

Configure Default Values:

EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0

EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek.

128

.. 112 120

2M 1M 500K 300K 250K

0.5 1 ..

63.5

SRT

26.7

25 .. 2 1

3.33

1.67

32 30

.. 4 2

512

4 8

. 504 508

EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis. Defaults to "1", FIFO disabled. The threshold defaults to "1".

POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired.

FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes.

PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track

0. A "00" selects track 0; "FF" selects track 255.

Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value of 90 H is returned as the result byte.

Relative Seek The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit.

DIR Head Step Direction Control

RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the

current track number.

DIR ACTION

0 1 Step Head Out

Step Head In

The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped with other Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0.

As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and the head is on any track (0-255). If a Seek command is issued, the head will stop at track 255. If a Relative Seek command is issued, the FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the maximum track that the FDC could position the head on using Relative Seek will be 295 (D), the initial track + 255 (D). The maximum count that the head can be moved with a single Relative Seek command is 255 (D).

The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the track number goes above 255 (D). It is the user's responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is working in an "extended track area" (greater than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the "extended track area". It is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area.

To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary.

A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results which may be difficult to keep track of with software without the Read ID command.

Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 27 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0).

Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The user must ensure that these two data rates remain consistent.

The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The format field shown on Page 58 illustrates the change in the Gap2 field size for the perpendicular format.

On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation.

For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC. With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0).

It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged.

The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values.

When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply:

1. The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate.

2. The write pre-compensation given to a perpendicular mode drive will be 0ns.

3. For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation.

Note: Bits D0-D3 can only be overwritten when OW is programmed as a "1".If either GAP or WGATE is a

"1" then D0-D3 are ignored.

Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND:

1. "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value.

2. "Hardware" resets will clear all bits

(GAP, WGATE and D0-D3) to "0", i.e all conventional mode.

Table 27 - Effects of WGATE and GAP Bits

WGATE

0 0

LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should be used.

The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware" RESET from the nPCI_RESET pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte.

Enhanced DUMPREG The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands.

GAP

0 1

MODE Conventional Perpendicular (500 Kbps) Reserved (Conventional) Perpendicular (1 Mbps)

LENGTH OF

GAP2 FORMAT

FIELD

22 Bytes 22 Bytes

22 Bytes

41 Bytes

PORTION OF

GAP 2 WRITTEN BY WRITE DATA

OPERATION

0 Bytes

19 Bytes

0 Bytes

38 Bytes

Compatibility The LPC47S42x was designed with software compatibility in mind. It is a fully backwards- compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS.

Direct Support for Two Floppy Drives The nMTR1 function is on pin 43. nMTR1 is the second alternate function on the GP22 pin. Pin 43 has the IO12 buffer type.

The nMTR1 function is selectable as open drain or push pull as nMTR0 is through bit 6 of the FDD Mode Register in CRF0 of LD 0. This overrides the selection of the output type through bit 7 of the GPIO control register. It is also controlled by bit 7 of the FDD Mode Register.

The nDS1 function is on pin 41. nDS1 is the second alternate function on the GP20 pin. Pin 41 has IO12 buffer type.

The nDS1 function is selectable as open drain or push pull as nDS0 is through bit 6 of the FDD Mode Register in CRF0 of LD 0. This overrides the selection of the output type through bit 7 of the GPIO control register. It is also controlled by bit 7 of the FDD Mode register.

See the Runtime Registers section for register information.

Disk Change Support for Second Floppy Bit[1] in the Force Disk Change register supports the second floppy. Setting either of the Force Disk Change bits active forces the internal FDD nDSKCHG active when the appropriate drive has been selected. The Force Disk Change register is defined in the Runtime Registers section.

Force Write Protect Support for Second Floppy Bit[0] in the Device Disable register and FDD Option register support floppy write protect.

See the Runtime Registers section for Device Disable register description and the Configuration Registers section for FDD Option register description.

SERIAL PORT (UART)

The LPC47S42x incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, power down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UART's interrupt. The second UART also supports IrDA 1.0, HP-SIR, ASK-IR infrared modes of operation.

Note: The UARTs 1 and 2 may be configured to share an interrupt. Refer to the Configuration section for more information.

Register Description Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see Configuration section). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The LPC47S42x contains two serial ports, each of which contain a register set as described below.

Table 28 - Addressing the Serial Port

DLAB* A2 A1 A0 REGISTER NAME

0 0 0 0 Receive Buffer (read) 0 0 0 0 Transmit Buffer (write) 0 0 0 1 Interrupt Enable (read/write) X 0 1 0 Interrupt Identification (read) X 0 1 0 FIFO Control (write) X 0 1 1 Line Control (read/write) X 1 0 0 Modem Control (read/write) X 1 0 1 Line Status (read/write) X 1 1 0 Modem Status (read/write) X 1 1 1 Scratchpad (read/write) 1 0 0 0 Divisor LSB (read/write) 1 0 0 1 Divisor MSB (read/write *Note: DLAB is Bit 7 of the Line Control Register

The following section describes the operation of the registers.

Receive Buffer Register (RB)

Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible.

Transmit Buffer Register (TB)

Address Offset = 0H, DLAB = 0, WRITE ONLY

This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete. Interrupt Enable Register (IER)

Address Offset = 1H, DLAB = 0, READ/WRITE

The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47S42x. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below.

Bit 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1".

Bit 1 This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1".

Bit 2

This bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source.

Bit 3 This bit enables the MODEM Status Interrupt when set to logic "1". This is caused when one of the Modem Status Register bits changes state.

Bits 4 through 7 These bits are always logic "0".

FIFO Control Register (FCR) Address Offset = 2H, DLAB = X, WRITE

This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported. The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x1D). Bit 0 Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0" disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed.

Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing.

Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing.

Bit 3 Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip.

Bit 4,5

Reserved

Bit 6,7 These bits are used to set the trigger level for the RCVR FIFO interrupt.

Bit 7

0 0 1 0 1 4 1 0 8 1 1 14

Interrupt Identification Register (IIR) Address Offset = 2H, DLAB = X, READ

By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority:

1. Receiver Line Status (highest priority)

2. Received Data Ready

3. Transmitter Holding Register Empty

4. MODEM Status (lowest priority)

Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR are described below.

Bit 6

RCVR FIFO

Trigger Level (BYTES)

Bit 0

This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending.

Bits 1 and 2 These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table.

Bit 3 In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending.

Bits 4 and 5 These bits of the IIR are always logic "0".

Bits 6 and 7 These two bits are set when the FIFO CONTROL Register bit 0 equals 1.

Table 29 - Interrupt Control

FIFO

MODE

ONLY

BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 1 - None None 0 1 1 0 Highest Receiver Line

0 1 0 0 Second Received Data

1 1 0 0 Second Character

0 0 1 0 Third Transmitter

INTERRUPT

IDENTIFICATION

PRIORITY

LEVEL

INTERRUPT SET AND RESET FUNCTIONS

INTERRUPT

TYPE

Status

Available

Timeout Indication

Holding Register Empty

INTERRUPT

SOURCE

Overrun Error, Parity Error, Framing Error or Break Interrupt Receiver Data Available

No Characters Have Been Removed From or Input to the RCVR FIFO during the last 4 Char times and there is at least 1 char in it during this time Transmitter Holding Register Empty

INTERRUPT

CONTROL

Reading the Line Status Register

Read Receiver Buffer or the FIFO drops below the trigger level. Reading the Receiver Buffer Register

Reading the IIR Register (if Source of Interrupt) or Writing the Transmitter

RESET

FIFO

MODE

ONLY

BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 0 Fourth MODEM

Line Control Register (LCR)

Address Offset = 3H, DLAB = 0, READ/WRITE

INTERRUPT

IDENTIFICATION

PRIORITY

LEVEL

INTERRUPT SET AND RESET FUNCTIONS

INTERRUPT

Status

TYPE

INTERRUPT

SOURCE

Clear to Send or Data Set Ready or Ring Indicator or Data Carrier Detect

INTERRUPT

RESET

CONTROL

Holding Register Reading the MODEM Status Register

Start LSB Data 5-8 bits MSB Parity Stop

FIGURE 1 - SERIAL DATA

This register contains the format information of the serial line. The bit definitions are:

Bits 0 and 1

These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows: The Start, Stop and Parity bits are not included in the word length.

BIT 1 BIT 0 WORD LENGTH

0 0 1 1

0 1 0 1

5 Bits 6 Bits 7 Bits 8 Bits

Bit 2

This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information.

BIT 2 WORD LENGTH

0 -- 1 1 5 bits 1.5 1 6 bits 2 1 7 bits 2 1 8 bits 2

Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.

Bit 3

Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed).

Bit 4

Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked.

Bit 5

Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or Space Parity. When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as 0 (Space Parity). If bits 3 and 5 are 1 and bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark Parity). If bit 5 is 0 Stick Parity is disabled.

Bit 6

Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the Spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system.

Bit 7

Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register.

Modem Control Register (MCR)

Address Offset = 4H, DLAB = X, READ/WRITE

This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below.

Bit 0

This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1".

NUMBER OF

STOP BITS

Bit 1

This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0.

Bit 2

This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU.

Bit 3

Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled.

Bit 4

This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occur:

1. The TXD is set to the Marking State (logic "1").

2. The receiver Serial Input (RXD) is disconnected.

3. The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input.

4. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected.

5. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI, DCD).

6. The Modem Control output pins are forced inactive high.

7. Data that is transmitted is immediately received.

This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register.

Bits 5 through 7

These bits are permanently set to logic zero.

Line Status Register (LSR)

Address Offset = 5H, DLAB = X, READ/WRITE

Bit 0

Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all of the data in the Receive Buffer Register or the FIFO.

Bit 1

Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrunn error will occur only when the FIFO is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the Line Status Register is read.

Bit 2

Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO.

Bit 3

Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'.

Bit 4

Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be logic "1" for at least 1/2 bit time.

Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled.

Bit 5

Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic "0" whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is a read only bit.

Bit 6

Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty.

Bit 7

This bit is permanently set to logic "0" in the 450 mode. In the FIFO mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO.

Modem Status Register (MSR)

Address Offset = 6H, DLAB = X, READ/WRITE

This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read.

Bit 0

Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read.

Bit 1

Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read.

Bit 2

Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to logic "1".

Bit 3

Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state.

Note: Whenever bit 0, 1, 2, or 3 is set to a logic "1", a MODEM Status Interrupt is generated.

Bit 4

This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR.

Bit 5

This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to DTR in the MCR.

Bit 6

This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR.

Bit 7

This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT2 in the MCR.

Scratchpad Register (SCR)

Address Offset =7H, DLAB =X, READ/WRITE

This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily.

Programmable Baud Rate Generator (AND Divisor Latches DLH, DLL) The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal PLL clock by any divisor from 1 to 65535. The internal PLL clock is divided down to generate a 1.8462MHz frequency for Baud Rates less than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz frequency for

230.4k and a 7.3728MHz frequency for 460.8k. This output frequency of the Baud Rate Generator is 16x

the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock.

Table 30 shows the baud rates possible.

Effect Of The Reset on Register File The Reset Function Table (Table 31) details the effect of the Reset input on each of the registers of the Serial Port.

FIFO Interrupt Mode Operation When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows:

A. The receive data available interrupt will be issued when the FIFO has reached its programmed trigger

level; it is cleared as soon as the FIFO drops below its programmed trigger level.

B. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is

cleared when the FIFO drops below the trigger level.

C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available

(IIR=04H) interrupt.

D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the

RCVR FIFO. It is reset when the FIFO is empty.

When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows:

A. A FIFO timeout interrupt occurs if all the following conditions exist:

- At least one character is in the FIFO.

- The most recent serial character received was longer than 4 continuous character times ago. (If 2

stop bits are programmed, the second one is included in this time delay).

- The most recent CPU read of the FIFO was longer than 4 continuous character times ago.

- This will cause a maximum character received to interrupt issued delay of 160 msec at 300

BAUD with a 12 bit character.

B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay

proportional to the baudrate).

C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one

character from the RCVR FIFO.

D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or

after the CPU reads the RCVR FIFO.

When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows:

A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as

soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read.

B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time

whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.

Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.

FIFO Polled Mode Operation With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows:

- Bit 0=1 as long as there is one byte in the RCVR FIFO.

- Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same

way as when in the interrupt mode, the IIR is not affected since EIR bit 2=0.

- Bit 5 indicates when the XMIT FIFO is empty.

- Bit 6 indicates that both the XMIT FIFO and shift register are empty.

- Bit 7 indicates whether there are any errors in the RCVR FIFO.

There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters.

Table 30 - Baud Rates

DESIRED

BAUD RATE

DIVISOR USED TO

GENERATE 16X CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL

SPEED BIT

HIGH

50 2304 0.001 X 75 1536 - X 110 1047 - X

134.5 857 0.004 X 150 768 - X 300 384 - X 600 192 - X

1200 96 - X 1800 64 - X 2000 58 0.005 X 2400 48 - X 3600 32 - X 4800 24 - X 7200 16 - X

9600 12 - X 19200 6 - X 38400 3 0.030 X 57600 2 0.16 X

115200 1 0.16 X 230400 32770 0.16 1 460800 32769 0.16 1

: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.

Note

: The High Speed bit is located in the Device Configuration Space.

Table 31 - Reset Function

Interrupt Enable Register RESET All bits low Interrupt Identification Reg. RESET Bit 0 is high; Bits 1 - 7 low FIFO Control RESET All bits low Line Control Reg. RESET All bits low MODEM Control Reg. RESET All bits low Line Status Reg. RESET All bits low except 5, 6 high MODEM Status Reg. RESET Bits 0 - 3 low; Bits 4 - 7 input TXD1, TXD2 RESET High INTRPT (RCVR errs) RESET/Read LSR Low INTRPT (RCVR Data Ready) RESET/Read RBR Low INTRPT (THRE) RESET/ReadIIR/Write THR Low OUT2B RESET High RTSB RESET High DTRB RESET High OUT1B RESET High RCVR FIFO RESET/

FCR1*FCR0/_FCR0

XMIT FIFO RESET/

FCR1*FCR0/_FCR0

All Bits Low

Table 32 - Register Summary for an Individual UART Channel

ADDRESS*

ADDR = 0 DLAB = 0

ADDR = 1 DLAB = 0

ADDR = 2

ADDR = 2 FIFO Control

ADDR = 3

ADDR = 4

ADDR = 5

ADDR = 6

ADDR = 7 Scratch Register

ADDR = 0 DLAB = 1 ADDR = 1 DLAB = 1

*DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.

Receive Buffer Register (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register

Interrupt Ident. Register (Read Only)

MODEM Control Register Line Status Register MODEM Status Register

(Note 4) Divisor Latch (LS) DDL Bit 0 Bit 1

Divisor Latch (MS) DLM Bit 8 Bit 9

SYMBOL

FCR (Note

RBR Data Bit 0 (Note

THR Data Bit 0 Data Bit 1

IER Enable

Received Data Available Interrupt (ERDAI)

IIR "0" if Interrupt

Pending

FIFO Enable RCVR FIFO Reset

LCR Word Length

Select Bit 0 (WLS0)

MCR Data Terminal

Ready (DTR)

LSR Data Ready

(DR)

MSR Delta Clear to

Send (DCTS)

SCR Bit 0 Bit 1

BIT 0

Data Bit 1

Enable Transmitter Holding Register Empty Interrupt (ETHREI)

Interrupt ID Bit

Word Length Select Bit 1 (WLS1)

Request to Send (RTS)

Overrun Error (OE)

Delta Data Set Ready (DDSR)

BIT 1

Table 32 - Register Summary for an Individual UART Channel (continued)

BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Enable Receiver Line Status Interrupt (ELSI) Interrupt ID Bit Interrupt ID Bit

XMIT FIFO Reset

Number of Stop Bits (STB) OUT1 (Note 3) Parity Error (PE)

Trailing Edge Ring Indicator (TERI) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15

Note 3: This bit no longer has a pin associated with it. Note 4: When operating in the XT mode, this register is not available. Note 5: These bits are always zero in the non-FIFO mode. Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip. Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register

(runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x1D).

Enable MODEM Status Interrupt (EMSI)

(Note 5)

DMA Mode Select (Note

6) Parity Enable (PEN)

OUT2 (Note 3) Framing Error (FE)

Delta Data Carrier Detect (DDCD)

0 0 0 0

0 0 FIFOs

Enabled (Note 5)

Reserved Reserved RCVR Trigger

LSB

Even Parity Select (EPS)

Loop 0 0 0

Break Interrupt (BI)

Clear to Send (CTS)

Stick Parity Set Break Divisor Latch

Transmitter Holding Register (THRE) Data Set Ready (DSR)

Transmitter Empty (TEMT) (Note 2)

Ring Indicator (RI)

FIFOs Enabled (Note 5) RCVR Trigger MSB

Access Bit (DLAB)

Error in RCVR FIFO (Note 5)

Data Carrier Detect (DCD)

Notes On Serial Port Operation

FIFO Mode Operation

GENERAL

The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.

TX AND RX FIFO Operation The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx.

The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt.

after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have the Tx FIFO empties after this condition, the Tx been loaded into the FIFO, concurrently. When interrupt will be activated without a one character delay.

Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs.

One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART.

software from having to check for this situation the chip incorporates a timeout interrupt.

The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it.

These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud).

The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the

Therefore,

To prevent the

INFRARED INTERFACE

The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Several IR implementations have been provided for the second UART in this chip

(logical device 5), IrDA, and Amplitude Shift Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins. These can be selected through the configuration registers.

IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit time. A one is signaled by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the IrDA waveform.

The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a 500KHz waveform for the duration of the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for the parameters of the ASK-IR waveform.

If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The IR half duplex time-out is programmable via CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments.

Figure 2 shows the block diagram of the IR components in the LPC47S42x:

ACE

Registers

Host Interface

ACE UART

COM

IrDA SIR

Sharp ASK

Output

MUX

IR Options Register, Bit 6

COM

FIGURE 2

IR Transmit Pin The following description pertains to the IRTX pin of the LPC47S42x.

Following a VTR POR, the IRTX pin will be output and low. It will remain low until one of the following conditions are met:

GP53/TXD2/IRTX Pin. This pin defaults to the GPIO function.

1. This pin will remain low following a VCC POR until the IRTX function is selected for the pin AND serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the IR transmit output of the IR block (if IR is enabled through the IR options Register for Serial Port 2).

2. This pin will remain low following a VCC POR until the TXD2 function is selected for the pin AND serial port 2 is enabled by setting the activate bit, at which the pin will reflect the state of the transmit output of serial port 2.

3. This pin will remain low following a VCC POR until the corresponding GPIO data bit (GP5 register bit 3) is set or the polarity bit in the GP53 control register is set.

PARALLEL PORT

The LPC47S42x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation.

The LPC47S42x also provides a mode for support of the floppy disk controller on the parallel port.

The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power-up.

The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the Parallel Port is shown below

DATA PORT BASE ADDRESS + 00H STATUS PORT BASE ADDRESS + 01H CONTROL PORT BASE ADDRESS + 02H EPP ADDR PORT BASE ADDRESS + 03H EPP DATA PORT 0 BASE ADDRESS + 04H EPP DATA PORT 1 BASE ADDRESS + 05H EPP DATA PORT 2 BASE ADDRESS + 06H EPP DATA PORT 3 BASE ADDRESS + 07H

The bit map of these registers is:

DATA PORT PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 1 STATUS PORT CONTROL PORT EPP ADDR PORT EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA

PORT 3 Note 1: These registers are available in all modes. Note 2: These registers are only available in EPP mode.

HOST

CONNECTOR

1 83 nSTROBE nWrite nStrobe

2-9 68-75 PD<0:7> PData<0:7> PData<0:7>

10 80 nACK Intr nAck 11 79 BUSY nWait Busy, PeriphAck(3) 12 78 PE (User Defined) PError,

13 77 SLCT (User Defined) Select 14 82 nALF NDatastb nAutoFd,

15 81 nERROR (User Defined) nFault(1)

16 66 nINIT nRESET nInit(1)

17 67 nSLCTIN NAddrstrb nSelectIn(1,3)

(1) = Compatible Mode (3) = High Speed Mode

Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard This document is available from Microsoft.

IBM XT/AT Compatible, Bi-Directional and EPP Modes Data Port

ADDRESS OFFSET = 00H

D0 D1 D2 D3 D4 D5 D6 D7 Note

TMOUT 0 0 nERR SLCT PE nACK nBUSY 1

STROBE AUTOFD nINIT SLC IRQE PCD 0 0 1

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2

Table 33 - Parallel Port Connector

PIN NUMBER

STANDARD

EPP

ECP

nAckReverse(3)

HostAck(3)

nPeriphRequest(3)

nReverseRqst(3)

, Rev. 1.14, July 14, 1993.

The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU.

Status Port

ADDRESS OFFSET = 01H

The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the duration of a read cycle. The bits of the Status Port are defined as follows:

BIT 0 TMOUT - TIME OUT

This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a RESET. Writing a one to this bit clears the time out status bit. On a write, this bit is self clearing and does not require a write of a zero. Writing a zero to this bit has no effect.

BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are

a low level.

BIT 3 nERR - nERROR

The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has been detected; a logic 1 means no error has been detected.

BIT 4 SLCT - PRINTER SELECTED STATUS

The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on line; a logic 0 means it is not selected.

BIT 5 PE - PAPER END

The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper.

BIT 6 nACK - nACKNOWLEDGE

The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer has received a character and can now accept another. A logic 1 means that it is still processing the last character or has not received the data.

BIT 7 nBUSY - nBUSY

The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic 1 means that it is ready to accept the next character.

Control Port

ADDRESS OFFSET = 02H

The Control Port is located at an offset of '02H' from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.

BIT 0 STROBE - STROBE

This bit is inverted and output onto the nSTROBE output.

BIT 1 AUTOFD - AUTOFEED

This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed.

BIT 2 nINIT - nINITIATE OUTPUT

This bit is output onto the nINIT output without inversion.

BIT 3 SLCTIN - PRINTER SELECT INPUT

This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected.

BIT 4 IRQE - INTERRUPT REQUEST ENABLE

The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled.

BIT 5 PCD - PARALLEL CONTROL DIRECTION

Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read).

Bits 6 and 7 during a read are a low level, and cannot be written.

EPP Address Port

ADDRESS OFFSET = 03H

The EPP Address Port is located at an offset of '03H' from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP ADDRESS WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register is only available in EPP mode.

EPP Data Port 0

ADDRESS OFFSET = 04H

The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP DATA WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP mode.

EPP Data Port 1

ADDRESS OFFSET = 05H

The EPP Data Port 1 is located at an offset of '05H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.

EPP Data Port 2

ADDRESS OFFSET = 06H

The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.

EPP Data Port 3

ADDRESS OFFSET = 07H

The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.

EPP 1.9 Operation When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port.

In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0.

During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted.

Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (i.e., a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic "1", and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the parallel bus, no error is indicated.

EPP 1.9 Write The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address cycle. The chip inserts wait states into the LPC I/O write cycle until it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances:

1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then

the write can complete when nWAIT goes inactive high.

2. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before

changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive.

Write Sequence of operation

1. The host initiates an I/O write cycle to the selected EPP register.

2. If WAIT is not asserted, the chip must wait until WAIT is asserted.

3. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.

4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information,

and the WRITE signal is valid.

5. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the

chip may begin the termination phase of the cycle.

6. a. The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the

termination phase. If it has not already done so, the peripheral should latch the information byte now. b. The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that no more wait states are required followed by the TAR to complete the write cycle.

7. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been

satisfied and acknowledging the termination of the cycle.

8. Chip may modify nWRITE and nPDATA in preparation for the next cycle.

EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states into the LPC I/O read cycle until it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances: 1 If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can

complete when nWAIT goes inactive high.

2. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before

changing the state of WRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive.

Read Sequence of Operation

1. The host initiates an I/O read cycle to the selected EPP register.

2. If WAIT is not asserted, the chip must wait until WAIT is asserted.

3. The chip tri-states the PData bus and deasserts nWRITE.

4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the

nWRITE signal is valid.

5. Peripheral drives PData bus valid.

6. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination

phase of the cycle.

7. a) The chip latches the data from the PData bus for the internal data bus and deasserts

nDATASTB or nADDRSTRB. This marks the beginning of the termination phase.

b) The chip drives the sync that indicates that no more wait states are required and drives valid data

onto the LAD[3:0] signals, followed by the TAR to complete the read cycle.

8. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-

stated.

9. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.

EPP 1.7 Operation When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port.

In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to the end of the cycle. If a time-out occurs, the current EPP cycle is aborted and the timeout condition is indicated in Status bit 0.

Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read.

EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The chip inserts wait states into the I/O write cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high.

Write Sequence of Operation

1. The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE.

2. The host initiates an I/O write cycle to the selected EPP register.

3. The chip places address or data on PData bus.

4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and

the WRITE signal is valid.

5. If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts

nWAIT or a time-out occurs.

6. The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the

internal data bus for the PData bus.

7. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.

EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high.

Read Sequence of Operation

1. The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the

PData bus.

2. The host initiates an I/O read cycle to the selected EPP register.

3. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the

nWRITE signal is valid.

4. If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts

nWAIT or a time-out occurs.

5. The Peripheral drives PData bus valid.

6. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the

termination phase of the cycle.

7. The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.

8. Peripheral tri-states the PData bus.

9. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.

Table 34 - EPP Pin Descriptions

EPP

SIGNAL EPP NAME TYPE

nWRITE nWrite O This signal is active low. It denotes a write operation. PD<0:7> Address/Data I/O Bi-directional EPP byte wide address and data bus. INTR Interrupt I This signal is active high and positive edge triggered. (Pass

through with no inversion, Same as SPP).

WAIT nWait I This signal is active low. It is driven inactive as a positive

acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer.

DATASTB nData Strobe O This signal is active low. It is used to denote data read or write

operation.

RESET nReset O This signal is active low. When driven active, the EPP device

is reset to its initial operational mode.

ADDRSTB nAddress

Strobe PE Paper End I Same as SPP mode. SLCT Printer Selected

Status nERR Error I Same as SPP mode.

Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle.

For correct EPP read cycles, PCD is required to be a low.

Extended Capabilities Parallel Port ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section.

O This signal is active low. It is used to denote address read or

write operation.

I Same as SPP mode.

EPP DESCRIPTION

High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer capability.

Vocabulary The following terms are used in this document: assert: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a

"false" state. forward: Host to Peripheral communication. reverse: Peripheral to Host communication Pword: A port word; equal in size to the width of the LPC interface. For this implementation, PWord is

always 8 bits. 1 A high level. 0 A low level.

These terms may be considered synonymous:

PeriphClk, nAck HostAck, nAutoFd PeriphAck, Busy nPeriphRequest, nFault nReverseRequest, nInit nAckReverse, PError Xflag, Select ECPMode, nSelectln HostClk, nStrobe

Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard

, Rev

1.14, July 14, 1993. This document is available from Microsoft.

The bit map of the Extended Parallel Port registers is:

D7 D6 D5 D4 D3 D2 D1 D0 Note

data PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 ecpAFifo Addr/RLE Address or RLE field 2 dsr nBusy nAck PError Select nFault 0 0 0 1 dcr 0 0

Direction

ackIntEn

SelectIn

nInit

autofd

strobe 1 cFifo Parallel Port Data FIFO 2 ecpDFifo ECP Data FIFO 2 tFifo Test FIFO 2 cnfgA 0 0 0 1 0 0 0 0 cnfgB compress

intrValue

Parallel Port IRQ Parallel Port DMA

ecr MODE nErrIntrEn dmaEn serviceIntr full empty

Note 1: These registers are available in all modes. Note 2: All FIFOs use one common 16 byte FIFO. Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the

Configuration Registers.

ECP Implementation Standard This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft.

Description The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions.

Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed.

The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional.

Table 35 - ECP Pin Descriptions

NAME TYPE DESCRIPTION

nStrobe O During write operations nStrobe registers data or address into the slave on

the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I Indicates valid data driven by the peripheral when asserted. This signal

handshakes with nAutoFd in reverse. PeriphAck (Busy) I This signal deasserts to indicate that the peripheral can accept data. This

signal handshakes with nStrobe in the forward direction. In the reverse

direction this signal indicates whether the data lines contain ECP

command information or data. The peripheral uses this signal to flow

control in the forward direction. It is an "interlocked" handshake with

nStrobe. PeriphAck also provides command information in the reverse

direction. PError (nAckReverse)

Select I Indicates printer on line. nAutoFd (HostAck)

nFault (nPeriphRequest)

nInit O Sets the transfer direction (asserted = reverse, deasserted = forward).

nSelectIn O Always deasserted in ECP mode.

Register Definitions The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr. The table below lists these dependencies. Operation of the devices in modes other that those specified is undefined.

NAME ADDRESS (Note 1) ECP MODES FUNCTION

data +000h R/W 000-001 Data Register

I Used to acknowledge a change in the direction the transfer (asserted =

forward). The peripheral drives this signal low to acknowledge

nReverseRequest. It is an "interlocked" handshake with nReverseRequest.

The host relies upon nAckReverse to determine when it is permitted to

drive the data bus.

O Requests a byte of data from the peripheral when asserted, handshaking

with nAck in the reverse direction. In the forward direction this signal

indicates whether the data lines contain ECP address or data. The host

drives this signal to flow control in the reverse direction. It is an

"interlocked" handshake with nAck. HostAck also provides command

information in the forward phase.

I Generates an error interrupt when asserted. This signal provides a

mechanism for peer-to-peer communication. This signal is valid only in the

forward direction. During ECP Mode the peripheral is permitted (but not

required) to drive this pin low to request a reverse transfer. The request is

merely a "hint" to the host; the host has ultimate control over the transfer

direction. This signal would be typically used to generate an interrupt to

the host CPU.

This pin is driven low to place the channel in the reverse direction. The

peripheral is only allowed to drive the bi-directional data bus while in ECP

Mode and HostAck is low and nSelectIn is high.

Table 36 - ECP Register Definitions

100

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