SMSC LPC47B34x Datasheet

LPC47B34x

128 Pin Enhanced Super I/O with LPC Interface

for Consumer Applications

FEATURES

• 3.3 Volt Operation (5V Tolerant)

• LPC Interface

• Floppy Disk Controller (Supports 2 FDCs)

• Multi-Mode Parallel Port

• Two Full UARTs

• 8042 Keyboard Controller (Internal Latch on

IRQ1 and IRQ12)

• Programmable Wakeup Event Interface
(nIO_PME Pin)

• SMI Pin

• GPIOs (62)

• ISA IRQ to Serial IRQ Conversion (11 Pins)

• WDT

• Security Register

• ACPI Support Register for Monitoring

System Sleep State and SMI Generation

• Intrusion Detection

• LED Control

• Low Battery Warning

• Battery Backup of Certain Wakeup Events

• XNOR Chain

• PC99 and ACPI 1.0 Compliant

• ISA Plug-and-Play Compatible Register Set

• Intelligent Auto Power Management

• 2.88MB Super I/O Floppy Disk Controller

- Licensed CMOS 765B Floppy Disk

Controller

- Software and Register Compatible with

SMSC's Proprietary 82077AA
Compatible Core

- Configurable Open Drain/Push-Pull
Output Drivers

- Supports Vertical Recording Format

- 16-Byte Data FIFO

- 100% IBM® Compatibility

- Detects All Overrun and Underrun

Conditions

- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power
Consumption

- DMA Enable Logic

- Data Rate and Drive Control Registers

- 480 Address, up to 15 IRQ and 3 DMA

Options

• Enhanced Digital Data Separator

- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates

- Programmable Precompensation
Modes

• Keyboard Controller

- 8042 Software Compatible

- 8-Bit Microcomputer

- 2k Bytes of Program ROM

- 256 Bytes of Data RAM

- Four Open Drain Outputs Dedicated for

Keyboard/Mouse Interface

- Asynchronous Access to Two Data
Registers and One Status Register

- Supports Interrupt and Polling Access

- 8-Bit Counter Timer

- Port 92 Support

- Fast Gate A20 and KRESET Outputs

• Serial Ports

- Two Full Function Serial Ports

- High Speed NS16C550 Compatible

UARTs with Send/Receive 16-Byte
FIFOs

- Supports 230k and 460k Baud

- Programmable Baud Rate Generator

- Modem Control Circuitry

- 480 Address and 15 IRQ Options

- IrDA 1.0, HP-SIR, ASK IR Support

• Multi-Mode Parallel Port with ChiProtect™

- Standard Mode IBM PC/XT®, PC/AT®,
and PS/2™ Compatible Bidirectional
Parallel Port

- Enhanced Parallel Port (EPP)
Compatible - EPP 1.7 and EPP 1.9
(IEEE 1284 Compliant)

- IEEE 1284 Compliant Enhanced
Capabilities Port (ECP)

GENERAL DESCRIPTION

- ChiProtect Circuitry for Protection
Against Damage Due to Printer Power­On

- 480 Address, up to 15 IRQ and 3 DMA
Options

• LPC Bus (Pin Reduced ISA) Host Interface

- Multiplexed Command, Address and
Data Bus

- 8-Bit I/O Transfers

- 8-Bit DMA Transfers

- 16-Bit Address Qualification

- Serial IRQ Interface Compatible with

Serialized IRQ Support for PCI
Systems

- Power Management Event (nIO_PME)
Interface Pin

• 128 Pin QFP Package

The LPC47B34x* is a 3.3V PC99 compliant
Super I/O controller. The LPC47B34x
implements the LPC interface, a pin reduced
ISA interface which provides the same or better
performance as the ISA/X-bus with a substantial
savings in pins used. The part provides 62

The on-chip UARTs are compatible with the
NS16C550. The parallel port is compatible with
IBM PC/AT architecture, as well as IEEE 1284
EPP and ECP. The LPC47B34x incorporates
sophisticated power control circuitry (PCC). The

PCC supports multiple low power down modes.
GPIO pins and ISA IRQ to serial IRQ
conversion.

The LPC47B34x supports the ISA Plug-and-Play

Standard (Version 1.0a) and provides the
The LPC47B34x incorporates a keyboard
interface, SMSC's true CMOS 765B floppy disk
controller, advanced digital data separator, two
16C550 compatible UARTs, one Multi-Mode
parallel port which includes ChiProtect circuitry
plus EPP and ECP, and Intelligent Power
Management. The true CMOS 765B core
provides 100% compatibility with IBM PC/XT

recommended functionality to support Windows

'95/‘98 and PC99. The I/O Address, DMA

Channel and Hardware IRQ of each logical

device in the LPC47B34x may be

reprogrammed through the internal

configuration registers. There are 480 I/O

address location options, a Serialized IRQ

interface, and three DMA channels.
and PC/AT architectures in addition to providing
data overflow and underflow protection. The
SMSC advanced digital data separator
incorporates SMSC's patented data separator
technology, allowing for ease of testing and use.

Standard Microsystems is a registered trademark and

SMSC is a trademark of Standard Microsystems

Corporation. Other product and company names are

trademarks or registered trademarks of their respective

holders.

*The “x” in the part number is a designator that changes depending upon the particular BIOS used
inside the specific chip.

2

TABLE OF CONTENTS

FEATURES....................................................................................................................................... 1

GENERAL DESCRIPTION ................................................................................................................ 2

PIN CONFIGURATION...................................................................................................................... 6

DESCRIPTION OF PIN FUNCTIONS ................................................................................................ 7

Buffer Type Descriptions.............................................................................................................. 11

3.3 Volt Operation /5 Volt Tolerance.............................................................................................12

Pins That Require External Pullup Resistors.................................................................................13

POWER FUNCTIONALITY.............................................................................................................. 14

VCC Power.................................................................................................................................. 14

VTR Support................................................................................................................................ 14

VBAT Power ................................................................................................................................ 14

Internal PWRGOOD..................................................................................................................... 14

32.768 kHz Trickle Clock Input..................................................................................................... 14

Indication of 32kHz Clock.............................................................................................................15

Internal Ring Oscillator................................................................................................................. 15

Trickle Power Functionality........................................................................................................... 17

Battery Power Functionality..........................................................................................................19

Maximum Current Values............................................................................................................. 19

Power Management Events (PME/SCI) ........................................................................................ 19

FUNCTIONAL DESCRIPTION......................................................................................................... 20

Super I/O Registers...................................................................................................................... 20

Host Processor Interface (LPC).................................................................................................... 20

LPC Interface............................................................................................................................... 20

FLOPPY DISK CONTROLLER........................................................................................................ 25

FDC Internal Registers................................................................................................................. 25

Status Register Encoding............................................................................................................. 39

DMA Transfers.............................................................................................................................43

Controller Phases......................................................................................................................... 43

Command Set/Descriptions .......................................................................................................... 45

Instruction Set .............................................................................................................................. 48

Data Transfer Commands............................................................................................................ 60

Control Commands...................................................................................................................... 67

Direct Support for Two Floppy Drives........................................................................................... 74

SERIAL PORT (UART).................................................................................................................... 76

Register Description..................................................................................................................... 76

Programmable Baud Rate Generator (AND Divisor Latches DLH, DLL)........................................ 85

Effect Of The Reset on Register File............................................................................................. 85

FIFO Interrupt Mode Operation..................................................................................................... 85

FIFO Polled Mode Operation........................................................................................................86

Notes On Serial Port Operation.................................................................................................... 90

Ring Wake Filter.......................................................................................................................... 91

INFRARED INTERFACE ................................................................................................................. 92

IR Transmit Pins.......................................................................................................................... 93

PARALLEL PORT........................................................................................................................... 93

IBM XT/AT Compatible, Bi-Directional And EPP Modes...............................................................95

EPP 1.9 Operation....................................................................................................................... 97

EPP 1.7 Operation....................................................................................................................... 99

Extended Capabilities Parallel Port..............................................................................................101

3

Vocabulary..................................................................................................................................101

ECP Implementation Standard....................................................................................................102

Parallel Port Floppy Disk Controller.............................................................................................114

POWER MANAGEMENT ...............................................................................................................116

FDC Power Management ............................................................................................................116

DSR From Powerdown ................................................................................................................116

Wake Up From Auto Powerdown.................................................................................................116

Register Behavior........................................................................................................................117

Pin Behavior ...............................................................................................................................117

UART Power Management..........................................................................................................119

Exit Auto Powerdown ..................................................................................................................119

Parallel Port................................................................................................................................119

SERIAL IRQ...................................................................................................................................120

ISA IRQ To Serial IRQ Conversion Capability..............................................................................123

8042 KEYBOARD CONTROLLER DESCRIPTION.........................................................................124

Keyboard Interface......................................................................................................................125

External Keyboard and Mouse Interface.......................................................................................126

Keyboard Power Management.....................................................................................................126

Interrupts ....................................................................................................................................127

Memory Configurations...............................................................................................................127

Register Definitions.....................................................................................................................127

External Clock Signal..................................................................................................................128

Default Reset Conditions.............................................................................................................128

Latches On Keyboard and Mouse IRQs.......................................................................................131

Keyboard and Mouse PME Generation........................................................................................132

GENERAL PURPOSE I/O ..............................................................................................................134

GPIO Pins...................................................................................................................................134

Description..................................................................................................................................136

GPIO Control..............................................................................................................................138

GPIO Operation..........................................................................................................................139

GPIO PME and SMI Functionality................................................................................................140

Either Edge Triggered Interrupts ..................................................................................................142

Watch Dog Timer ........................................................................................................................143

SYSTEM MANAGEMENT INTERRUPT (SMI)................................................................................144

SMI Registers .............................................................................................................................144

Low Battery Warning SMI Event..................................................................................................145

ACPI Support Register for SMI Generation..................................................................................145

PME SUPPORT .............................................................................................................................146

Low Battery Warning PME Event.................................................................................................147

‘Wake On Specific Key’ Option ....................................................................................................148

SECURITY FEATURE....................................................................................................................149

GPIO Device Disable Register Control.........................................................................................149

Device Disable Register ..............................................................................................................149

INTRUDER DETECTION................................................................................................................150

Intrusion Bit.................................................................................................................................150

PME and SMI Generation ............................................................................................................150

LED BLINK AND COLOR CONTROL ............................................................................................151

RUNTIME REGISTERS..................................................................................................................152

Runtime Registers Block Summary.............................................................................................152

4

GPIO Registers Block Summary .................................................................................................156

Registers Powered by VBAT........................................................................................................157

Runtime Registers Block Description...........................................................................................157

GPIO Registers Block Description...............................................................................................194

CONFIGURATION .........................................................................................................................200

OPERATIONAL DESCRIPTION.....................................................................................................222

Maximum Guaranteed Ratings....................................................................................................222

DC Electrical Characteristics.......................................................................................................222

TIMING DIAGRAMS ......................................................................................................................226

ECP Parallel Port Timing.............................................................................................................237

PACKAGE OUTLINE .....................................................................................................................245

APPENDIX - TEST MODES ...........................................................................................................246

Board Test Mode.........................................................................................................................246

80 Arkay Drive
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5

12345678910111213141516171819202122232425262728293031323334353637

38

Reserved/GP62

Reserved/GP63

Reserved/GP64

Reserved/GP83

Reserved/GP84

VSS

GP85

Reserved/GP86

Reserved/GP55

Reserved/GP66

Reserved/GP67

COLOR/GP30

BLINK/GP31

nIO_PME/GP42

VTR

CLKI32

Reserved/GP60

Reserved/GP61

VCC

CLOCKI

LAD0

LAD1

LAD2

LAD3

nLFRAME

nLDRQ

nPCI_RESET

nLPCPD

GP43/DDRC

PCI_CLK

SER_IRQ

VSS

GP10

GP11

GP12

Reserved/GP13

Reserved/GP14

Reserved/GP15

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

GP72/IRQ5

GP71/IRQ4

GP70/IRQ3

VSS

nSTROBE

nALF

nERROR

nACK

BUSYPESLCT

PD7

PD6

PD5

PD4

VSS

PD3

PD2

PD1

PD0

nSLCTIN

nINIT

VCC

A20M

nKBDRST

MCLK

MDAT

KCLK

KDAT

nRDATA

nWRTPRT

nTRK0

nINDEX

nHDSEL

nWGATE

nWDATA

nSTEP

nDIR

GP73/IRQ6
GP74/IRQ7

GP75/IRQ9
GP76/IRQ10
GP77/IRQ11
GP80/IRQ12
GP81/IRQ14
GP82/IRQ15

nIO_SMI/GP46

RXD1

TXD1
nDSR1
nRTS1
nCTS1
nDTR1

nRI1

nDCD1

nRI2/GP50

VCC

nDCD2/GP51

RXD2/GP52

TXD2/GP53
nDSR2/GP54
nRTS2/GP55
nCTS2/GP56
nDTR2/GP57

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

PIN CONFIGURATION

LPC47B34x

128 Pin QFP

nDS0

64

nDSKCHG

63

nMTR0

62

GP41/DRVDEN1/nIOCHCK

61

GP40/DRVDEN0

60

GP37/nDS1

59

GP36/nMTR1

58

VSS

57

GP35/IRTX2

56

GP34/IRRX2

55

GP33/WDO

54

Reserved/GP32

53

AVSS

52

GP45

51

GP44

50

GP27

49

Reserved/GP26

48

nINTRSN/GP25

47

VBAT

46

GP24/SYSOPT

45

GP23/nRING

44

GP22/P12

43

GP21/P16

42

GP20/P17

41

GP17

40

Reserved/GP16

39

Note: Pins with a “Reserved” function default to a reserved function and must be programmed to

their GPIO function immediately following power-up.

6

DESCRIPTION OF PIN FUNCTIONS

Note: There are no internal pullups on any of the pins in the LPC47B34x.

PIN # NAME FUNCTION

FDD INTERFACE
60
61

62
63
64
65
66
67
68
69
70
71
72
73
58

59

21

22

23

24

25
26
27
28
30
31

1

GP40 /DRVDEN0 GPIO /Drive Density Select 0 IO12 (I/O12/OD12)/

GP41 /DRVDEN1/
nIOCHCK

GPIO /Drive Density Select 1/

I/O Channel Check
nMTR0 Motor On 0 O12 (O12/OD12)
nDSKCHG Disk Change IS IS
nDS0 Drive Select 0 O12 (O12/OD12)
nDIR Step Direction O12 (O12/OD12)
nSTEP Step Pulse O12 (O12/OD12)
nWDATA Write Disk Data O12 (O12/OD12)
nWGATE Write Gate O12 (O12/OD12)
nHDSEL Head Select O12 (O12/OD12)
nINDEX Index Pulse Input IS IS
nTRK0 Track 0 IS IS
nWRTPRT Write Protected IS IS
nRDATA Read Disk Data IS IS
GP36/nMTR1 General Purpose I/O /Motor On 1 IO12 (I/O12/OD12)/

GP37/nDS1 General Purpose I/O /Drive Select 1 IO12 (I/O12/OD12)/

LPC INTERFACE

LAD0 Multiplexed Command Address and

Data 0
LAD1 Multiplexed Command Address and

Data 1
LAD2 Multiplexed Command Address and

Data 2
LAD3 Multiplexed Command Address and

Data 3
nLFRAME Frame PCI_I PCI_I
nLDRQ Encoded DMA Request PCI_O PCI_O
nPCI_RESET PCI Reset PCI_I PCI_I
nLPCPD (Note 1) Power Down PCI_I PCI_I
PCI_CLK PCI Clock PCI_ICLK PCI_ICLK
SER_IRQ Serial IRQ PCI_IO PCI_IO

GENERAL PURPOSE I/O PINS

Reserved 2 /GP62 Reserved Function /General Purpose

I/O

BUFFER TYPE

BUFFER

TYPE

PER FUNCTION

(NOTE 6)

(O12/OD12)

IO12 (I/O12/0D12)/

(O12/OD12)/I

(O12/OD12)
(O12/OD12)

PCI_IO PCI_IO
PCI_IO PCI_IO
PCI_IO PCI_IO
PCI_IO PCI_IO

IS/O8 IS/O8/OD8

7

PIN # NAME FUNCTION

2

Reserved 2 /GP63 Reserved Function /General Purpose

I/O

3

Reserved 2/GP64 Reserved Function /General Purpose

I/O

4

Reserved 2 /GP83 Reserved Function /General Purpose

I/O

5

Reserved 2 /GP84 Reserved Function /General Purpose

I/O

7
8

GP85 General Purpose I/O IO8 (IO8/OD8)
Reserved 2 /GP86 Reserved Function /General Purpose

I/O

9

10
11

Reserved 2 /GP65 Reserved Function /General Purpose

I/O
Reserved 2 /GP66 Reserved Function /General Purpose

I/O
Reserved 2 /GP67 Reserved Function /General Purpose

I/O

12
13

COLOR /GP30 LED Color /General Purpose I/O IO8 O8/(I/O8/OD8)
BLINK /GP31 LED Blink Output /General Purpose

I/O

17
18
29

Reserved 2 /GP60 Reserved Function /General Purpose I/O IO8 I/O8/OD8
Reserved 2 /GP61 Reserved Function /General Purpose I/O IO8 I/O8/OD8
GP43 /DDRC General Purpose I/O /Device Disable

Register Control

33
34
35
36

GP10 General Purpose I/O IO8 (I/O8/OD8)
GP11 General Purpose I/O IO8 (I/O8/OD8)
GP12 General Purpose I/O IO8 (I/O8/OD8)
Reserved 2 /GP13 Reserved Function /General Purpose

I/O

37

Reserved 2 /GP14 Reserved Function /General Purpose

I/O

38

Reserved 2 /GP15 Reserved Function /General Purpose

I/O

39

Reserved 2 GP16 Reserved Function /General Purpose

I/O

40
41
42
43
44
45

GP17 General Purpose I/O IO8 (I/O8/OD8)
GP20 /P17 General Purpose I/O /P17 IO8 (I/O8/OD8)/IO8
GP21 /P16 General Purpose I/O /P16 IO8 (I/O8/OD8)/IO8
GP22 /P12 General Purpose I/O /P12 IO8 (I/O8/OD8)/IO8
GP23 /nRING General Purpose I/O /Ring Input IO8 (I/O8/OD8)/I
GP24/SYSOPT

General Purpose I/O /System Option IO8 (I/O8/OD8)
(Note 4)

BUFFER TYPE

BUFFER

TYPE

PER FUNCTION

(NOTE 6)

IO8 I/O8/OD8
IO8 I/O8/OD8

IS/O8 IS/O8/OD8

IO8 I/O8/OD8

IO8 I/O8/OD8
IO8 I/O8/OD8

IO12 I/O12/OD12

IO8 I/O8/OD8

IO8 O8/(I/O8/OD8)

IO8 (I/O8/OD8)/I

IO8 I/O8/OD8
IO8 I/O8/OD8
IO8 I/O8/OD8
IO8 I/O8/OD8

8

PIN # NAME FUNCTION

47

nINTRSN/GP25 Intrusion Latch Input /General

Purpose Input

48

Reserved 2 /GP26 Reserved Function /General Purpose

Input

49
50
51

53
54

100
101
102
103
104
105
106
107
108
109
110

GP27 General Purpose Input I I
GP44 General Purpose I/O IO8 (I/O8/OD8)/O8
GP45 General Purpose I/O IO8 (I/O8/OD8)/O8
Reserved 2 /GP32 Reserved Function /General Purpose

I/O
GP33 /WDO

General Purpose I/O/ Watch Dog Timer

Output

GP70/IRQ3 General Purpose I/O /IRQ3 IO8 (I/O8/OD8)/I
GP71/IRQ4 General Purpose I/O /IRQ4 IO8 (I/O8/OD8)/I
GP72/IRQ5 General Purpose I/O /IRQ5 IO8 (I/O8/OD8)/I
GP73/IRQ6 General Purpose I/O /IRQ6 IO8 (I/O8/OD8)/I
GP74/IRQ7 General Purpose I/O / IRQ7 IO8 (I/O8/OD8)/I
GP75/IRQ9 General Purpose I/O /IRQ9 IO8 (I/O8/OD8)/I
GP76/IRQ10 General Purpose I/O /IRQ10 IO8 (I/O8/OD8)/I
GP77/IRQ11 General Purpose I/O /IRQ11 IO8 (I/O8/OD8)/I
GP80/IRQ12 General Purpose I/O /IRQ12 IO8 (I/O8/OD8)/I
GP81/IRQ14 General Purpose I/O /IRQ14 IO8 (I/O8/OD8)/I
GP82/IRQ15 General Purpose I/O /IRQ15 IO8 (I/O8/OD8)/I

POWER MANAGEMENT PINS
14
111

nIO_PME /GP42 Power Management Event Output

/General Purpose I/O

nIO_SMI/GP46 SMI Output /General Purpose I/O IO12 (O12/OD12) /

INFRARED INTERFACE
55
56

GP34/IRRX2 GPIO /IR Receive Input 2 IS/O8 (IS/O8/OD8)/IS
GP35/IRTX2

Note 8

GPIO /IR Transmit Output 2 IO12 (I/O12/OD12)/

KEYBOARD/MOUSE
74
75
76
77
78

KDAT Keyboard Data IOD16 IOD16
KCLK Keyboard Clock IOD16 IOD16
MDAT Mouse Data IOD16 IOD16
MCLK Mouse Clock IOD16 IOD16
nKBDRST

Keyboard Reset (Active low) O8 O8

(Note 3)

79

A20M (Note 3) Gate A20 O8 O8

BUFFER TYPE

BUFFER

TYPE

PER FUNCTION

(NOTE 6)

I I/I
I I/I

IO8 I/O8/OD8

IO8 (I/O8/OD8)/I

IO12 (O12/OD12) /

(I/O12/OD12)

(I/O12/OD12)

O12

9

PIN # NAME FUNCTION

PARALLEL PORT INTERFACE

81

82

83
84
85
86
88
89
90
91
92

nINIT Initiate Output/FDC Direction Control (OD14/OP

nSLCTIN Printer Select Input/FDC Step Pulse (OD14/

PD0 Port Data 0/FDC Index IS/OP14 IOP14/IS
PD1 Port Data 1/FDC Track 0 IS/OP14 IOP14/IS
PD2 Port Data 2/FDC Write Protected IS/OP14 IOP14/IS
PD3 Port Data 3/FDC Read Disk Data IS/OP14 IOP14/IS
PD4 Port Data 4/FDC Disk Change IS/OP14 IOP14/IS
PD5 Port Data 5 IOP14 IOP14
PD6 Port Data 6/FDC Motor On 0 IOP14 IOP14/OD14
PD7 Port Data 7 IOP14 IOP14
SLCT Printer Selected Status/FDC Write

Gate

93
94
95
96
97

98

PE Paper End/FDC Write Data IO12 I/OD12
BUSY Busy/FDC Motor On IO12 I/OD12
nACK Acknowledge/FDC Drive Select 1 IO12 I/OD12
nERROR Error/FDC Head Select IO12 I/OD12
nALF Autofeed Output/FDC Density Select (OD14/

nSTROBE Strobe Output/FDC Drive Select (OD14/

SERIAL PORT 1 INTERFACE
112
113
114
115
116
117
118
119

RXD1 Receive Data 1 IS IS
TXD1 Transmit Data 1 O12 O12
nDSR1 Data Set Ready 1 I I
nRTS1 Request to Send 1 O8 O8
nCTS1 Clear to Send 1 I I
nDTR1 Data Terminal Ready 1 O6 O6
nRI1 Ring Indicator 1 I I
nDCD1 Data Carrier Detect 1 I I

SERIAL PORT 2 INTERFACE
120
122
123

nRI2 /GP50 Ring Indicator 2 /GPIO IO8 I /(I/O8/OD8)
nDCD2 /GP51 Data Carrier Detect 2 /GPIO IO8 I /(I/O8/OD8)
RXD2 /GP52 Receive Serial Data 2 /GPIO IS/O8 IS /(I/O8/OD8)

BUFFER TYPE

BUFFER

TYPE

14)

OP14)

PER FUNCTION

(NOTE 6)

(OD14/OP14)/

OD14

(OD14/OP14)/

OD14

IO12 I/OD12

(OD14/OP14)/

OP14)

OP14)

OD14

(OD14/OP14)/

OD14

124

125

TXD2 /GP53
(Note 5)

Transmit Serial Data 2 /GPIO IO12 O12

/(I/O12/OD12)

nDSR2 /GP54 Data Set Ready 2 /GPIO IO8 I /(I/O8/OD8)

10

BUFFER TYPE

PER FUNCTION

(NOTE 6)

PIN # NAME FUNCTION
126
127
128

nRTS2 /GP55 Request to Send 2 /GPIO IO8 O8 /(I/O8/OD8)
nCTS2 /GP56 Clear to Send 2 /GPIO IO8 I /(I/O8/OD8)
nDTR2 /GP57 Data Terminal Ready 2 /GPIO IO8 O8 /(I/O8/OD8)

BUFFER

TYPE

POWER PINS

19,80,

VCC +3.3 Volt Supply Voltage

121
15
46
6,32,

VTR Standby Supply Voltage
VBAT Battery Voltage
VSS Ground

57,87,
99
52

AVSS Analog Ground

CLOCK PINS
16
20

CLKI32 32.768kHz Standby Clock Input IS IS
CLOCKI 14.318MHz Clock Input IS IS

Note 1: The nLPCPD pin may be pulled high. The LPC interface will function properly if the

nPCI_RESET signal follows the protocol defined for the nLRESET signal in the “Low Pin
Count Interface Specification”.

Note 2: These pins default to a reserved function and must be programmed to their GPIO function

immediately following power-up.
Note 3: The nKBDRST and A20M functions must default to high on VCC POR and Hard Reset.
Note 4: This pin requires an external pulldown resistor to put the base I/O address for configuration at

0x02E. An external pullup resistor is required to move the base I/O address for configuration

to 0x04E.
Note 5: The TXD2 pin will power up as an output and low following a VCC POR and Hard Reset due

to its IR functionality.
Note 6: Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in

parenthesis represent multiple buffer types for a single pin function.
Note 7: If the 32kHz clock is not used, the CLKI32 pin must be grounded. Bit 0 of the CLKI32

configuration register located at 0xF0 in Logical Device A must be set to ‘1’.
Note 8: The GP35/IRTX2 pin powers up as an output and high on VTR POR, VCC POR and Hard

Reset. This pin and GP34/IRRX2 pin are not recommended to be used for IR functionality.

Buffer Type Descriptions

Engineering Note: The buffer type values are specified at VCC=3.3V
IO12 Input/Output, 12mA sink, 6mA source.
IS/O12 Input with Schmitt Trigger/Output, 12mA sink, 6mA source.
O12 Output, 12mA sink, 6mA source.
OD12 Open Drain Output, 12mA sink.
O6 Output, 6mA sink, 3mA source.
IO8 Input/Output, 8mA sink, 4mA source.
IS/O8 Input with Schmitt Trigger/Output, 8mA sink, 4mA source.
O8 Output, 8mA sink, 4mA source.
OD8 Open Drain Output, 8mA sink.

11

OD14 Open Drain Output, 14mA sink.
OP14 Output, 14mA sink, 14mA source.
IOP14 Input/Output, 14mA sink, 14mA source. Backdrive protected.
IS/OP14 Input with Schmitt Trigger /Output, 14mA sink, 14mA source. Backdrive protected.
IOD16 Input/Output (Open Drain), 16mA sink.
O4 Output, 4mA sink, 2mA source.
I Input TTL Compatible.
IS Input with Schmitt Trigger.
PCI_IO Input/Output. These pins meet the PCI 3.3V AC and DC Characteristics.

(Note 1)
PCI_O Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)
PCI_OD Open Drain Output. These pins meet the PCI 3.3V AC and DC Characteristics.

(Note 1)
PCI_I Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)
PCI_ICLK Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing.

(Note 2)
Note 1. See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2.

Note 2. See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. and 4.2.3.

3.3 Volt Operation /5 Volt Tolerance

The LPC47B34x is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are
5V tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive
protected.

The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling.
These pins are:

• LAD[3:0]

• nLFRAME

• nLDRQ

• nLPCPD

The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the
following pins:

• nPCI_RESET

• PCI_CLK

• SERIRQ

• nIO_PME

12

Pins That Require External Pullup Resistors

The following pins require external pullup resistors:

• KDAT

• KCLK

• MDAT

• MCLK

• nKBDRST

• A20M

• GP20/P17 If P17 function is used

• GP21/P16 if P16 or IRQ6 function is used

• GP22/P12 if P12 function is used

• nIO_SMI/GP46 if nIO_SMI function is used as Open Collector Output

• nIO_PME/GP42 if nIO_PME function is used as Open Collector Output

• GP40/DRVDEN0 if DRVDEN0 function is used as Open Collector Output

• GP41/DRVDEN1 if DRVDEN1 function is used as Open Collector Output

• GP70-GP82 if IRQx function is used

• nMTR0 if used as Open Collector Output

• nDS0 if used as Open Collector Output

• nDIR if used as Open Collector Output

• nSTEP if used as Open Collector Output

• nWDATA if used as Open Collector Output

• nWGATE if used as Open Collector Output

• nHDSEL if used as Open Collector Output

• nINDEX

• nTRK0

• nWRTPRT

• nRDATA

• nDSKCHG

13

POWER FUNCTIONALITY

The LPC47B34x has three power planes: VCC, VTR and VBAT.

VCC Power

The LPC47B34x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the “Operational
Description” section. See also the “Maximum Current Values” subsection of the “Power Functionality”
section.

VTR Support

The LPC47B34x requires a trickle supply (VTR) to provide sleep current for the programmable wake-up
events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the
“Operational Description” section. The maximum VTR current that is required depends on the
functions that are used in the part. See the “Trickle Power Functionality” and the “Maximum Current
Values” subsections of the “Power Functionality” section. If the LPC47B34x is not intended to provide
wake-up capabilities on standby current, VTR can be connected to VCC. The VTR pin generates a V
Power-on-Reset signal to initialize the components that are powered by VTR.

Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its
full minimum potential at least 10 µs before VCC begins a power-on cycle. When VTR and VCC are fully
powered, the potential difference between the two supplies must not exceed 500mV.

VBAT Power

The LPC47B34x requires a battery supply (VBAT) to provide battery functionality to certain pins,
registers and logic. The VBAT supply is 3.3 Volts (nominal). See the “Operational Description”
section. See also the “Battery Power Functionality” and the “Maximum Current Values” subsection of
the “Power Functionality” section.

TR

Internal PWRGOOD

An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in
the host interface as VCC cycles on and off. When the internal PWRGOOD signal is “1” (active), VCC >

2.3V (nominal), and the LPC47B34x host interface is active. When the internal PWRGOOD signal is
“0” (inactive), VCC <= 2.3V (nominal), and the LPC47B34x host interface is inactive; that is, LPC bus
reads and writes will not be decoded.

The LPC47B34x device pins nIO_PME, CLOCKI32, KDAT, MDAT, RING, nRI1, nRI2, RXD2 and
GPIOs (as input) are part of the PME interface and remain active when the internal PWRGOOD signal
has gone inactive, provided VTR is powered. The COLOR and BLINK pins also remain active when the
internal PWRGOOD signal has gone inactive, provided VTR is powered. The nINTRSN pin also
remains active when the internal PWRGOOD signal is inactive, however, this is a battery powered pin,
so it is functional as input even if VTR is not powered.

32.768 kHz Trickle Clock Input

The LPC47B34x utilizes a 32.768 kHz trickle clock input to supply a clock signal for the WDT, ring
filter, LED blink, wake on specific key function. See the following section for more information.

14

Indication of 32kHz Clock

There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47B34x. This
bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered
by VTR and reset on a VTR POR.

Bit[0] (CLK32_PRSN) is defined as follows:
0=32kHz clock is connected to the CLKI32 pin (default)
1=32kHz clock is not connected to the CLKI32 pin (pin is grounded).

Bit 0 controls the source of the 32kHz (nominal) clock for the WDT, ring filter, the LED blink logic, the
“wake on specific key” logic. When the external 32kHz clock is connected (CLK32_PRSN=0), that will
be the source for these functions. When the external 32kHz clock is not connected (CLK32_PRSN=1),
an internal 32kHz clock source will be derived from the 14MHz clock for these functions when VCC is
active.

The internal ring oscillator can be used for the LED blink and the wake on specific key logic, when the
32kHz clock is not available. See the Internal Ring Oscillator section.

The following functions will not work under VTR power (VCC removed) if the external 32kHz clock is
not connected. These functions will work under VCC power.

• Ring Filter

• WDT

Internal Ring Oscillator

The internal ring oscillator may be used when the 32kHz trickle input clock is not active. This ring
oscillator can be used for the following functions when VCC=0:

• LED blink

• Wake on Specific Key Feature

When the ring oscillator is used, there is a frequency range on the LED blink rates as follows (the duty
cycle is in parenthesis).

• 0.25 Hz max, 0.084-0.25Hz (10%)

• 0.5 Hz max, 0.17-0.5 Hz (25%)

• 1.0 Hz max, 0.33-1.0 Hz (50%)

• 2.0 Hz max, 0.67-2.0 Hz (50%)

• 3.0 Hz max, 1.0 - 3.0 Hz (50%)

• 4.0 Hz max, 1.33-4.0 Hz (50%)

See the LED register (offset 0x5B) in the “Runtime Registers” section for the bit combinations to select
these blink rates.

The Oscillator Select register contains the bits that are used to determine whether the 32kHz trickle
clock is used or the ring oscillator is used, as follows:

• If bits[1:0] are set to ‘10’ then the 32kHz input is always used for the functions described above.

In this case, the internal ring oscillator is not used. This is the default condition. The
CLK32_PRSN bit is set to ‘0’.

• If bits[1:0] are set to ‘01’ then the internal ring oscillator is always used for the functions described

above while VCC=0 (S3, S4/S5 sleep states). When VCC is active, the 32kHz clock signal is

15

derived from the 14MHz clock. The CLK32_PRSN bit is set to ‘1’. In this case, the range on the
LED blink rates is as indicated above.

• If bits[1:0] are set to ‘00’ then the 32kHz clock is always used for the functions described above. In

this case, the ring oscillator is turned off. The CLK32_PRSN bit is set to ‘0’.

Note: It is recommended that bits[1:0] be reprogrammed to ‘00’ upon power-up if the 32kHz input is to
be used so that the ring oscillator is turned off.

Bit 0 of the CLOCKI32 Configuration Register (CLK32_PRSN) determines whether an external 32kHz
clock is connected to the part. If the external 32kHz clock is not connected to the part (bit 0 of the
CLOCKI32 Configuration Register is ‘1’) then the bits defined above must be ‘01’ for the internal ring
oscillator to be used for these functions described above. That is, if the external 32kHz clock is not
connected to the part then the internal ring oscillator replaces the 32kHz clock to all functions when
VCC=0 if bits[1:0] are set to ‘01’. Note that if the 32kHz clock is not used then the 32kHz clock signal
is derived from the 14MHz clock when VCC is active.

See the Intrusion/Oscillator Select Register for a description of the bits to be used to determine
whether the 32kHz trickle clock is used or the Ring Oscillator is used. This register is located at the
offset of 0x5E from the base I/O address in logical device A. See the Runtime Registers section for
description.

The 32kHz clock signal from the external 32kHz clock input is available/unavailable for these features
in one of two cases:

• Case 1: External 32kHz clock input is active when VCC is active (S0, S1) and when VCC=0 (S3-

S5 states) i.e., the 32kHz clock is connected and always active. In this case, the internal ring
oscillator would not be used and bits[1:0] of the Oscillator Select Register should be programmed
to ‘00’. The CLK32_PRSN bit is ‘0’.

• Case 2: External 32kHz clock is not connected. The internal ring oscillator is used when VCC=0

with bits[1:0] of the Oscillator Select Register = ‘01’. Note that in this case, the internal ring
oscillator is used for the LED blink and wake on specific key in the S3 state as well as in the
S4/S5 state. When VCC is active (S0, S1) the 32kHz clock is derived from the 14MHz clock. The
CLK32_PRSN bit is ‘1’.

When the LPC47B34x switches from the ring oscillator to the 32kHz clock, edge detection on the
internal 32kHz clock source is used to insure that it is active before the switching takes place.

Switching between the ring oscillator and the 32kHz clock derived from the 14MHz clock input (case 2)
is performed by the part as follows:

• When VCC goes inactive, use the ring oscillator.

• When VCC goes active and an edge is detected on the 32kHz clock source to the Clock Select

Logic, switch to the 32kHz clock.

The “Wake on Specific Key” option and LED blink will run off of the ring oscillator when the external
32kHz clock and 14MHz clock are not available.

The Ring Filter and WDT options do not function when both external 32kHz input clock signal and
14MHz input clock signal are not available. These features do not run off the ring oscillator.

16

Trickle Power Functionality

When the LPC47B34x is running under VTR only, the following functionality is retained:
PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The
following lists the wakeup events:

• UART 1 Ring Indicator

• UART 2 Ring Indicator

• Keyboard data

• Mouse data

• nRING

• Wake on Specific Key Logic

• Intrusion

• GPIOs for wakeup. See below.

The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.

• I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0),

these pins may only be configured as inputs. These inputs have input buffers into the wakeup
logic that are powered by VTR.

• I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0),

are powered by VTR. This means at a minimum, they will source their specified current from VTR
even when VCC is present.

The GPIOs that are used for PME wakeup are GP10-GP17, GP20- GP27, GP32-GP33, GP36, GP37,
GP41, GP42, GP43-GP45, GP50, GP56-GP57, GP60, GP61, GP65, GP70-77, GP80-82, GP85-86.
These GPIOs function as follows (with the exception of GP42, GP65 and GP86 - see below):

• Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not

impose a load on any external VTR powered circuitry). They are wakeup compatible inputs under

VTR power. These pins have input buffers into the wakeup logic that are powered by VTR.
All GPIOs listed above are for PME wakeup. GP50 can be used for PME wakeup only if nRI2 function
is selected. GP42 has the nIO_PME output pin function.

The other GPIOs function as follows:
GP34, GP35, GP40, GP46, GP51-GP55, GP62, GP63, GP64, GP83 and GP84:

• Buffers powered by VCC, but in the absence of VCC they are backdrive protected.
These pins are not used for wakeup.

GP30, GP31, GP42, GP65, GP66, GP67, GP86:

• Buffer is powered by VTR.
GP42 has the IO_PME pin function.
GP66 and GP67 are not used for wakeup.

See the Table in the GPIO section for more information.
The IRTX pin (TXD2/GP53) is driven low on VCC POR and Hard Reset regardless of the selected pin

function. The TXD2/GP53 pin will remain low following a VCC POR until the serial port is enabled by
setting the activate bit, at which time the pin will reflect the state of the UART2 transmit output. If the
IRTX function is selected for the pin, the pin will reflect the state of the IR transmit output of the IRCC
block when the serial port is enabled by setting the activate bit. If the GPIO output function is
selected, the pin will reflect the state of the data bit.

17

The following list summarizes the blocks, registers and pins that are powered by VTR.

• PME interface block

• Runtime register block (includes all PME, SMI, GPIO and other miscellaneous registers)

• Wake on Specific Key logic

• Ring Filter Logic

• Internal Ring Oscillator

• Pins for PME Wakeup:

- nIO_PME/GP42

- nRING

- RI1

- RI2

- RXD2

- KDAT

- MDAT

- GPIOs (GP10-GP17, GP20-GP27, GP32-GP33, GP36, GP37, GP41, GP43-GP45, GP50,

GP56-GP57, GP60, GP61, GP65, GP70-GP77, GP80-GP82, GP85, GP86)

Note: The output pins that are powered by VTR are listed in the next section.

18

Battery Power Functionality
The following list summarizes the blocks, registers and pins that are powered by VBAT.

• Intruder Detection Logic

• Runtime Registers

- Device Disable Register

- GP25

- GP26

- GP27

- Intrusion/Oscillator Select Register

- Keyboard Scan Code

• Pin

- nINTRSN

The part can be enabled to indicate low battery / battery removal as a PME and an SMI event. See
the “PME Support” and “System Management Interrupt” section.

Maximum Current Values

See the “Operational Description” section for the maximum current values.
The maximum VTR current, ITR, is given with all outputs open (not loaded). The total maximum

current for the part is the unloaded value PLUS the maximum current sourced by all pins that are
driven by VTR. The output pins that are powered by VTR are listed below. These pins, if configured
as push-pull outputs, will source a minimum of 6mA at 2.4V when driving.

PIN DEFAULT TYPE (VTR POR) POWER SOURCE

Reserved /GP86 Output, high VTR
Reserved /GP67 Output – OD, low VTR
Reserved /GP66 Output – OD, high VTR
BLINK/GP31 Output, low VTR
COLOR/GP30 Output, low VTR
Reserved /GP65 Output, OD (Note) VTR
nIO_PME/GP42 Output - OD, high VTR

Note: Default value depends on the value of pin 48 upon VTR POR: if pin 48 is high, then this pin is

high on VTR POR; if pin 48 is low, then this pin is low on VTR POR.
The maximum VCC current, ICC, is given with all outputs open (not loaded).
The maximum VBAT current, I

, is given with all outputs open (not loaded).

BAT

Power Management Events (PME/SCI)

The LPC47B34x offers support for Power Management Events (PMEs), also referred to as System
Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this
document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output
signal on pin 14. See the “PME Support” section.

19

FUNCTIONAL DESCRIPTION

Super I/O Registers

The address map, shown below in Table 1, shows the addresses of the different blocks of the Super
I/O immediately after power up. The base addresses of the FDC, serial and parallel ports, PME
register block, Game port and configuration register block can be moved via the configuration
registers. Some addresses are used to access more than one register.

Host Processor Interface (LPC)

The host processor communicates with the LPC47B34x through a series of read/write registers via the
LPC interface. The port addresses for these registers are shown in Table 1. Register access is
accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.

Table 1 – Super Block Address

LOGICAL

ADDRESS BLOCK NAME

Base+(0-5) and +(7) Floppy Disk 0
Base+(0-7) Serial Port Com 1 4
Base1+(0-7) Serial Port Com 2 5 IR Support

Parallel Port
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
60, 64 KYBD 7
Base + (0-71) Runtime Registers A
Base + (0-1) Configuration

Note 1: Refer to the configuration register descriptions for setting the base address.

SPP

EPP

ECP

ECP+EPP+SPP

DEVICE NOTES

3

LPC Interface

The following sub-sections specify the implementation of the LPC bus.

LPC Interface Signal Definition

The signals required for the LPC bus interface are described in the table below. LPC bus signals use
PCI 33MHz electrical signal characteristics.

SIGNAL NAME TYPE DESCRIPTION

LAD[3:0] I/O LPC address/data bus. Multiplexed command, address and data

bus.

nLFRAME Input Frame signal. Indicates start of new cycle and termination of

broken cycle

nPCI_RESET Input PCI Reset. Used as LPC Interface Reset. Same functionality as

RST_DRV but active low 3.3V.
nLDRQ Output Encoded DMA/Bus Master request for the LPC interface.
nIO_PME OD Power Mgt Event signal. Allows the LPC47B34x to request

wakeup.
nLPCPD Input Powerdown Signal. Indicates that the LPC47B34x should prepare

for power to be shut on the LPC interface.

20

SIGNAL NAME TYPE DESCRIPTION

SERIRQ I/O Serial IRQ.
PCI_CLK Input PCI Clock.

LPC Cycles

The following cycle types are supported by the LPC protocol.

CYCLE TYPE TRANSFER SIZE

I/O Write 1 Byte Transfer

I/O Read 1 Byte Transfer
DMA Write 1 byte
DMA Read 1 byte

The LPC47B34x ignores cycles that it does not support.

Field Definitions

The data transfers are based on specific fields that are used in various combinations, depending on
the cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control
and data information over the LPC bus between the host and the LPC47B34x. See the Low Pin Count
(LPC) Interface Specification Reference, Section 4.2 for definition of these fields.

nLFRAME Usage

nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an
abort or time-out condition. This signal is to be used by the LPC47B34x to know when to monitor the
bus for a cycle.

This signal is used as a general notification that the LAD[3:0] lines contain information relative to the
start or stop of a cycle, and that the LPC47B34x monitors the bus to determine whether the cycle is
intended for it. The use of nLFRAME allows the LPC47B34x to enter a lower power state internally.
There is no need for the LPC47B34x to monitor the bus when it is inactive, so it can decouple its state
machines from the bus, and internally gate its clocks.

When the LPC47B34x samples nLFRAME active, it immediately stops driving the LAD[3:0] signal
lines on the next clock and monitor the bus for new cycle information.

The nLFRAME signal functions as described in the Low Pin Count (LPC) Interface Specification
Reference.

I/O Read and Write Cycles
The LPC47B34x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO
accesses, and will generally have minimal Sync times. The minimum number of wait-states between
bytes is 1. EPP cycles will depend on the speed of the external device, and may have much longer
Sync times.

Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the
host will break it up into 8-bit transfers.

See the Low Pin Count (LPC) Interface Specification Reference, Section 5.2, for the sequence of
cycles for the I/O Read and Write cycles.

21

DMA Read and Write Cycles
DMA read cycles involve the transfer of data from the host (main memory) to the LPC47B34x. DMA

write cycles involve the transfer of data from the LPC47B34x to the host (main memory). Data will be
coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the
LPC47B34x are 1 byte.

See the Low Pin Count (LPC) Interface Specification Reference, Section 6.4, for the field definitions
and the sequence of the DMA Read and Write cycles.

DMA Protocol
DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47B34x and special
encodings on LAD[3:0] from the host.

The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Interface Specification
Reference.

Power Management

CLOCKRUN Protocol

The nCLKRUN pin is not implemented in the LPC47B34x.
See the Low Pin Count (LPC) Interface Specification Reference, Section 8.1.

LPCPD Protocol

See the Low Pin Count (LPC) Interface Specification Reference, Section 8.2.

SYNC Protocol

See the Low Pin Count (LPC) Interface Specification Reference Section 4.2.1.8 for a table of valid
SYNC values.

Typical Usage

The SYNC pattern is used to add wait states. For read cycles, the LPC47B34x immediately drives the
SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write
cycles. If the LPC47B34x needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0]
until it is ready, at which point it will drive 0000 or 1001. The LPC47B34x will choose to assert 0101
or 0110, but not switch between the two patterns.

The data (or wait state SYNC) will immediately follow the 0000 or 1001 value.
The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete

within a few clocks. The LPC47B34x uses a SYNC of 0101 for all wait states in a DMA transfer.
The SYNC value of 0110 is intended to be used where the number of wait states is large. This is

provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond).
However, the LPC47B34x uses a SYNC of 0110 for all wait states in an I/O transfer.

The SYNC value is driven within 3 clocks.

22

SYNC Timeout

The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid
SYNC pattern, it will abort the cycle.

The LPC47B34x does not assume any particular timeout. When the host is driving SYNC, it may
have to insert a very large number of wait states, depending on PCI latencies and retries.

SYNC Patterns and Maximum Number of SYNCS

If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8.
If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47B34x has

protection mechanisms to complete the cycle. This is used for EPP data transfers and utilizes the
same timeout protection that is in EPP.

SYNC Error Indication

The LPC47B34x reports errors via the LAD[3:0] = 1010 SYNC encoding.
If the host was reading data from the LPC47B34x, data will still be transferred in the next two nibbles.
This data may be invalid, but it will be transferred by the LPC47B34x. If the host was writing data to
the LPC47B34x, the data had already been transferred.

In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle.
Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the
first byte, the other three bytes will not be transferred.

I/O and DMA START Fields
I/O and DMA cycles use a START field of 0000.

Reset Policy
The following rules govern the reset policy:

1) When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec
prior to the removal of the reset signal, so that everything is stable. This is the same reset active
time after clock is stable that is used for the PCI bus.

2) When nPCI_RESET goes active (low):
a) The host drives the nLFRAME signal high, tristates the LAD[3:0] signals, and ignores the

nLDRQ signal.

b) The LPC47B34x ignores nLFRAME, tristate the LAD[3:0] pins and drive the nLDRQ signal

inactive (high).

23

LPC Transfer Sequence Examples

Wait State Requirements

I/O Transfers
The LPC47B34x inserts three wait states for an I/O read and two wait states for an I/O write cycle. A
SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY
would be deasserted in an ISA system (i.e., EPP transfers) in which case the sync pattern of 0110 is
used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of
10us).

DMA Transfers
The LPC47B34x inserts three wait states for a DMA read and four wait states for a DMA write cycle. A
SYNC of 0101 is used for all DMA transfers.

See the example timing for I/O and DMA transfers in the “Timing Diagrams” section.

24

FLOPPY DISK CONTROLLER

The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy
disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator,
Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true
CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow
and underflow protection.

The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.

FDC Internal Registers

The Floppy Disk Controller contains eight internal registers that facilitate the interfacing between the
host microprocessor and the disk drive. Table 2 shows the addresses required to access these
registers. Registers other than the ones shown are not supported. The rest of the description
assumes that the primary addresses have been selected.

(Shown with base addresses of 3F0 and 370)

PRIMARY

ADDRESS

3F0
3F1
3F2
3F3
3F4
3F4
3F5
3F6
3F7
3F7

SECONDARY

ADDRESS R/W REGISTER

370
371
372
373
374
374
375
376
377
377

R

R
R/W
R/W

R

W

R/W

R

W

Status Register A (SRA)
Status Register B (SRB)
Digital Output Register (DOR)
Tape Drive Register (TDR)
Main Status Register (MSR)
Data Rate Select Register (DSR)
Data (FIFO)
Reserved
Digital Input Register (DIR)
Configuration Control Register (CCR)

Status Register A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state of the internal interrupt signal and several disk
interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2
mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of
address 3F0.

PS/2 Mode

7 6 5 4 3 2 1 0

RESET
COND.

INT

PENDING

0 1 0 N/A 0 N/A N/A 0

nDRV2 STEP nTRK0 HDSEL nINDX NWP DIR

25

BIT 0 DIRECTION

Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a
logic "0" indicates outward direction.

BIT 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is
write protected.

BIT 2 nINDEX

Active low status of the INDEX disk interface input.

BIT 3 HEAD SELECT

Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects
side 0.

BIT 4 nTRACK 0

Active low status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the STEP output disk interface output pin.

BIT 6 nDRV2

This function is not supported in the LPC47B34x. This bit is always read as ‘1’.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0

INT

PENDING
RESET
COND.

BIT 0 nDIRECTION

Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a
logic "1" indicates outward direction.

BIT 1 WRITE PROTECT

Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is
write protected.

BIT 2 INDEX

Active high status of the INDEX disk interface input.

0 0 0 N/A 1 N/A N/A 1

DRQ STEP

F/F

TRK0 nHDSEL INDX WP nDIR

26

BIT 3 nHEAD SELECT

Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects
side 0.

BIT 4 TRACK 0

Active high status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP
output going active, and is cleared with a read from the DIR register, or with a hardware or software
reset.

BIT 6 DMA REQUEST

Active high status of the DMA request pending.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt.

Status Register B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state of several disk interface pins in PS/2 and model 30
modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus
pins D0 - D7 are held in a high impedance state for a read of address 3F1.

PS/2 Mode

7 6 5 4 3 2 1 0

RESET

1 1 DRIVE

SEL0

1 1 0 0 0 0 0 0

WDATA

TOGGLE

RDATA

TOGGLE

WGATE MOT

EN1

MOT

EN0

COND.

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and
unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and
unaffected by a software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

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BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a
hardware reset and it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic "1".

BIT 7 RESERVED

Always read as a logic "1".

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0

RESET

nDRV2 nDS1 nDS0 WDATA

F/F

N/A 1 1 0 0 0 1 1

RDATA

F/F

WGATE

F/F

nDS3 nDS2

COND.

BIT 0 nDRIVE SELECT 2

The DS2 disk interface is not supported in the LPC47B34x.

BIT 1 nDRIVE SELECT 3

The DS3 disk interface is not supported in the LPC47B34x.

BIT 2 WRITE GATE

Active high status of the latched WGATE output signal. This bit is latched by the active going edge of
WGATE and is cleared by the read of the DIR register.

BIT 3 READ DATA

Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge
of RDATA and is cleared by the read of the DIR register.

BIT 4 WRITE DATA

Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge
of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface output.

BIT 7 nDRV2

Active low status of the DRV2 disk interface input. Note: This function is not supported in the
LPC47B34x.

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Digital Output Register (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enables of the disk interface outputs. It also
contains the enable for the DMA logic and a software reset bit. The contents of the DOR are
unaffected by a software reset. The DOR can be written to at any time.

7 6 5 4 3 2 1 0

MOT

EN3

RESET

MOT

EN2

MOT

EN1

MOT

EN0

DMAEN nRESET DRIVE

SEL1

DRIVE

SEL0

0 0 0 0 0 0 0 0

COND.

BIT 0 and 1 DRIVE SELECT

These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected
at one time.

BIT 2 nRESET

A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic
"1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it
affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore
toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DMA and interrupt functions.
This bit being a logic "0" will disable the DMA and interrupt functions. This bit is a logic "0" after a
reset and in these modes.

PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit
will be cleared to a logic "0".

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go
active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go
active.

BIT 6 MOTOR ENABLE 2

The MTR2 disk interface output is not supported in the LPC47B34x.

BIT 7 MOTOR ENABLE 3

The MTR3 disk interface output is not supported in the LPC47B34x.

29

DRIVE DOR VALUE

0
1

1CH
2DH

Tape Drive Register (TDR)

Address 3F3 READ/WRITE

The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to
assign tape support to a particular drive during initialization. Any future references to that drive
automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive
number. Table 3 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and
cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated
when read. The TDR is unaffected by a software reset.

Table 2 – Tape Select Bits

TAPE SEL1

(TDR.1)

0
0
1
1

TAPE SEL0

(TDR.0) DRIVE SELECTED

0
1
0
1

None

1
2
3

Table 3 – Internal Drive Decode (Normal)

DIGITAL OUTPUT

REGISTER

DRIVE SELECT

OUTPUTS (ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X 1 0 0 1 0 nBIT 5 nBIT 4
1 X 0 1 0 1 nBIT 5 nBIT 4
0 0 X X 1 1 nBIT 5 nBIT 4

Table 4 – Internal 2 Drive Decode (Drives 0 and 1 Swapped)

DIGITAL OUTPUT

REGISTER

DRIVE SELECT

OUTPUTS (ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X 1 0 0 0 1 nBIT 4 nBIT 5
1 X 0 1 1 0 nBIT 4 nBIT 5
0 0 X X 1 1 nBIT 4 nBIT 5

30