SMSC FDC37C665GT, FDC37C666GT Technical data

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Parallel Port Super I/O Floppy Disk Controllers

• 5 Volt Operation

• Floppy Disk Available on Parallel Port Pins

• 2.88MB Super I/O Floppy Disk Controller

- Licensed CMOS 765B Floppy Disk Controller

- Software and Register Compatible to the 82077AA Using SMSC's Proprietary Floppy Disk Controller Core

- Supports Vertical Recording Format

- 100% IBM® Compatibility

- Detects All Overrun and Underrun Conditions

- 48 mA Drivers and Schmitt Trigger Inputs

- DMA Enable Logic

- Data Rate and Drive Control Registers

- Swap Drives A and B

- Non-Burst Mode DMA Option

- FDC Primary/Secondary Address Selection

- 16 Byte Data FIFO

- Low Power CMOS 0.8µ Design

• Enhanced Digital Data Separator

- Low Cost Implementation - 24 MHz Crystal

- No Filter Components Required

- Ease of Test and Use, Lower System Cost, and Reduced Board Area

- 1 Mb/s, 500 Kb/s, 300 Kb/s, 250 Kb/s Data Rates

- Supports Floppy Disk and Tape Drives

- Programmable Precompensation Modes

FDC37C665GT FDC37C666GT

High-Performance Multi-Mode

FEATURES

• Multi-Mode Parallel Port with ChiProtect Circuitry

- Standard Mode

- IBM PC/XT®, PC/AT®, and PS/2 Compatible Bidirectional Parallel Port

- Enhanced Mode

- Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)

- High Speed Mode

- Microsoft and Hewlett Packard Extended Capabilities Port (ECP) IEEE 1284 Compliant

- Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On

- Provides Backdrive Current Protection

- 24 mA Output Drivers

- Two Parallel Port Interrupt Pins

• Serial Ports

- Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs

- MIDI Compatible

- Programmable Baud Rate Generator

- Modem Control Circuitry

• ISA Host Interface

• IDE Interface

- On-Chip Decode and Select Logic Compatible with IBM PC/XT and PC/AT Embedded Hard Disk Drives

- IDE Primary/Secondary Address Selection

Ÿ Supports Four Floppy Drives Directly

(Standard and Enhanced Modes)

Ÿ General Purpose 11 Bit Address Decoder

Ÿ Game Port Select Logic (FDC37C666GT

Only)

Ÿ 100 Pin QFP Package

TABLE OF CONTENTS

FEATURES...................................................................................................................................... 1

GENERAL DESCRIPTION................................................................................................................ 3

PIN CONFIGURATION ...................................................................................................................... 4

DESCRIPTION OF PIN FUNCTIONS ................................................................................................ 5

FUNCTIONAL DESCRIPTION........................................................................................................ 22

SUPER I/O REGISTERS ...........................................................................................................22

HOST PROCESSOR INTERFACE ............................................................................................ 22

FLOPPY DISK CONTROLLER.................................................................................................. 23

FLOPPY DISK CONTROLLER INTERNAL REGISTERS............................................................23

COMMAND SET/DESCRIPTIONS.................................................................................................. 46

INSTRUCTION SET ........................................................................................................................ 50

PARALLEL PORT FLOPPY DISK CONTROLLER.............................................................................76

SERIAL PORT (UART).................................................................................................................... 78

PARALLEL PORT........................................................................................................................... 92

IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES...............................................94

EXTENDED CAPABILITIES PARALLEL PORT........................................................................100

INTEGRATED DRIVE ELECTRONICS INTERFACE..................................................................... 113

CONFIGURATION......................................................................................................................... 117

OPERATIONAL DESCRIPTION..................................................................................................... 131

MAXIMUM GUARANTEED RATINGS..................................................................................... 131

DC ELECTRICAL CHARACTERISTICS ................................................................................. 131

TIMING DIAGRAMS...................................................................................................................... 134

ECP PARALLEL PORT TIMING...............................................................................................147

GENERAL DESCRIPTION

The SMSC FDC37C665GT and FDC37C666GT Advanced High Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller ICs utilize SMSC's proven SuperCell technology for increased product reliability and functionality. The FDC37C665GT is optimized for motherboard applications while the FDC37C666GT is oriented towards controller card applications. Both devices support 1 Mb/s data rates for vertical recording operation. The FDC37C665GT is hardware compatible with the FDC37C651 and FDC37C661 in the Standard and Enhanced Parallel Port Modes.

The FDC37C665GT and FDC37C666GT incorporate SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16 byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP support, IDE interface, on-chip 24 mA AT bus drivers, game port chip select (FDC37C666GT only), general purpose address decoder and four floppy direct drive support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both on-chip UARTs are compatible with the NS16C550. The parallel port, the IDE interface and the

game port select logic are compatible with IBM PC/XT and PC/AT architectures, as well as EPP and ECP. The FDC37C665GT and FDC37C666GT incorporate sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes.

The FDC37C665GT Floppy Disk Controller incorporates Software Configurable Logic (SCL) for ease of use. Use of the SCL feature allows programmable system configuration of key functions such as the FDC, parallel port, and UARTs. The parallel port ChiProtect prevents damage caused by the printer being powered when the FDC37C665GT or FDC37C666GT is not powered. The parallel port backdrive current protection prevents the FDC37C665GT or FDC37C666GT from sinking current when the device is powered off and the printer is left powered on.

The FDC37C665GT and FDC37C666GT do not require any external filter components and are, therefore, easy to use and offer lower system cost and reduced board area. The FDC37C665GT and FDC37C666GT are software and register compatible to the 82077AA using SMSC's proprietary floppy disk controller core.

IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark of International Business Machines Corporation. SMSC is a registered trademark and ChiProtect, SuperCell, and Multi-Mode are trademarks of Standard Microsystems Corporation

PIN CONFIGURATION

FDRQD4D5D6D7

RESET

PWRGD

SLCTPEBUSY

nACK

PD7

PD6

PD5

PD4

VSS

PD3

PD2

PD1

PD0

VCC

nSLCTIN

nINIT

nAUTOFD

nSTROBE

TXD1

nDSR1

nERROR

nIOCS16

nHDCS1

nHDCS0

nIDEENHI

nIDEENLO

IDED7

X2/CLK2

X1/CLK1

DRATE0/MEDIA _ID0

DRATE1/MEDIA_ID1

nDSKCHG

nRDATA

VCC

nWRTPRT

nTRK0

nINDEX

nHDSEL

nWGATE

nWDATA

nSTE P

nDIR

nMTR1

nDS0

nDS1

nMTR0

VSS

DENSEL

FDRQD4D5D6D7

RESET

nGAMECS/PADCF

SLCTPEBUSY

nACK

PD7

PD6

PD5

PD4

VSS

PD3

PD2

PD1

PD0

VCC

nSLCTIN

nINIT

nAUTOFD

nSTROBE

RXD1

TXD1

nDSR1

nERROR

nIOCS16

nHDCS1/FACF

nHDCS0/IDEACF

nIDEENHI

nIDEENLO

IDED7

X2/CLK2

X1/CLK1

DRATE0/MEDIA_ID0

DRATE1/MEDIA_ID1

nDSKCHG

nRDATA

VCC

nWRTPRT

nTRK0

nINDEX

nHDSEL

nWGATE

nWDATA

nSTE P

nDIR

nMTR1

nDS0

nDS1

nMTR0

VSS

DENSEL

RXD1

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

VSS

AEN

nIOW

nIOR

FINTR

PINTR

IRQ4

IRQ3

nDACK

VSS

AEN

nIOW

nIOR

FINTR

PINTR

PSPIRQ

SSPIRQ

nDACK

nRI1

nRI2

RXD2 TXD2

VSS

nRTS1 nCTS1 nDTR1

nRI1

nRI2

RXD2

TXD2

nRTS2 nCTS2

VSS

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

81 82

100

83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

FDC37C665GT

FDC37C666GT

302928272625242322212019181716151413121110987654321

nRTS1 nCTS1 nDTR1

nDCD1

nDCD2

nDSR2 nRTS2 nCTS2

DRV2/ADRx/PINTR2

nDTR2

nMTR2/PDACK

nDS3/A10

nDS2/nDS3/PDIR

nMTR3/PDRQ

IOCHRDY

nDCD1

nDCD2

nDSR2

nDTR2

nMTR2/PDACK

nDS3/A10

nDS2/nDS3/PDIR

nMTR3/PDRQ

IOCHRDY

DESCRIPTION OF PIN FUNCTIONS

BUFFER

PIN NO. NAME SYMBOL

HOST PROCESSOR INTERFACE

48-51 53-56

44 nI/O Read nIOR I This active low signal is issued by the host

45 nI/O Write nIOW I This active low signal is issued by the host

46 Address Enable AEN I Active high Address Enable indicates DMA

28-34 41-43

52 FDC DMA

36 nDMA Acknowle-

35 Terminal Count TC I This signal indicates to the FDC37C665GT

Data Bus 0-7 D0-D7 I/O24 The data bus connection used by the host

I/O Address A0-A9 I These host address bits determine the I/O

FDRQ O24 This active high output is the DMA request

Request

nDACK I An active low input acknowledging the

dge

TYPE DESCRIPTION

microprocessor to transmit data to and from the FDC37C665GT. These pins are in a high-impedance state when not in the output mode.

microprocessor to indicate a read operation.

microprocessor to indicate a write operation.

operations on the host data bus. Used internally to qualify appropriate address decodes.

address to be accessed during nIOR and nIOW cycles. These bits are latched internally by the leading edge of nIOR and nIOW.

for byte transfers of data to the host. This signal is cleared on the last byte of the data transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode).

request for a DMA transfer of data. This input enables the DMA read or write internally.

that data transfer is complete. TC is only accepted when nDACK or nPDACK is low. In AT and PS/2 model 30 modes, TC is active high and in PS/2 mode, TC is active low.

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL

38 Serial Port

Interrupt Request

IRQ4

BUFFER

TYPE DESCRIPTION

O24

FDC37C665GT (Motherboard application): IRQ4 is the interrupt from the Primary Serial Port (PSP) or Secondary Serial Port (SSP) when the PSP or SSP have their address programmed as COM1 or COM3 (as defined in the Configuration Registers). The appropriate interrupt from the Serial Port is enabled/disabled via the Interrupt Enable Register (IER). The interrupt is reset inactive after interrupt service. It is disabled through IER or hardware reset.

Primary Serial Port Interrupt

37 Serial Port

Interrupt Request

Secondary Serial Port Interrupt

40 Floppy

Controller Interrupt Request

PSPIRQ

IRQ3

SSPIRQ

FINTR O24 This interrupt from the Floppy Disk

O24

FDC37C666GT (Adapter application): PSPIRQ is a source of PSP interrupt. Externally, it should be connected to either IRQ3 or IRQ4 on PC/AT via jumpers.

FDC37C665GT (Motherboard application): IRQ3 is the interrupt from the Primary Serial Port (PSP) or secondary Serial Port (SSP) when the PSP or SSP have their address programmed as COM2 or COM4 (as defined in the Configuration Registers). The appropriate interrupt from the Serial Port is enabled/disabled via the Interrupt Enable Register (IER). The interrupt is reset inactive after interrupt service. It is disabled through IER or hardware reset.

FDC37C666GT (Adapter application): SSPIRQ is a source of SSP interrupt. Externally, it should be connected to either IRQ3 or IRQ4 on PC/AT via jumpers.

Controller is enabled/disabled via bit 3 of the Digital Output Register (DOR).

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL

39 Parallel Port

Interrupt Request 1

PINTR1 O24

BUFFER

TYPE DESCRIPTION

This interrupt from the Parallel Port is enabled/disabled via bit 4 of the Parallel Port Control Register. Refer to configuration registers CR1 and CR3 for more information.

OD24

57 Reset RST IS This active high signal resets the

FLOPPY DISK INTERFACE

16 nRead Disk Data nRDATA IS Raw serial bit stream from the disk drive,

10 nWrite

Gate

9 nWrite

Data

11 nHead

Select

nWGATE OD48 This active low high current driver allows

nWDATA OD48 This active low high current driver provides

nHDSEL OD48 This high current output selects the floppy

If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts.

FDC37C665GT and must be valid for 500 ns minimum. The effect on the internal registers is described in the appropriate section. The configuration registers are not affected by this reset. In the FDC37C666GT, the falling edge of reset latches the jumper configuration. The jumper select lines must be valid 50 ns prior to this edge.

low active. Each falling edge represents a flux transition of the encoded data.

current to flow through the write head. It becomes active just prior to writing to the diskette.

the encoded data to the disk drive. Each falling edge causes a flux transition on the media.

disk side for reading or writing. A logic "1" on this pin means side 0 will be accessed, while a logic "0" means side 1 will be accessed.

DESCRIPTION OF PIN FUNCTIONS

BUFFER

PIN NO. NAME SYMBOL

7 nDirection

Control

8 nStep Pulse nSTEP OD48 This active low high current driver issues a

17 nDisk Change nDSKCHG IS This input senses that the drive door is open

4,3 nDrive Select

O,1

98 nDrive Select 2

nDIR OD48 This high current low active output

nDS0,1 OD48 Active low open drain outputs select drives

nDS2

TYPE DESCRIPTION

determines the direction of the head movement. A logic "1" on this pin means outward motion, while a logic "0" means inward motion.

low pulse for each track-to-track movement of the head.

or that the diskette has possibly been changed since the last drive selection. This input is inverted and read via bit 7 of I/O address 3F7H.

0-1. Refer to Note 2.

OD48

Active low open drain output selects drives

2. Refer to Note 2.

nDrive Select 3

PDIR

97 nDrive Select 3

I/O Address 10

2,5 nMotor On 0,1 nMTR0,1 OD48 These active low open drain outputs select

96 nMotor On 2 nMTR2

99 nMotor On 3 nMTR3

nDS3

PDIR

nDS3

A10

nPDACK

PDRQ

OD48

0D48IIn non-ECP mode: Active low open drain

OD48IMotor On 2: Refer to Note 1.

OD48

O24

In non-ECP mode: Active low open drain output selects drive 3. Refer to Note 2.

This bit is used to indicate the direction of the Parallel Port data bus. 0 = output/write 1 = input/read

output selects drive 3. Refer to Note 2. In ECP Mode, this pin is the A10 address

input.

motor drives 0-1. Refer to Note 1.

In ECP Mode, nMTR2 is the Parallel Port DMA Acknowledge input. Active Low.

Motor On 3: Refer to Note 1. In ECP Mode, MTR3 is the Parallel Port

DMA Request output. Active High.

DESCRIPTION OF PIN FUNCTIONS

BUFFER

PIN NO. NAME SYMBOL

1 Density Select DENSEL OD48 Indicates whether a low (250/300 Kb/s) or

14 nWrite

Protected

13 nTrack 00 nTR0 IS This active low Schmitt Trigger input senses

12 nIndex nINDEX IS This active low Schmitt Trigger input senses

19,18

Data Rate 0, Data Rate 1

nWRTPRT IS This active low Schmitt Trigger input senses

DRATE0, DRATE1

TYPE DESCRIPTION

high (500 Kb/s) data rate has been selected. This is determined by the IDENT bit in Configuration Register 3.

from the disk drive that a disk is write protected. Any write command is ignored.

from the disk drive that the head is positioned over the outermost track.

from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole.

O24IThese two outputs reflect bits 0 and 1

respectively of the Data Rate Register. At power on, these two outputs are in a high impedance state (refer to Table 50).

19,18

78,88 Receive Data RXD1,

79 Transmit Data TXD1

Media ID0, Media ID1

RXD2

PCF0

In Floppy Enhanced Mode 2 - These bits are the Media ID 0,1 inputs. The value of these bits can be read as bits 6 and 7 of the Floppy Tape register.

SERIAL PORT INTERFACE

I Receiver serial data input.

Transmitter serial data output from Primary Serial Port.

FDC37C666GT (Adapter Mode): Parallel Port Configuration Control 0. During reset active this input is read and latched to define the address of the Parallel Port.

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL

81 nRequest to

Send

nRTS1

BUFFER

TYPE DESCRIPTION

Active low Request to Send output for Primary Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). Forced inactive during loop mode operation.

Parallel Port Configuration Control

91 nRequest to

Send

Secondary Serial Port Configuration Control

PCF1

nRTS2

S2CF0

FDC37C666GT (Adapter Mode): Parallel Port Configuration Control 1. During reset active this input is read and latched to define the address of the Parallel Port.

Active low Request to Send output for Secondary Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). Forced inactive during loop mode operation.

FDC37C666GT (Adapter Mode): Secondary Serial Port Configuration Control 0. During Reset active this input is read and latched to define the address of the Secondary Serial Port.

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL

83 nData Terminal

Ready

IDE Configuration Control

93 nData Terminal

Ready

nDTR1

IDECF

nDTR2

BUFFER

TYPE DESCRIPTION

Active low Data Terminal Ready output for primary serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). Forced inactive during loop mode operation.

FDC37C666GT (Adapter Mode): IDE

Configuration Control. During reset active this input is read and latched to enable/disable the IDE.

Active low Data Terminal Ready output for secondary serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR), The hardware reset will reset the nDTR signal to inactive mode (high). Forced inactive during loop mode operation.

Secondary Serial Port Configuration Control 1

89 Transmit Data 2 TXD2

S2CF1

FDCCF

FDC37C666GT (Adapter Mode): Secondary

Serial Port Configuration Control 1. During reset active this input is read and latched to define the address of the Secondary Serial Port.

Transmitter Serial Data output from Secondary Serial Port.

FDC37C666GT (Adapter Mode): Floppy Disk Configuration. This input is read and latched during Reset to enable/disable the Floppy Disk Controller.

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL

82,92 nClear to Send nCTS1,

nCTS2

80,90 nData Set Ready nDSR1,

nDSR2

85,87 nData Carrier

Detect

nDCD1, nDCD2

BUFFER

TYPE DESCRIPTION

I Active low Clear to Send inputs for primary

and secondary serial ports. Handshake signal which notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS.

I Active low Data Set Ready inputs for

primary and secondary serial ports. Handshake signal which notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR.

I Active low Data Carrier Detect inputs for

primary and secondary serial ports. Handshake signal which notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD.

DESCRIPTION OF PIN FUNCTIONS

BUFFER

PIN NO. NAME SYMBOL

84,86 nRing Indicator nRI1, nRI2 I Active low Ring Indicator input for primary

94 Drive 2

DRV2

TYPE DESCRIPTION

and secondary serial ports. Handshake signal which notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR). A nRI signal state change from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nRI changes state. Note: Bit 6 of MSR is the complement of nRI.

In PS/2 mode, this input indicates whether a second drive is connected; DRV2 should be low if a second drive is connected. This status is reflected in a read of Status Register A. (Only available in FDC37C665GT. This pin must not be driven in the FDC37C666GT)

nADRx

Parallel Port Interrupt Request 2

nADRx

PINTR2

ECPEN

PARALLEL PORT INTERFACE

O24

Optional I/O port address decode output. Refer to Configuration registers CR3, CR8 and CR9 for more information. Active low. (Available in FDC37C665GT and FDC37C666GT.) Defaults to tri-state after power-up. This pin has a 30µa internal pullup.

This interrupt from the Parallel Port is enabled/disabled via bit 4 of the Parallel Port Control Register. Refer to configuration registers CR1 and CR3 for more information.

FDC37C666GT (Adapter Mode): Enhanced Parallel Port mode select. Refer to FDC37C666GT hardware configuration for more information. Read and latched during reset active.

DESCRIPTION OF PIN FUNCTIONS

BUFFER

PIN NO. NAME SYMBOL

73 nPrinter Select

Input

74 nInitiate Output nINIT OD24 This output is bit 2 of the printer control

76 nAutofeed

Output

77 nStrobe Output nSTROBE OD24 An active low pulse on this output is used to

61 Busy BUSY I This is a status output from the printer, a

62 nAcknowledge nACK I A low active output from the printer

nSLCTIN OD24 This active low output selects the printer.

nAUTOFD OD24 This output goes low to cause the printer to

TYPE DESCRIPTION

This is the complement of bit 3 of the Printer Control Register.

0P24 Refer to Parallel Port description for use of

this pin in ECP and EPP mode.

0P24 Refer to Parallel Port description for use of

this pin in ECP and EPP mode.

automatically feed one line after each line is printed. The nAUTOFD output is the complement of bit 1 of the Printer Control Register.

0P24 Refer to Parallel Port description for use of

this pin in ECP and EPP mode.

strobe the printer data into the printer. The nSTROBE output is the complement of bit 0 of the Printer Control Register.

0P24 Refer to Parallel Port description for use of

this pin in ECP and EPP mode.

high indicating that the printer is not ready to receive new data. Bit 7 of the Printer Status Register is the complement of the BUSY input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.

indicating that it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the nACK input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.

DESCRIPTION OF PIN FUNCTIONS

BUFFER

PIN NO. NAME SYMBOL

60 Paper End PE I Another status output from the printer, a

59 Printer Selected

Status

75 nError nERR I A low on this input from the printer indicates

71-68 66-63

100 IOCHRDY IOCHRDY OD24P In EPP mode, this pin is pulled low to

23 nIDE Low Byte

Port Data PD0-PD7 I/OP24 The bi-directional parallel data bus is used

Enable

SLCT I This high active output from the printer

nIDEENLO

TYPE DESCRIPTION

high indicating that the printer is out of paper. Bit 5 of the Printer Status Register reads the PE input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.

indicates that it has power on. Bit 4 of the Printer Status Register reads the SLCT input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.

that there is a error condition at the printer. Bit 3 of the Printer Status register reads the nERR input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.

to transfer information between CPU and peripherals.

extend the read/write command. This pin has an internal pull-up.

IDE

This active low signal is used in both the XT and AT mode. In the AT mode, this pin is active when the IDE is enabled and the I/O address is accessing 1F0H-1F7H and 3F6H-3F7H in primary address mode or 170H-177H and 376H,377H in secondary address mode. In the XT mode, this signal is active for accessing 320H-323H, 8 bit programmed I/O or DMA.

S1CF1

FDC37C666GT (Adapter Mode): Primary

Serial Configuration 1. Read and latched during reset active to select the address of the Secondary Serial Port.

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL

24 nIDE High Byte

Enable

nIDEENHI

BUFFER

TYPE DESCRIPTION

This signal is active low only in the AT mode, and when IO16CSB is also active. The I/O addresses for which this pin reacts are 1F0H-1F7H in primary address mode or 170H-177H in secondary address mode. This pin is not used in XT mode.

25 nHard Disk Chip

Select

26 nHard Disk Chip

Select

27 nI/O 16 Bit

Indicator

S1CF0

nHDCS0

IDEACF

nHDCS1

FACF

nIOCS16

FDC37C666GT (Adapter Mode): Primary Serial Configuration 0. Read and latched during reset active to define the address of the Secondary Serial Port.

O24IThis is the Hard Disk Chip select

corresponding to addresses 1F0H-1F7H in primary address mode or 170H-177H in secondary address mode in the AT mode and addresses 320H-323H in the XT mode.

FDC37C666GT (Adapter Mode): IDE Address Control. Refer to FDC37C666GT hardware configuration for more information. Read and latched during reset active.

O24IThis is the Hard Disk Chip select

corresponding to 3F6H,3F7H for primary address mode or 376H,377H for secondary address mode in the AT mode and addresses 3F6H,3F7H in the XT mode.

FDC37C666GT (Adapter Mode): Floppy Disk Address Control. Refer to FDC37C666GT hardware configuration for more information. Read and latched during reset active.

This input indicates, in AT mode only, when 16 bit transfers are to take place. This signal is generated by the hard disk interface. Logic "0" = 16 bit mode; logic "1" = 8 bit mode.

nHDACK

In the XT mode, this is the Hard Disk Controller DMA Acknowledge, low active.

DESCRIPTION OF PIN FUNCTIONS

BUFFER

PIN NO. NAME SYMBOL

22 IDE Data Bit 7 IDED7 I/O24 IDE data bit 7 in the AT mode. IDED7

58 Power Good PWRGD I FDC37C665GT (Motherboard Mode): This

TYPE DESCRIPTION

transfers data at I/O addresses 1F0H-1F7H (R/W), 3F6 (R/W), 3F7(W). IDED7 should be connected to IDE data bit 7. The FDC37C665GT functions as a buffer transferring data bit 7 between the IDE device and the host. During I/O read of 3F7H, IDED7 is the FDC disk change bit. In the XT mode, IDE7 is not used.

MISCELLANEOUS

input indicates that the power (VCC) is valid. For device operation, PWRGD must be active. When PWRGD is inactive, all inputs to the FDC37C665GT are disconnected and put in a low power mode, all outputs are put into high impedance. The contents of all registers are preserved as long as VCC has a valid value. The driver current drain in this mode drops to ISTBY - standby current. This input has a weak pullup resistor to VCC.

nGame Port Chip Select

20 CLOCK 1 X1/CLK1 ICLK The external connection for a parallel

21 CLOCK 2 X2/CLK2 OCLK 24 MHz crystal. If an external clock is used,

nGAMECS

PADCF

FDC37C666GT (Adapter Mode): This is the Game Port Chip Select output - active low. It will go active when the I/O address is 201H.

FDC37C666GT (Adapter Mode): Parallel Port Mode Control. Refer to FDC37C666GT hardware configuration for more information. Read and latched during reset active.

resonant 24 MHz crystal. A CMOS compatible oscillator is required if crystal is not used.

this pin should not be connected. This pin should not be used to drive any other drivers.

DESCRIPTION OF PIN FUNCTIONS

BUFFER

PIN NO. NAME SYMBOL

15,72 Power V

6,47,

Ground GND Ground pin.

67,95

Note 1: These active low open drain outputs select motor drives 0-3. In non-ECP modes, four drives

can be supported directly. These motor enable bits are controlled by software via the Digital Output Register (DOR). In ECP mode, MTR0,1 can be used to directly support 2 drives or can support 4 drives by using an external 2 to 4 decoder.

Note 2: Active low open drain outputs select drives 0-3. In non-ECP modes, four drives can be

supported directly. These drive select outputs are a decode of bits 0 and 1 of the Digital Output Register and qualified by the appropriate Motor Enable Bit of the DOR (bits 4-7). In ECP mode, DS0,1 can be used to directly support 2 drives or can support 4 drives by using an external 2 to 4 decoder.

TYPE DESCRIPTION

+ 5 Volt supply pin.

BUFFER TYPE DESCRIPTIONS

BUFFER TYPE DESCRIPTION

I/O24 Input/output. 24 mA sink; 12 mA source.

O24 Output. 24 mA sink; 12 mA source.

OD24 Output. 24 mA sink.

OD24P

OP24 Output. 24 mA sink; 4 mA source. OD48 Open drain. 48 mA sink.

O4 Output. 4 mA sink; 2.0 mA source. O8 Output. 8 mA sink; 4.0 mA source.

OCLK Output to external crystal

ICLK Input to Crystal Oscillator Circuit (CMOS levels)

I Input TTL compatible.

IS Input with Schmitt Trigger

Open drain. 24 mA sink; 30 µA source.

nHDSEL

nIOR

nIOW

AEN

A0-A9

DO-D7

FDRQ

nDACK

IRQ3

IRQ4

PINTR

PINTR2

FINTR

RESET

PDRQ

PDACK

A10

IOCHRDY

HOST

CPU

INTERFACE

SERIAL CLOCK

CLOCK

GEN

CLK 1 CLK2

(FDC37C665GT only) (FDC37C666GT only)Vcc (2) Vss (4)

POWER

MANAGEMENT

ADDRESS BUS

82077 COMPATIBLE

nINDEX

nTRK0

nDSKCHG

nWRPRT

nWGATE

SMSC

PROPRIETARY

VERTICAL

FLOPPYDISK

CONTROLLER

CORE

DENSEL

nDIR

nSTEP DRATE0 DRATE1

nGAMECSPWRGD

DECODER

DATA BUS

CONFIGURATION

REGISTERS

CONTROL BUS

WDATA

WCLOCK

RCLOCK

RDATA

nDS0,1,2,3

nMTR0,1,2,3

DIGITAL

DATA SEPARATOR WITH WRITE

PRECOM-

PENSATION

nWDATA nRDATA

MULTI-MODE

PARALLEL PORT/FDC

MUX

16C550

COMPATIBLE

SERIAL PORT 1

16C550

COMPATIBLE

SERIAL PORT 2

IDE

INTERFACE

PDIR

PD0-7

BUSY, SLCT, PE, nERROR, nACK

nSTROBE, nSLCTIN, nINIT, nAUTOFD

TXD1, nCTS1, nRTS1 RXD1

nDSR1, nDCD1, nRI1, nDTR1

TXD2, nCTS2, nRTS2 RXD2

nDSR2, nDCD2, nRI2, nDTR2

nIDEENLO, nIDEENHI IDED7 nHDCS0, nHDCS1 nIOCS16

FIGURE 1 - FDC37C665GT/FDC37C666GT BLOCK DIAGRAM

FDC37C665GT

20 pF

FDC36C666GT

CLOCK 1

CLOCK 2

24 MHz CRYSTAL

20 pF

FIGURE 2 - SUGGESTED 24 MHz OSCILLATOR CIRCUIT

FUNCTIONAL DESCRIPTION

SUPER I/O REGISTERS

The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, IDE, serial and parallel ports can be moved via the configuration registers. Some addresses are used to access more than one register.

Table 1 - FDC37C665GT/666GT Block Addresses

ADDRESS BLOCK NAME NOTES

3F0, 3F1 Configuration Write only; Note 1, 2 3F0, 3F1 Floppy Disk Read only; Address at power

3F2, 3F3, 3F4, 3F5, 3F7 Floppy Disk Address at power up; Note 2 3F8-3FF Serial Port Com 1 Address at power up; Note 2 2F8-2FF Serial Port Com 2 Address at power up; Note 2 278-27A Parallel Port Address at power up; Note 2 1F0-1F7, 3F6, 3F7 IDE AT Mode; Note 2, 3

Note 1: Configuration registers can only be modified in configuration mode, entered only by writing a

security code sequence to 3F0. The configuration registers can only be read in configuration mode by accessing 3F1. Access to status registers A and B of the floppy disk is disabled in configuration mode. Outside of configuration mode, a read of 3F0 accesses status register A

and a read of 3F1 accesses status register B of the floppy disk. Note 2: Address at power up; These addresses can be changed in the configuration setup. Note 3: Addresses 320H-323H and 3F5-3F7H for XT Mode. Selectable in configuration setup.

HOST PROCESSOR INTERFACE

The host processor communicates with the FDC37C665GT/666GT through a series of read/write registers. The port addresses for these registers are shown in Table 1. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide except the IDE data register at port 1F0H which is 16 bits wide. All host interface output buffers are capable of sinking a minimum of 24 mA.

up; Note 2

FLOPPY DISK CONTROLLER

The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection.

The FDC37C665GT and FDC37C666GT are compatible to the 82077AA using SMSC's proprietary floppy disk controller core.

Table 2 - Status, Data and Control Registers

PRIMARY ADDRESS

3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7

SECONDARY

ADDRESS REGISTER

370 371 372 373 374 374 375

R R/W R/W

R/W

376 377 377

FLOPPY DISK CONTROLLER INTERNAL REGISTERS

The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected.

Status Register A Status Register B Digital Output Register Tape Drive Register Main Status Register Data Rate Select Register Data (FIFO)

SRA SRB

DOR

TSR MSR DSR FIFO

Reserved Digital Input Register Configuration Control Register

DIR

CCR

For information on the floppy disk on Parallel Port pins, refer to Configuration Register CR4 and Parallel Port Floppy Disk Controller description.

STATUS REGISTER A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state of the FINTR pin and several disk interface pins,

PS/2 Mode

7 6 5 4 3 2 1 0

INT

nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR

PENDING

RESET

0 N/A 0 N/A 0 N/A N/A 0

COND.

in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0.

BIT 0 DIRECTION

Active high status indicating the direction of head movement. A logic "1" indicating inward direction a logic "0" outward.

BIT 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic "0" indicating that the disk is write protected.

BIT 2 nINDEX

Active low status of the INDEX disk interface input.

BIT 3 HEAD SELECT

Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0.

BIT 4 nTRACK 0

Active low status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the STEP output disk interface output pin.

BIT 6 nDRV2

Active low status of the DRV2 disk interface input pin, indicating that a second drive has been installed.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

PS/2 Model 30 Mode

RESET COND.

7 6 5 4 3 2 1 0

INT

PENDING

0 0 0 N/A 1 N/A N/A 1

DRQ STEP

F/F

TRK0 nHDSEL INDX WP nDIR

BIT 0 nDIRECTION

Active low status indicating the direction of head movement. A logic "0" indicating inward direction a logic "1" outward.

BIT 1 WRITE PROTECT

Active high status of the WRITE PROTECT disk interface input. A logic "1" indicating that the disk is write protected.

BIT 2 INDEX

Active high status of the INDEX disk interface input.

BIT 3 nHEAD SELECT

Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0.

BIT 4 TRACK 0

Active high status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset.

BIT 6 DMA REQUEST

Active high status of the DRQ output pin.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

STATUS REGISTER B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state of several disk interface pins, in PS/2 and Model

PS/2 Mode

7 6 5 4 3 2 1 0

RESET

1 1 DRIVE

SEL0

1 1 0 0 0 0 0 0

WDATA

TOGGLE

COND.

30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1.

RDATA

TOGGLE

WGATE MOT

EN1

MOT

EN0

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset, it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic "1".

BIT 7 RESERVED

Always read as a logic "1".

PS/2 Model 30 Mode

nDRV2 nDS1 nDS0 WDATA

RESET COND.

7 6 5 4 3 2 1 0

F/F

RDATA

F/F

WGATE

F/F

nDS3 nDS2

N/A 1 1 0 0 0 1 1

BIT 0 nDRIVE SELECT 2

Active low status of the DS2 disk interface output.

BIT 1 nDRIVE SELECT 3

Active low status of the DS3 disk interface output.

BIT 2 WRITE GATE

Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register.

BIT 3 READ DATA

Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register.

BIT 4 WRITE DATA

Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface output.

BIT 7 nDRV2

Active low status of the DRV2 disk interface input.

DIGITAL OUTPUT REGISTER (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enables of the disk interface outputs. It also

7 6 5 4 3 2 1 0

MOT

EN3

RESET

MOT

EN2

MOT

EN1

0 0 0 0 0 0 0 0

COND.

contains the enable for the DMA logic and contains a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time.

MOT

EN0

DMAEN nRESETDRIVE

SEL1

DRIVE

SEL0

BIT 0 and 1 DRIVE SELECT

These two bits a are binary encoded for the four drive selects DS0-DS3, thereby allowing only one drive to be selected at a time.

BIT 2 nRESET

A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. This bit being a logic "0" will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance state. This bit is a logic "0" after a reset and in these modes.

PS/2 Mode: In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0".

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 6 MOTOR ENABLE 2

This bit controls the MTR2 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 7 MOTOR ENABLE 3

This bit controls the MTR3 disk interface output. A logic "1" in this bit causes the output to go active.

Table 3 - Drive Activation Values

DRIVE DOR VALUE

0 1 2 3

1CH 2DH 4EH 8FH

TAPE DRIVE REGISTER (TDR)

Address 3F3 READ/WRITE

This register is included for 82077 software compatability. The robust digital data separator used in the FDC37C665GT does not require its characteristics modified for tape support. The contents of this register are not used internal to the device. The TDR is unaffected by a software reset. Bits 2-7 are tri-stated when read in this mode.

TAPE SEL1 TAPE SEL2

Table 4- Tape Select Bits

0 0 1 1

0 1 0 1

DRIVE

SELECTED

None

1 2 3

Table 5 - Internal 4 Drive Decode - Normal

DIGITAL OUTPUT REGISTER DRIVE SELECT OUTPUTS

(ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS3 nDS2 nDS1 nDS0 nMTR3 nMTR2 nMTR1 nMTR0

X X X 1 0 0 1 1 1 0 nBIT 7 nBIT 6 nBIT 5 nBIT 4 X X 1 X 0 1 1 1 0 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4 X 1 X X 1 0 1 0 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4

1 X X X 1 1 0 1 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4 0 0 0 0 X X 1 1 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4

MOTOR ON OUTPUTS

(ACTIVE LOW)

Table 6 - Internal 4 Drive Decode - Drives 0 and 1 Swapped

DIGITAL OUTPUT REGISTER DRIVE SELECT OUTPUTS

(ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS3 nDS2 nDS1 nDS0 nMTR3 nMTR2 nMTR1 nMTR0

X X X 1 0 0 1 1 0 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5 X X 1 X 0 1 1 1 1 0 nBIT 7 nBIT 6 nBIT 4 nBIT 5 X 1 X X 1 0 1 0 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5

1 X X X 1 1 0 1 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5 0 0 0 0 X X 1 1 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5

MOTOR ON OUTPUTS

(ACTIVE LOW)

Table 7 - External 2 to 4 Drive Decode - Normal

DRIVE SELECT

DIGITAL OUTPUT REGISTER

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X X X 1 0 0 0 0 1 0 X X 1 X 0 1 0 1 1 0 X 1 X X 1 0 1 0 1 0

1 X X X 1 1 1 1 1 0 X X X 0 0 0 0 0 1 1 X X 0 X 0 1 0 1 1 1 X 0 X X 1 0 1 0 1 1

0 X X X 1 1 1 1 1 1

OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Table 8 - External 2 to 4 Drive Decode - Drives 0 and 1 Swapped

DRIVE SELECT

DIGITAL OUTPUT REGISTER

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X X X 1 0 0 0 1 1 0 X X 1 X 0 1 0 0 1 0 X 1 X X 1 0 1 0 1 0

1 X X X 1 1 1 1 1 0 X X X 0 0 0 0 1 1 1 X X 0 X 0 1 0 0 1 1 X 0 X X 1 0 1 0 1 1

0 X X X 1 1 1 1 1 1

OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

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SMSC FDC37C665GT, FDC37C666GT Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual