SMSC COM20020I 3.3V DATASHEET

COM20020I 3.3V

5Mbps ARCNET (ANSI

878.1) Controller with
2K x 8 On-Chip RAM

Datasheet

Product Features

 New Features:

- Data Rates up to 5 Mbps

- Programmable Reconfiguration Times
 28 Pin PLCC and 48 Pin TQFP Packages;

Lead-free RoHS Compliant Packages also
available

 Ideal for Industrial/Factory/Building Automation

and Transportation Applications

 Deterministic, (ANSI 878.1), Token Passing

ARCNET Protocol

 Minimal Microcontroller and Media Interface

Logic Required

 Flexible Interface For Use With All

Microcontrollers or Microprocessors

 Automatically Detects Type of Microcontroller

Interface

 2Kx8 On-Chip Dual Port RAM
 Command Chaining for Packet Queuing
 Sequential Access to Internal RAM
 Software Programmable Node ID

 Eight, 256 Byte Pages Allow Four Pages TX and

RX Plus Scratch-Pad Memory

 Next ID Readable
 Internal Clock Scaler and Clock Multiplier for

Adjusting Network Speed

o

 Operating Temperature Range of -40
 Self-Reconfiguration Protocol
 Supports up to 255 Nodes
 Supports Various Network Topologies (Star, Tree,

Bus...)

 CMOS, Single +3.3V Supply
 Duplicate Node ID Detection
 Powerful Diagnostics
 Receive All Packets Mode
 Flexible Media Interface:

- Traditional Hybrid Interface For Long
Distances up to Four Miles at 2.5Mbps

- RS485 Differential Driver Interface For Low
Cost, Low Power, High Reliability

C to +85oC

SMSC COM20020I 3.3V 1 Revision 12-06-06

DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

ORDERING INFORMATION

Order Numbers:

COM20020I3VLJP for 28 pin PLCC package

COM20020I3V-DZD for 28 pin PLCC package lead-free RoHS co mpliant package

COM20020I3V-HD for 48 pin TQFP package

COM20020I3V-HT for 48 pin TQFP lead-free RoHS compliant package

Hauppauge, NY 11788
[phone]
FAX [phone]

80 Arkay Drive

Copyright © 2006 SMSC or its subsidiaries. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY
DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR
REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC
OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHET HER OR NOT ANY REMEDY OF BUYER IS HELD TO
HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.

Revision 12-06-06 SMSC COM20020I 3.3V

2

DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

TABLE OF CONTENTS

2.0

GENERAL DESCRIPTION..............................................................................................................................5

3.0 PIN CONFIGURATIONS.................................................................................................................................6

4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP ..........................................................................................8

5.0 PROTOCOL DESCRIPTION.........................................................................................................................11

5.1 NETWORK PROTOCOL ..................................................................................................................................11

5.2 DATA RATES ...............................................................................................................................................11

5.3 NETWORK RECONFIGURATION.......................................................................................................................12

5.4 BROADCAST MESSAGES...............................................................................................................................12

5.5 EXTENDED TIMEOUT FUNCTION.....................................................................................................................12

5.6 LINE PROTOCOL ..........................................................................................................................................13

6.0 SYSTEM DESCRIPTION...............................................................................................................................15

6.1 MICROCONTROLLER INTERFACE ....................................................................................................................15

6.2 TRANSMISSION MEDIA INTERFACE .................................................................................................................19

7.0 FUNCTIONAL DESCRIPTION...................................................................................................................... 24

7.1 MICROSEQUENCER ......................................................................................................................................24

7.2 INTERNAL REGISTERS...........................................................................................................................25

7.3 INTERNAL RAM ............................................................................................................................................35

7.4 COMMAND CHAINING....................................................................................................................................40

7.5 INITIALIZATION SEQUENCE ............................................................................................................................42

7.6 IMPROVED DIAGNOSTICS ..............................................................................................................................42

8.0 OPERATIONAL DESCRIPTION...................................................................................................................45

8.1 MAXIMUM GUARANTEED RATINGS*................................................................................................................45

8.2 DC ELECTRICAL CHARACTERISTICS ...............................................................................................................45

9.0 TIMING DIAGRAMS......................................................................................................................................48

10.0 PACKAGE OUTLINES..................................................................................................................................60

11.0 APPENDIX A.................................................................................................................................................62

12.0 APPENDIX B.................................................................................................................................................65

12.1 SOFTWARE IDENTIFICATION OF THE COM20020I REV B, REV C AND REV D .....................................................65

LIST OF FIGURES

Figure 1 - COM20020I OPERATION ...........................................................................................................................10

Figure 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE...............................................16

Figure 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE......................................17

Figure 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE...............................................................................18

Figure 5 - COM20020 I NETWORK USING RS-485 D I F F ERENTIAL TR A NSCEIVERS................................................20

Figure 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0.............................................................................................20

Figure 7 - INTERNAL BLOCK DIAGRAM....................................................................................................................22

Figure 8 – SEQUENTIAL ACCESS OPERATION........................................................................................................35

Figure 9 – RAM BUFFER PACKET CONFIGURATION ..............................................................................................38

Figure 10 - COMMAND CHAINING STATUS REGISTER QUEUE...............................................................................40

Figure 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE..................................................48

Figure 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE..................................................49

Figure 13 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................50

SMSC COM20020I 3.3V Page 3 Revision 12-06-06

DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Figure 14 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................51

Figure 15 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE.........................................52

Figure 16 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE.........................................53

Figure 17 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE.........................................54

Figure 18 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE.........................................55

Figure 19 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE .......................................56

Figure 20 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE .......................................57

Figure 21 – NORMAL MODE TRANSMIT OR RECEIVE TIMING...............................................................................58

Figure 22 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING.........................................................................58

Figure 23 – TTL INPUT TIMING ON XTAL1 PIN.........................................................................................................59

Figure 24 – RESET AND INTERRUPT TIMING...........................................................................................................59

Figure 25 - 28 PIN PLCC PACKAGE DIMENSIONS ...................................................................................................60

Figure 26 - 48 PIN TQFP PACKAGE OUTLINE...........................................................................................................61

Figure 27 - EFFECT OF THE EF BIT ON THE TA/RI BIT...........................................................................................63

LIST OF TABLES

Table 1 - Typical Media................................................................................................................................................23

Table 2 - Read Register Summary...............................................................................................................................24

Table 3 - Write Register Summary...............................................................................................................................25

Table 4 - Status Register..............................................................................................................................................28

Table 5 - Diagnostic Status Re gister.............................................................................................................................29

Table 6 - Command Register........................................................................................................................................30

Table 7 - Address Pointer High Register.......................................................................................................................31

Table 8 - Address Pointer Low Register........................................................................................................................31

Table 9 - Sub Address Reg i ster...................................................................................................................................31

Table 10 - Configuration Register ................................................................................................................................31

Table 11 - Setup 1 Register..........................................................................................................................................33

Table 12 - Setup 2 Register..........................................................................................................................................34

Revision 12-06-06 SMSC COM20020I 3.3V

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5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

2.0 General Description

SMSC's COM20020I is a member of the family of Embedded ARCNET Controllers from Standard Microsystems
Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent
peripherals in industrial, automotive, and embedded control environments using an ARCNET
flexible microcontroller and media interfaces, eight-page message support, and extended temperature range of the
COM20020I make it the only true network controller optimized for use in industrial, embedded, and automotive
applications. Using an ARCNET protocol engine is the ideal solution for embedded control applications because it
provides a deterministic t oken-passing protocol, a hig hly reliable and proven net working scheme, a nd a data rate of u p
to 5 Mbps when using the COM20020I.

A token-passing protocol provides predictable response times because each network event occurs within a
predetermined time interval, based upon the number of nodes on the network. The deterministic nature of ARCNET is
essential in real time applications. T he integration of the 2Kx8 RAM buffer on-chip, the Command Chaining feature, the
5 Mbps maximum data rate, and the internal diagnostics make the COM20020I the highest performance embedded
communications device available. With only one COM20020I and one microcontroller, a complete communications node
may be implemented.

For more details on the ARCNET protocol engine and traditional dipulse signaling schemes, please refer
to the ARCNET Local Area Network Standard
ARCNET Designer's Handbook

For more detailed information o n cabling optio ns including RS485 , transforme r-coupled RS- 485 and Fiber
Optic interfaces, please refer to the following technical note which is available from Standard
Microsystems Corporation: Techn ical Not e 7- 5 - Cabling Guid elin es for the COM20 020I ULA NC.

, available from Datapoint Corporation.

, available from Standard Microsystems Corporation or the

protocol engine. The

SMSC COM20020I 3.3V Page 5 Revision 12-06-06

DATASHEET

3.0 PIN CONFIGURATIONS

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

A0/nMUX

A2/ALE

1

2

A1

3

AD0

4

AD1

5

AD2

6

D3

7

D4

8

D5

9
10

D6

11

D7

12

VSS

Package: 28-Pin PLCC

Pac kag es: 24-Pin DIP or 28-Pin PLCC

Ordering Information:

Ordering Information:

COM20020 I P

COM20019

N

I
T

E

N

S

24

VDD

23

nRD/nDS

22

nWR/DIR

21

nCS

20

nINTR

19

nRESET IN

18

nTXEN

17

RXIN
nPULSE2

16

15

nPULSE1

14

XTAL2

13

XTAL1

I

P

PACKAGE TYPE: P = Plastic , LJP = PLCC

PACKAGE TYPE: P = Plastic, LJP = PLCC

nWR/DIR

nRD/nDS

VDD

A0/nMUX

A1

A2/ALE

AD0

TR

S

N

I

C

n

n

25 24 23 22 21 20 19

26

27

28

1

2

3

4

567891011

2

1

D

D

A

A

E

S

E

S

R

TX

n

V

n

3

S

D

S
V

TEMP RANGE: (Blank) = Commercial: 0°C to +70°C

TEMP RANGE: 1 = Industrial: -40° C to 75° C

I = Industrial: -40°C to +85°C

DEVICE TYPE: 20020 = Universal Local Area Network

DEVICE TYPE: 20019 = Universal Local Area Network Controller

(with 2K x 8 RAM)

(with 2K x 8 RAM)

2
E
S

L

N

I

U

X

P

R

n

nPULSE 1

18

17

XTAL2

16

XTAL1

15

VDD

VSS

14

13

N/C

12

D7

6

5

4

D

D

D

Revision 12-06-06 SMSC COM20020I 3.3V

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DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

N/C

N/C

A2/ALEA1A0/nMUX

48

47

46

45

AD0
AD1

N/C

AD2

1
2
3
4

COM20020I

N/C

VSS

D3

VDD

D4
D5

VSS

D6

5
6
7
8

9
10
11
12

48 PIN TQFP

44

VDD

N/C

43

424140

VSS

N/C

nRD/nDS

VDD

nWR/DIR

39

38

37

36
35
34
33
32
31
30
29
28
27
26
25

nCS
VDD
nINTR
N/C
VDD
nRESET
VSS
nTXEN
RXIN
N/C
BUSTMG
nPULSE2

13

14

15

16

17

18

D7

192021

N/C

N/C

N/C

N/C

VSS

N/C

VDD

22

XTAL1

XTAL2

23

VSS

24

nPULSE1

SMSC COM20020I 3.3V Page 7 Revision 12-06-06

DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP

PIN NO NAME SYMBOL I/O DESCRIPTION

MICROCONTROLLER INTERFACE

44, 45,

46

1, 2, 4,

7, 9, 10,

12, 13

47, 48,

3, 5,

14-17

37 nWrite/

39 nRead/

31 nReset In nRESET IN Hardware reset signal. Active Low.
34 nInterrupt nINTR OUT Interrupt signal output. Active Low.
36

42 N/C N/C OUT Non-connection
26

33 N/C N/C OUT
35

38

40 N/C N/C Non-connection

Address
0-2

Data 0-7

N/C N/C I/O Non-connection

Direction

nData
Strobe

nChip
Select

Read/Write
Bus Timing
Select

Power
Supply

Power
Supply

A0/nMUX
A1

A2/ALE
AD0-AD2,

D3-D7

nWR/DIR IN

nRD/nDS IN

nCS IN Chip Select input. Active Low.

BUSTMG IN

VDD PWR

VDD PWR +3.3 volts power supply pins.

IN

On a non-multiplexed mode, A0-A2 are address
input bits. (A0 is the LSB) On a multiplexed

IN

address/data bus, nMUX tied Low, A1 is left open,
and ALE is tied to the Address Latch Enable signal.

IN

A1 is connected to an internal pull-up resistor.

I/O

On a non-multiplexed bus, these signals are used as
the lower byte data bus lines. On a multiplexed
address/data bus, AD0-AD2 act as the address lines
(latched by ALE) and as the low data lines. D3-D7
are always used for data only. These signals are
connected to internal pull-up resistors.

nWR is for 80xx CPU, nWR is Write signal input.
Active Low.

DIR is for 68xx CPU, DIR is Bus Direction signal
input. (Low: Write, High: Read.)

nRD is for 80xx CPU, nRD is Read signal input.
Active Low.

nDS is for 68xx CPU, nDS is Data Strobe signal
input. Active Low.

Read and Write Bus Access Timing mode selecting
signal. Status of this signal effects CPU and DMA
Timing.

L: High speed timing mode (only for non-multiplexed

bus)
H: Normal timing mode
This signal is connected to internal pull-up registers.

Revision 12-06-06 SMSC COM20020I 3.3V

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DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

PIN NO NAME SYMBOL I/O DESCRIPTION

TRANSMISSION MEDIA INTERFACE

24

25

28 Receive In RXIN IN

29

21
22

8, 20,

32, 35,

38, 43

6, 11,

18, 23,

30, 41

3, 5,

14-17,
19, 27,
33, 40,

42, 48

nPulse 1

nPulse 2

nTransmit
Enable

Crystal
Oscillator

Power
Supply

Ground VSS PWR Ground pins.

N/C N/C Non-connection

nPULSE1

nPULSE2

nTXEN OUT

XTAL1
XTAL2

VDD PWR +5 Volt power supply pins.

OUT

I/O

IN

OUT

In Normal Mode, these active low signals carry the
transmit data information, encoded in pulse format as
DIPULSE waveform. In Backplane Mode, the
nPULSE1 signal driver is programmable (push/pull or
open-drain), while the nPULSE2 signal provides a
clock with frequency of doubled data rate. nPULSE1
is connected to a weak internal pull-up resistor on
the open/drain driver in backplane mode.

This signal carries the receive data information from
the line transceiver.

Transmission Enable signal. Active polarity is
programmable through the nPULSE2 pin.

nPULSE2 floating before power-up;
nTXEN active low
nPULSE2 grounded before power-up;
nTXEN active high (this option is only available in

Back Plane mode)
An external crystal should be connected to these

pins. Oscillation frequency range is from 10 MHz to
20 MHz. If an external TTL clock is used instead, it
must be connected to XTAL1 with a 390ohm pull-up
resistor, and XTAL2 should be left floating.

SMSC COM20020I 3.3V Page 9 Revision 12-06-06

DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

1

Reconfigure
Timer has
Timed Out

Power On

Send

Reconfigure

Burst

Read Node ID

Write ID to

RAM Buffer

Set NID= ID

Start
Reconfiguration
Timer (420 mS)*

Y

Invitation

to Transmit to

this ID?

N

No
Activity
for 37.4

us?

N

No

Activity

for 37.4

us?

Y

Set TA

Pass the

Token

NY

RI?

YN

SOH?

NY

Write S ID
to Buffer

Y

DID
=0?

N

Broadcast

DID

=ID?

Y

Write B u ffer
with Packet

CRC
OK?

LENGTH

OK?

DID
=0?

N

DID

=ID?

Y

SEND ACK

Enabled?

N

N

Y

N

Y

Y

N

No Activity

for 41

Set NID= ID

N

Start Timer:

Y

Set RI

T=(255-ID)

x 73 us

Activity

On Line?

N

T=0?

N

uS?

Y

Y

N

Y

1

YN

TA?

Trans mi t

NAK

Trans mi t

Broadcast?

Y

Send

Packet

Was Packet
Broadcast?

N

No
Activity
for 37.4

us?

N

N

-

ID refers to the identification number of the ID assigned to this node.

-

NID refers to the next identification number that receives the token
after this ID passes it.

-

SID refers to the source identif i cation.

-

DID refers to the destination identification.

-

SOH refers to the start of header character; preceeds all data packets.

* Reconfig timer is programmable via setup2 register bit s 1, 0.
Note - All time values are valid for 5 Mbps.

Y

ACK? Set TMA

ACK

N

Y

Y

Set TA

YN

Free Buffer

Enquiry to

Y

Free Buffer

Increment

this ID?

N

RI?

Tran s m it
Enquiry

N

YN

ACK?

Y

NAK?

NID

FIGURE 1 - COM20020I OPERATION

Revision 12-06-06 SMSC COM20020I 3.3V

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DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5.0 PROTOCOL DESCRIPTION

5.1 Network Protocol

Communication on the network is based on a token passing protocol. Establishment of the network configuration and
management of the network protocol are handled entirely by the COM20020I's internal microcoded sequencer. A
processor or intelligent peripheral transmits data by simply loading a data packet and its destination ID into the
COM20020I's internal RAM buffer, and issuing a command to enable the transmitter. When the COM20020I next
receives the token, it verifies that the receiving node is ready by first transmitting a FREE BUFFER ENQUIRY message.
If the receiving node transmits an ACKnowledge message, the data packet is transmitted followed by a 16-bit CRC. If
the receiving node cannot accept the packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge
message and the transmitter passes the token. Once it has been established that the re ceiving node can accept the
packet and transmission is co mplete, the receiving node verifies the p acket. If the packet is rec eived successfully, t he
receiving node transmits an ACKnowledge message (or nothing if it is not received successfully) allowing the transmitter
to set the appropriate status bits to indicate successful or unsucce ssfu l delivery of the packet. An interrupt mask permits
the COM20020I to generate an interrupt to the processor when selected status bits become true. Figure 1 is a flow
chart illustrating the inte rn al operation of the COM20020I connected to a 20 MHz crystal oscillator.

5.2 Data Rates

The COM20020I is capable of supporting data rates from 156.25 Kbps to 5 Mbps. The following protocol description
assumes a 5 Mbps data rate. To attain the faster data rates, the clock frequency may be doubled by the internal clock
multiplier (see next section). For slower data rates, an internal clock divider scales down the clock frequency. Thus all
timeout values are scaled as shown in the following table:

Example: IDLE LINE Timeout @ 5 Mbps = 41 μs. IDLE LINE Timeout for 156.2 Kbps is 41 μs * 32 = 1.3 ms

INTERNAL

CLOCK

FREQUENCY

40 MHz Div. by 8 5 Mbps 1
20 MHz Div. by 8

Selecting Clock Frequencies Above 2.5 Mbps
To realize a 5 Mbps network, an external 40 MHz clock mus t be input. H owever, since 40 MHz is near t he frequenc y
of FM radio band, it is not practical for use for noise emission reasons. Therefore, higher frequency clocks are
generated from the 20 MHz crystal as selected through two bits in the Setup2 register, CKUP[1,0] as shown below.
The selected clock is supplied to the ARCNET controller.

CKUP1 CKUP0 CLOCK FREQUENCY (DATA RATE)

0 0 20 MHz (Up to 2.5Mbps) Default (Bypass)
0 1 40 MHz (Up to 5Mbps)
1 0 Reserved
1 1 Reserved

This clock multiplier is powered-down (bypassed) on default. After changing the CKUP1 and CKUP0 bits, the
ARCNET core operation is stopped and the internal P LL in the clock ge nerator is awakened an d it starts to generate
the 40 MHz. The lock out time of the internal PLL is 8uSec t ypically. After more than 8 μsec (this wait time is defined
as 1 msec in this data sheet), it is necessary to write c ommand data '18H' to the command register to re-start the
ARCNET core operation. This clock generator is called “clock multiplier”.

Changing the CKUP1 and CKUP0 bits must be one time or less after releasing hardware reset.

CLOCK

PRESCALER

Div. by 16
Div. by 32
Div. by 64

Div. by 128

DATA RATE

2.5 Mbps

1.25 Mbps
625 Kbps

312.5 Kbps

156.25 Kbps

TIMEOUT SCALING

FACTOR (MULTIPLY BY)

2
4

8
16
32

SMSC COM20020I 3.3V Page 11 Revision 12-06-06

DATASHEET

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

The EF bit in the SETUP2 register must be set when the data rate is over 5 Mbps.

5.3 Network Reconfiguration

A significant advantage of the COM20020I is its ability to adapt to ch anges on the n etwork. Whenever a new node is
activated or deactivated, a NETWORK RECONFIGURATION is perform ed. When a new COM20020I is turned on
(creating a new active node on the network), or if the COM20020I has not received an INVITATION TO TRANSMIT
for 420mS, or if a software reset occurs, the COM20020I causes a NETWORK RECONFIGURATION by sending a
RECONFIGURE BURST consisting of eight marks and one space repeated 765 tim es. The pur pose of this burst is to
terminate all activity on the network. Since this burst is longer than any other type of transmission, the burst will
interfere with the next INVITATION TO TRANSMIT, destroy the token and keep any other node from assuming
control of the line.

When any COM20020I senses an idle line for greater than 41 μS, which occurs only when the token Is lost, each
COM20020I starts an internal timeout equal to 73μs times t he quantit y 255 minus its own ID. The CO M20020I starts
network reconfiguration by sending an invitation to transm it first to itself and then to all ot her nodes by decrementing
the destination Node ID. If the timeout expires with no line activity, the COM20020I star ts sending INVITATION TO
TRANSMIT with the Destination ID (DID) equal to the currently stored NID. Within a given network, only one
COM20020I will timeout (the one with the highest ID number). After sending the INVITATION TO TRANSMIT, the
COM20020I waits for activity on the line. If there is no activity for 37.4μS, the COM20020I increments the NID value
and transmits another INVITATION TO TRANSMIT using the NID equal to the DID. If activity appears before the

37.4μS timeout expires, the COM20020I releases control of the line. During NETWORK RECONFIGURATION,
INVITATIONS TO TRANSMIT are sent to all NIDs (1-255).

Each COM20020I on the network will finally have saved a NID value equal to the ID of the COM20020I that it
released control to. At this point, control is passed directly from o ne node to the next with no wasted INVIT ATIONS
TO TRANSMIT being sent to ID's not on the network, until the ne xt NETWORK RECONFIGURATION occurs. When
a node is powered off, the previous node attempts to pass the token to it by issuing an INVITATION TO TRANSMIT.
Since this node does not respond, the previ ous node tim es out an d transmits another IN VITAT ION TO T RANSMIT to
an incremented ID and eventually a response will be received.

The NETWORK RECONFIGURATION time depends on the number of nodes in the net work, the propagation delay
between nodes, and the highest ID number on the network, but is typically within the range of 12 to 30.5 mS.

5.4 Broadcast Messages

Broadcasting gives a particular node the ability to transmit a data packet to all n odes on the net work simultaneously.
ID zero is reserved for this feature and no node on the network can be a ssigned ID zero. To broadcast a message,
the transmitting node's processor simply loads the RAM buffer with the data packet and sets the DID equal to zero.
Figure 4 illustrates the position of each byte in the packet with the DID residing at address 0X01 or
Hex of the current page selected in the "Enable T ransmit from Page fnn" command. Each individual node has the
ability to ignore broadcast messages by setting the most significa nt bit of th e "Enab le Rec eive to Pa ge fn n" comm and
to a logic "0".

5.5 Extended Timeout Function

There are three timeouts associated with the COM20020I operation. The values of these timeouts are
controlled by bits 3 and 4 of the Configuration Register and bit 5 of the Setup 1 Register.

Response Time

The Response Time determines the maximum propagation delay allowed between any two nodes, and should be
chosen to be larger than the round trip propagation delay between the two furthest nodes on the network plus the
maximum turn around time (the time it takes a particular COM20020I to start sending a message in response to a
received message) which is a pproximately 6.4 μS. The round trip propagation delay is a function of the transmission
media and network topology. For a typical system using RG62 coax in a baseband system, a one way cable
propagation delay of 15.5 μS translates to a distance of about 2 miles. The flow chart in Figure 1 uses a value of 37.4
S (15.5 + 15.5 + 6.4) to determine if any node w ill re spond.

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Idle Time

The Idle Time is associated wit h a NETWORK RECONFIGURATION. Figure 1 illustrates that during a NETWORK
RECONFIGURATION one node will continually transmit INVITATIONS TO TRANSMIT until it encounters an active
node. All other nodes on the network must distinguish between this operation and an entirely idle line. During
NETWORK RECONFIGURATION, activity will appear on the line every 41 μS. This 41 μS is equal to the Response
Time of 37.4 μS plus the time it takes the COM20020I to start retransmitting another message (usually another
INVITATION TO TRANSMIT).

Reconfiguration Time
If any node does not receive the token within the Reconfiguration Time, the node will initiate a NETWORK
RECONFIGURATION. The ET 2 and ET1 bits of the Configuration Register allow the network to operate over longer
distances than the 2 miles stated earlier. The logic levels on these bits control the maximum distances over which the
COM20020I can operate by controlling the three timeout values described above. For proper network operation, all
COM20020I's connected to the same network must have the same Response Time, Idle Time, and Reconfiguration
Time.

5.6 Line Protocol

The ARCNET line protocol is considered isochronous because each byte is preceded by a start interval and ended with
a stop interval. Unlike asynchronous protocols, there is a constant amount of time separating each data byte. On a 5
Mbps network, each byte takes exactly 11 clock intervals of 200ns each. As a result, one byte is transmitted every 2.2
S and the time to transmit a mes sag e ca n be pre cise ly d eterm ine d. The line i dles i n a sp acing ( log ic " 0") co ndit ion. A
logic "0" is defined as no line activity and a logic "1" is defined as a negative pulse of 100nS duration. A transmission
starts with an ALERT BURST consisting of 6 un it intervals of mark (logic "1"). Eight bit data characters are then sent,
with each character preceded by 2 unit intervals of mark and one unit interval of space. Five types of transmission can
be performed as described below:

Invitations To Transmit
An Invitation To Transmit is used to pass the token from one node to another and is sent by the following sequence:

 An ALERT BURST
 An EOT (End Of Transmission: ASCII code 04H)
 Two (repeated) DID (Destination ID ) ch aracters

ALERT

BURST

Free Buffer Enquiries

A Free Buffer Enquiry is used to ask another node if it is able to accept a packet of data. It is sent by the following
sequence:

 An ALERT BURST
 An ENQ (ENQuiry: ASCII code 85H)
 Two (repeated) DID (Destination ID ) ch aracters

ALERT

BURST

Data Packets
A Data Packet consists of the actual data being sent to another node. It is sent by the following sequence:

 An ALERT BURST
 An SOH (Start Of Header--ASCII code 01H)
 An SID (Source ID) character
 Two (repeated) DID (Destination ID ) ch aracters
 A single COUNT chara cter which is the 2's complement of t he number of data bytes to follo w if a short packet is

sent, or 00H followed by a COUNT character if a long packet is sent.

 N data bytes where COUNT = 256-N (or 512-N for a long packet)

EOT DID DID

ENQ DID DID

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5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

 Two CRC (Cyclic Redundancy Check) charac te rs. The CRC polynomial used is: X16 + X15 + X2 + 1.

Acknowledgements

An Acknowledgement is used to acknowledge reception of a packet or as an affirmative response to FREE BUFFER
ENQUIRIES and is sent by the following sequence:

 An ALERT BURST
 An ACK (ACKnowledgement--ASCII code 86H) charac te r

ALERT BURST ACK

Negative Acknowledgements

A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the
following sequence:

 An ALERT BURST
 A NAK (Negative Acknowledgement--ASCII code 15H) character

ALERT BURST NAK

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6.0 SYSTEM DESCRIPTION

6.1 Microcontroller Interface

The top halves of Fig ur e 2 and Fig ure 3 illustrate typi cal COM20020I in terfaces to t he microcontr ollers. The int erfaces
consist of a 8-bit data bus, an address bus and a control bus. In order to support a wide range of microcontrollers without
requiring glue logic and without increasing the number of pins, the COM20020I automatically detects and adapts to the
type of microcontroller being used. Upon hardware reset, the COM20020I first determines whether the read and write
control signals are separate READ and WRITE signals (like the 80XX) or DIRECTION and DATA STROBE (like the
68XX). To determine the type of control signals, the device requires the software to execute at least one write access to
external memory before attemp ting t o ac cess t h e COM 200 2 0I . The device defaults to 80XX-like signals. Once the type
of control signals are determined, the COM20020I remains in this interface mode until the next hardware reset occurs.
The second determination the COM20020I makes is whether the bus is multiplexed or non-multiplexed. To determine
the type of bus, the device requires the software to write to an odd memory location followed by a read from an odd
location before attempting to access the COM20020I. The signal on the A0 pin during the odd location access tells the
COM20020I the type of bus. Since multiplexed operation requires A0 to be active low, activity on the A0 line tells the
COM20020I that the bus is non-multiplexed. The device defaults to multiplexed operation. Both determinations may be
made simultaneously by performing a WRITE followed by a READ operation to an odd location within the COM20020I
Address space 20020D registers. Once the type of bus is determined, the COM20020I remains in this interface mode
until hardware reset occurs.

Whenever nCS and nRD are activated, the preset determinations are assumed as final and will not be changed until
hardware reset. Refer to DESCRIPTION OF PIN FUNCTIONS FOR TQFP section for details on t h e related signals. All
accesses to the internal RAM and th e in ternal registers are controlled by the COM20020I. The internal RAM is accessed
via a pointer-based scheme (refer to the Sequential Access Memory section), and the internal registe rs are accessed via
direct addressing. Many peripherals are not fast enough to take advantage of high-speed microcontrollers. Since
microcontrollers do not typically have READY inputs, standard peripherals cannot extend cycles to extend the access
time. The access time of the COM20020I, on the other hand, is so fast that it does not need to limit the speed of the
microcontroller. The COM20020I is designed to be flexi ble so that it is independent of the microcontrol ler speed.

The COM20020I provides for no wait state arbit ration via direct address ing to its internal registers an d a pointer based
addressing scheme to access its internal RAM. The pointer may be used in auto-increment mode for typical sequential
buffer emptying or loading, or it can be taken out of auto-increment mode to perform random accesses to the RAM. The
data within the RAM is accessed through the data register. Data being read is prefetched from memory and placed into
the data register for the microc ontroller to read. It is important to notice that only by writing a new address pointer
(writing to an address pointer low), one obtains the contents of COM20020I internal RAM. Performing only read from the
Data Register does not load new data from the internal RAM. During a write operation, th e data is stored in the data
register and then written into memory. Whenever the pointer is loaded for reads with a new value, data is immediately
prefetched to prepare for the first read operation .

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5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

A

A15A

A

A

A

D0-AD2, D3­2/BAL

XTAL1

0/nMU

COM20020I

20 MHz

XTAL

XTAL2

RXIN

nTXEN
nPULSE
nPULSE

GND

27 pF

LTC1480 or
Equiv.

Differential

Configuratio

Media

*

may be

with Figure A, B or

8051

XTAL1

XTAL2

D0-

RESET

nWR

nINT1

LE

nRD

nCS

nRESET

nRD/nD
nWR/DI

nINTR

27 pF

RXIN

TXEN

nPULSE
nPULSE

GND

BACKPLANE

FIGURE A

+3.3V

100

RXIN

nPULSE

NOTE: COM20020 must be in backplane mode

3.3V-5V Converter

FIGURE B

+5V

+5V

2
6

HFD3212-

7

Transmitte

HFE4211-

3

2
6
7

2 Fiber
(ST

Receive

FIGURE 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE

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A

A

X

A

A1A

A

A

XTAL1

XTAL2

6801

D0-D7

nRES

nIOS

R/nW

nIRQ1

0
1
2
7

RXIN

nTXEN

nPULSE1
nPULSE2

GND

3.3V-5V Converter

N/C

D0-D7

nCS
nRESET
nRD/nDS

nWR/nDIR

nINTR

27 pF

HYC9068 or

HYC9088

RXIN

nPULSE1
nPULSE2

17, 19,

4, 13, 14

0.47
uF

FIGURE 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE

0/nMU

2/BALE

FIGURE C

COM2002

XTAL1

20MHz

XTAL

+5V

6

3

+

10

uF

nPULSE1
nPULSE2

XTAL2

+

10
uF

12
11

5.6K

1/2W

5.6K
1/2W

Traditional Hybrid

-5V
*Valid for 2.5 Mbps only.

RXIN

TXEN

GND

Differential Driver

27 pF

0.47
uF

Configuration

LTC1480 or
Equiv.

Configuration

Media Interface

*

may be replaced
with Figure A, B or C.

0.01 uF
1KV

SMSC COM20020I 3.3V Page 17 Revision 12-06-06

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High Speed CPU Bus Timing Support
High speed CPU bus support was added to the COM20020I. The reasoning behind this is as follows: With the Host
interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable before the read signal is
active and remain after the read signal is inactive. But the High Speed CPU bus timing doesn't adhere to these
timings. For example, a RISC type single chip microcontroller (like the HITACHI SuperH series) changes I/O addres s
at the same time as the read signal. Therefore, several external logic ICs would be required to connect to this
microcontroller.

In addition, the Diagnostic Status (DIAG) register is cleared automatically by reading itself . T he internal DIAG register
read signal is generated by decoding the Address (A2-A0), Chip Select (nCS) and Rea d (nRD) signals. T he decoder
will generate a noise spike at the above ti ght timing. The DI AG register is cleared by the spike signal without r eading
itself. This is unexpected operation. Reading the internal RAM an d Next Id Register have the same mechanism as
reading the DIAG register.

Therefore, the address decode and host interface mode blocks were modified to fit the above CPU interface to
support high speed CPU bus timing. In Intel CPU mode (nRD, nWR mode), 3 bit I/O address (A2-A0) and Chi p
Select (nCS) are sampled internally by Flip- Flops on the falling edge of the internal delayed nRD signa l. The internal
real read signal is the more delayed nRD signal. But the rising edge of nRD doesn't delay. By this modification, the
internal real address and Chip Select are stable while the internal real read signal is active. Refer to Figure 4 below.

A2-A0, nCS

nRD

Delayed nRD

(nRD1)

Sampled A2-A0, nCS

More delayed nRD

(nRD2)

VALID

VALID

FIGURE 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE

The I/O address and Chip Select signals, which are supplied to the data output logic, are not sampled. Also, the nRD
signal is not delayed, because the above sampling and delaying paths decrease the data access time of the read
cycle.

The above sampling and delaying signals are supplied to the Read Pulse Generation logic which generates the
clearing pulse for the Diagnostic register and generates the starting pulse of the RAM Arbitration. T ypical delay time
between nRD and nRD1 is around 15nS and between nRD1 and nRD2 is around 10nS.

Longer pulse widths are needed due to these d elays on nRD signal. However, the CP U can insert some wait cycles
to extend the width without any impact on performance.
The RBUSTMG bit was added to Disable/Enable the High Speed CPU Read function. It is defined as: RBUSTMG= 0,
Disabled (Default); RBUSTMG=1, Enabled.

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In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply.

RBUSTMG BIT BUS TIMING MODE

0 Normal Speed CPU Read and Write
1 High Speed CPU Read and Normal Speed CPU Write

6.2 Transmission Media Interface

The bottom halves of Figure 2 and Figure 3 illustrate the COM20020I interface to the transmission medi a used to
connect the node to the network. TABLE 1 - TYPICAL MEDIA lists different types of cable which are suitable for
ARCNET applications. The user may interface to the cable of choice in one of three ways:

Traditional Hybrid Interface
The Traditional Hybrid Interface is that which is used with previous ARCNET devices. The Hybrid Interface is
recommended if the node is to be placed in a network with other Hybrid-Interfaced nodes. The Traditional Hybrid
Interface is for use with nodes operating at 2.5 Mbps only. The transformer co upling of the Hybrid offers isolation for the
safety of the system and offers high Common Mode Rejection. The Traditional Hybrid Interface uses circuits like
SMSC's HYC9068 or HYC9088 to transfer the pulse-encoded data between the cable and the COM20020I. The
COM20020I transmits a logic "1" by generating two 100nS non-overlapping negative pulses, nPULSE1 and nPULSE2.
Lack of pulses indicates a logic "0". T he nPU LSE 1 and nP UL SE2 sig nals ar e sent t o the H ybrid, whic h creat es a 20 0nS
dipulse signal on the media.

A logic "0" is transmitted by the absence of the dipulse. During reception, the 200nS dipulse appearing on the media is
coupled through the RF transformer of the LAN Driver, which produces a positive pulse at the RXIN pin of the
COM20020I. The pulse on the RXIN pin represents a logic "1". Lack of pulse represents a logic "0". Typically, RXIN
pulses occur at multiples of 400nS. The COM20020I can tolerate distortion of plus or minus 100nS and still correctly
capture and convert the R XIN pulses to NRZ format. Figure 5 illustrates th e events which occur in transmission or
reception of data consisting of 1, 1, 0.

Please refer to TN7-5 – Cabling Guidelines for the COM20020I ULANC, available from SMSC, for recommended
cabling distance, termination, and node count for ARCNET nodes.

Backplane Configuration
The Backplane Open Drain Configuration is recommended for cost-sensitive, short-distance applications like backplanes
and instrumentation. This mode is advantageous because it saves components, cost, and power.

Since the Backplane Configurati on encodes data differe ntly than the tradit ional Hybrid Conf iguration, no des utilizing th e
Backplane Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid Configuration. The
Backplane Configuration does not isolate the node from the media nor protects it from Common Mode noise, but
Common Mode Noise is less of a p roblem in short distances.

The COM20020I supplies a programmable output driver for Backplane Mode operation. A push/pull or open drain driver
can be selected by programming the P1MODE bit of the Setup 1 Register (see register descriptions for details). The
COM20020I defaults to an open drain output.

The Backplane Configuration provides for direct connection between the COM20020I and the media. Only one pull-up
resistor (in open drain configuration of the output driver) is required somewhere on the media (not on each individual
node). The nPULSE1 signal, in this mode, is an open drain or push/pull driver and is used to directly drive the media. It
issues a 200nS negative pulse to transmit a logic "1". Note that when used in the open-drain mode, the COM20020I
does not have a fail/safe input on the RXIN pin. The nPULSE1 signal actually contains a weak pull-up resistor. This
pull-up should not take the place of the resistor required on the me dia for open drain mode .

SMSC COM20020I 3.3V Page 19 Revision 12-06-06

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5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

RT RT

+3.3V

LTC1480 or
Equiv.

RBIAS

+3.3V

RBIAS

+3.3V

RBIAS

COM2002

COM2002 COM2002

FIGURE 5 - COM20020I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS

20MHZ
CLOCK
(FOR REF.

ONL Y)
nPULSE1

100ns

nPULSE2

10

100ns

200ns

1

DIPULSE

400ns

RXIN

FIGURE 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0

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