SMC Networks SMC91C95 User Manual
SMC91C95
PRELIMINARY
ISA/PCMCIA Full Duplex Single-Chip
Ethernet and Modem Controller with RAM
FEATURES
• ISA/PCMCIA Single Chip Ethernet Controller
With Modem Support
• 6 Kbytes Built-In RAM
• Supports IEEE 802.3 (ANSI 8802-3) Ethernet
Standards
• Full Duplex Support
• Hardware Memory Management Unit
• Built-In AUI and 10BASE-T Network
Interfaces
• Simultasking - Early Transmit and Early
Receive Functions
• Advanced Power Management
Features/Including Magic Packet Frame
Control
• Software Compatible with SMC91C92/
SMC91C94 (in ISA Mode)
• Configuration Registers Implement Cardbus
Multi-Function Specification V3.0 with
Backward Compatibility to V2.1
• Interfaces Directly to Lucent Technologies and
Rockwell International Modem Chipsets
• On-Chip Attribute Memory (CIS) of up to 512
Bytes (On Even Addresses) For Card
Configuration Information; Expandable
Externally
• Option for Serial or Parallel EEPROM for CIS
Simultasking is a trademark and SMC is a registered trademark of Standard Microsystems Corporation
• Optional External Flash Capability for XIP
(Execute in Place)
• Automatic Technology to Detect TX/RX
10BASE-T Tranceiver Pair Miswiring
• Low Power CMOS Design
• Supports Magic Packet Wakeup
• 128 Pin VTQFP Package
Bus Interface
• Direct Interface to ISA and PCMCIA with
No Wait States
• High Impedance Speaker Interface
• Flexible Bus Interface
• 16-Bit Data and Control Paths
• Fast Access Time (40 ns)
• Pipelined Data Path
• Handles Block Word Transfers for Any
Alignment
• High Performance Chained ("Back-toBack") Transmit and Receive
• Flat Memory Structure for Low CPU
Overhead
• Dynamic Memory Allocation Between
Transmit and Receive
• Buffered Architecture, Insensitive to Bus
Latencies (No Overruns/Underruns)
• Supports Boot PROM for Diskless ISA
Applications
TABLE OF CONTENTS
FEATURES.......................................................................................................................................................1
PIN CONFIGURATION....................................................................................................................................3
GENERAL DESCRIPTION...............................................................................................................................4
OVERVIEW ......................................................................................................................................................4
PIN REQUIREMENTS......................................................................................................................................7
DESCRIPTION OF PIN FUNCTIONS..............................................................................................................9
BUFFER TYPES........................................................................................................................................... 17
FUNCTIONAL DESCRIPTION.......................................................................................................................21
INTERRUPT STRUCTURE............................................................................................................................32
RESET LOGIC.............................................................................................................................................. 33
POWERDOWN LOGIC................................................................................................................................ 34
PCMCIA ATTRIBUTE MEMORY: ADDRESS 0- 7FFEH............................................................................................ 35
PCMCIA CONFIGURATION REGISTERS: ADDRESS 8000-803E H............................................................................. 35
INTERNAL VS EXTERNAL ATTRIBUTE MEMORY MAP.................................................................................................. 36
THEORY OF OPERATION............................................................................................................................69
“MAGIC PACKET” SUPPORT.................................................................................................................................. 70
INTERNAL VS. EXTERNAL ATTRIBUTE MEMORY MAP........................................................................ 80
PCMCIA CONFIGURATION REGISTERS DESCRIPTION....................................................................... 82
FUNCTIONAL DESCRIPTION OF THE BLOCKS...................................................................................... 91
BOARD SETUP INFORMATION............................................................................................................... 100
OPERATIONAL DESCRIPTION..................................................................................................................104
TIMING DIAGRAMS ....................................................................................................................................108
Related Documentation
1. PCMCIA 2.1 Standard (for PCMCIA timing and functionality)
2. PCMCIA 3.X spec (for multi-function extensions)
3. AT&T HSM288xCF Modem Chip Set Data Sheet - July 5, 1994
4. Rockwell RC224ATF and C39 Modem Chip Sets Designer’s Guide
2
Network Interface
NC
AVSS
COLN
COLP
RECN
RECP
TPERXN
TPERXP
AVDD
AVSS
RBIAS
AVDD
nXENDEC
nEN16
PWRDWN/TXCLK
nROM/nPCMCIA
VSS
ENEEP
EESK
EECS
EEDO/SDOUT
EEDI
IOS2
IOS1
VDD
IOS0
XTAL2
XTAL1
WAKEUP
nWAKEUP_EN
RESET
NC
33343536373839404142434445464748495051525354555657585960616263
64
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
999897
NC
A0
A1
VDD
A2A3A4A5A6
A7
VSS
A8
A9
A10
A11
A12
A13
VDD
A14
A15
A16/nFWE
A17/nFCS
A18
A19/nCE1
VSS
D0D1D2
VDD
D3
NC
• Integrates 10BASE-T Transceiver
Functions:
- Driver and Receiver
- Link Integrity Test
- Receive Polarity Detection and
Correction
• Integrates AUI Interface
• Implements 10 Mbps Manchester
Encoding/Decoding and Clock Recovery
• Automatic Retransmission, Bad Packet
Rejection, and Transmit Padding
• External and Internal Loopback Modes
PIN CONFIGURATION
• Four Direct Driven LEDs for Status/
Diagnostics
Software Drivers
• Uses Certified SMC9000 Drivers Which
Operate with Every Major Network
Operating System
• Software Driver Compatible with
SMC91C92, SMC91C94 and SMC91C100
(100 Mbps) Controllers in ISA Mode
• Software Driver Utilizes Full Capability of
32 Bit Microprocessor
AVDD
TXP/nCOLL
TXN/nCRS
TPETXP
TEPTXDP
TPETXN
TPETXDN
AVSS
nTXLED/nTXEN
nRXLED/RXCLK
nLINKLED/TXD
nBSELED/RXD
SPKRIN
SPKROUT
nMIS16
MRDY
MINT
MRINGIN
nMRINGOA
MRINGOB
nMCS
nMRESET
MIDLEN1
nMPWDN
nMPDOUT
MFBK1
VDD
VSS
VDD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
31
ND
32
SMC91C95
128 Pin VTQFP
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
NC
NC
VSS
INTR3
INTR2/nSTSCHG
INTR1/nINPACK
INTR0/nIREQ
VDD
nIORD
nIOWR
nMEMR/nOE
nIOSC16/nIOIS16
VSS
IOCHRDY/nWAIT
BALE/nWE
nSBHE/nCE2
VDD
D15
D14
D13
D12
VSS
D11
D10
D9
VDD
D8
D7
D6
VSS
D5
D4
3
GENERAL DESCRIPTION
The SMC91C95 is a VLSI Ethernet Controller
that combines ISA and PCMCIA interfaces, as
well as an interface to a companion modem
chip set, in one chip. The SMC91C95
integrates all the MAC and physical layer
functions as well as the packet RAM needed to
implement a high performance 10BASE-T
(twisted pair) node. For 10BASE5 (thick coax),
10BASE2 (thin coax), and 10BASE-F (fiber)
implementations, the SMC91C95 interfaces to
external transceivers via its AUI port. Only one
additional IC is required on most applications.
The SMC91C95 occupies 16 I/O locations and
no memory space except for PCMCIA attribute
memory space. The same I/O space is used for
both ISA and PCMCIA operations. The
SMC91C95 can directly interface the ISA and
PCMCIA buses and deliver no wait state
operation. Its shared memory is sequentially
OVERVIEW
A unique architecture allows the SMC91C95 to
combine high performance, flexibility, high
integration and simple software interface.
The SMC91C95 incorporates the SMC91C92/4
functionality for ISA environments with several
new features, as well as a PCMCIA interface
and attribute registers that comply with the
PCMCIA Multi-Function specification. Mode
selection between ISA and PCMCIA is static
and is done only once at the end of power on
reset. The SMC91C95 consists of the same
logical I/O register structure in ISA and
PCMCIA modes. However, some of the signals
used to access the PCMCIA differ from the ISA
mode. Additional registers exist in the PCMCIA
attribute space. The ROM memory space only
exists in ISA mode and the attribute space only
exists in PCMCIA mode.
accessed with 40ns access times to any of its
registers, including its packet memory. No
DMA services are used by the SMC91C95;
virtually decoupling network traffic from local or
system bus utilization. For packet memory
management, the SMC91C95 integrates a
unique hardware Memory Management Unit
(MMU) with enhanced performance and
decreased software overhead when compared
to ring buffer and linked list architectures. The
SMC91C95 is portable to different CPU and bus
platforms due to its flexible bus interface, flat
memory structure (no pointers), and its loosely
coupled buffered architecture (not sensitive to
latency).
The SMC91C95 interfaces directly with
Rockwell International L39/C39 controller-based
modems and Lucent Technologies’
HSM288xCF modem.
I/O decoders are included in the SMC91C95’s
PCMCIA interface, with independent decoders
for the LAN and for the modem functions.
These decoders are used whenever the
SMC91C95 is used as a multi-function card,
and they can be bypassed when only one
function is enabled. The SMC91C95 also
merges the LAN’s internal interrupt source with
the external modem interrupt connected to the
SMC91C95.
The MMU (Memory Management Unit)
architecture used by the SMC91C95 combines
the simplicity and low overhead of fixed areas
with the flexibility of linked lists providing
improved performance over other methods.
The SMC91C95 is designed to support full
duplex switched Ethernet where transmit and
4
receive are fully independent. It has 6 kbytes of
internal memory and the MMU manages
memory in 256 byte pages. The memory size
accommodates the increase in interrupt latency
resulting from simultaneous LAN and modem
operation as well as the potential for
simultaneous transmit and receive traffice in
some full duplex applications.
Packet reception and transmission are
determined by memory availability. All other
resources are always available if memory is
available. To complement this flexible
architecture, all ISA bus interface functions are
incorporated in the SMC91C95, as well as a
4608 byte packet RAM and serial EEPROMbased setup. The user can select or modify
configuration choices.
The SMC91C95 stores the Configuration
Information Structure (CIS) on reset or powerup from the serial EEPROM. This allows the
host to access data to allow the setup of the
PCMCIA multi-function card.
In ISA mode, the serial EEPROM acts as
storage for configuration and IEEE Ethernet
address information compatible with the existing
SMC9000 family of ISA Ethernet controllers.
In PCMCIA mode, the serial EEPROM stores
the CIS, as well as the IEEE address,
information, but it does not store any I/O or IRQ
information since this information is handled by
the host’s socket controller. For CIS
requirements above 512 bytes, an optional
external parallel EEPROM can be used in
conjunction with the internal CIS. This allows
additional external, non-volatile storage for
applications that require XIP and use the
modem function. If the serial EEPROM is not
used in PCMCIA mode, the parallel EEPROM
must be used. In this case, the parallel
EEPROM is selected for the first 512 bytes of
storage as well, allowing the CIS to be stored in
the parallel EEPROM and, on power-up, to be
read directly by the host. The remaining
parallel EEPROM can be used for XIP
applications, if needed.
The SMC91C95 integrates most of the 802.3
functionality, incorporating the MAC layer
protocol, the physical layer encoding and
decoding functions with the ability to handle the
AUI interface. For twisted pair networks, the
SMC91C95 integrates the twisted pair
transceiver as well as the link integrity test
functions.
The SMC91C95 is a true 10BASE-T single chip
able to interface a system or a local bus.
Directly-driven LEDs for installation and runtime diagnostics are provided, as well as 802.3
statistics gathering to facilitate network
management.
The SMC91C95 offers:
High integration:
Single chip adapter including:
Packet RAM
ISA bus interface
PCMCIA interface
EEPROM interface
Encoder decoder with AUI interface
Full duplex, magic packet 10BASE-T
transceiver
Lucent Technologies and Rockwell
International modem interface
High performance:
Chained (“back-to-back”) packet handling
with no CPU intervention:
Queues transmit packets
Queues receive packets
Full duplex operation for higher
network throughput
Stores results in memory along with
packet
Queues Ethernet and modem
interrupts
Optional single interrupt upon
completion of transmit chain
5
Fast block move operation for load/unload:
CPU sees packet bytes as if stored
contiguously
Handles 16 bit transfers regardless of
address alignment
Access to packet through fixed window
Fast bus interface:
Compatible with ISA type and faster buses
Flexibility:
Flexible packet and header processing:
Can be set to Simultasking - Early
Receive and transmit modes
Can access any byte in the packet
Can immediately remove undesired
packets from queue
Can move packets from receive to
transmit queue
Can alter receive processing order
without copying data
Can discard or enqueue again a failed
transmission
Resource allocation:
Memory dynamically allocated for transmit
and receive
Can automatically release memory on
successful transmission
Configuration:
ISA:
Uses non-volatile jumperless setup via
serial EEPROM
PCMCIA:
Uses serial EEPROM for attribute
memory storage. PCMCIA I/O ignores
address lines A4-A15 and relies on the
PCMCIA host, decoding for the slot
nROM/nPCMCIA on the SMC91C95 is left
open with a pullup for ISA mode. This pin
is sampled at the end of Power On Reset.
If found low, the SMC91C95 is configured
for PCMCIA mode.
6
PIN REQUIREMENTS
FUNCTION ISA PCMCIA NUMBER OF
PINS
SYSTEM ADDRESS BUS A0-A15
A16
A17
A18
A19
AEN
SYSTEM DATA BUS D0-D15 D0-D15 16
SYSTEM CONTROL BUS RESET
BALE
nIORD
nIOWR
nMEMR
IOCHRDY
nIOCS16
nSBHE
INTR0
INTR1
INTR2
INTR3
MODEM INTERFACE nMRESET
MINT
nMCS
MRDY
nMPWDN
MIDLEN1
MRINGIN
nMRINGOA
MRINGOB
SPKRIN
SPKROUT
nMPDOUT
MFBK1
nMIS16
SERIAL EEPROM EEDI
EEDO
EECS
EESK
ENEEP
IOS0
IOS1
IOS2
A0-A15
nFWE
nFCS
nCE1
nREG
RESET
nWE
nIORD
nIOWR
nOE
nWAIT
nIOIS16
nCE2
nIREQ
nINPACK
nSTSCHG
nMRESET
MINT
nMCS
MRDY
nMPWDN
MIDLEN1
MRINGIN
nMRINGOA
MRINGOB
SPKRIN
SPKROUT
nMPDOUT
MFBK1
nMIS16
EEDI
EEDO
EECS
EESK
ENEEP
IOS0
IOS1
IOS2
21
12
14
8
7
FUNCTION ISA PCMCIA NUMBER OF
PINS
CRYSTAL OSC. XTAL1
XTAL2
POWER VDD
AVDD
GROUND GND
AGND
10BASE-T INTERFACE TPERXP
TPERXN
TPETXP
TPETXN
TPETXDP
TPETXDN
AUI INTERFACE RECP
RECN
COLP
COLN TXP/nCOLL
TXN/nCRS
LEDs nLNKLED/TXD
nRXLED/RXCLK
nBSELED/RXD
nTXLED/nTXEN
MISC. RBIAS
WAKEUP
nWAKEUPEN
PWRDWN/TXCLK
nXENDEC
nEN16
ROM/nPCMCIA
XTAL1
XTAL2
VDD
AVDD
GND
AGND
TPERXP
TPERXN
TPETXP
TPETXN
TPETXDP
TPETXDN
RECP
RECN
COLP
COLN
TXP/nCOLL
TXN/nCRS
nLNKLED/TXD
nRXLED/RXCLK
nBSELED/RXD
nTXLED/nTXEN
RBIAS
WAKEUP
nWAKEUPEN
PWRDWN/TXCLK
nXENDEC
nEN16
ROM/nPCMCIA
2
12
12
6
6
4
7
TOTAL PINS 120
8
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
113 nROM/
nPCMCIA
35, 36,
38-43,
45-50,
52, 53
54 Address 16 A16 I ISA - Input address line 16.
55 Address 17 A17 I ISA - Input address line 17.
Address 015
nFlash
Memory
Write
nFlash
Memory
Chip Select
A0-A15 I Input address lines 0 through 15.
nFWE O4 PCMCIA - Output. Flash Memory Write
nFCS O4 PCMCIA - Output. Flash Memory Chip Select
I/O4 with
pullup
This pin is sampled at the end of RESET.
When this pin is sampled low the SMC91C95
is configured for PCMCIA operation and all
pin definitions correspond to the PCMCIA
mode. For ISA operation this pin is left open
and is used as a ROM chip select output that
goes active when nMEMR is low and the
address bus contains a valid ROM address.
Enable used for programming the attribute
memory. Goes active (low) when nWE=0 and
WRATTRIB=1 (in ECOR bit 3).
used to access attribute memory. Goes active
(low) when nREG=0, nCE1=0 and A15=0.
56 Address 18 A18 I Input address line 18.
57 Address 19 A19 I with pullup ISA - Input address line 19.
Card Enable
1
34 Address
Enable
nCE1 PCMCIA - Card Enable 1 input. Used to
select card on even byte accesses.
AEN I with pullup ISA - Address enable input. Used as an
address qualifier. Address decoding is only
enabled when AEN is low.
nREG PCMCIA - Attribute memory and IO select
input. Asserted when the card attribute space
or IO space is being accessed.
9
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
81 nByte High
Enable
nCard
Enable 2
83 Ready IOCHRDY OD24 with
nWait nWAIT PCMCIA - Output. Optionally used by the
59, 60,
61, 63,
65, 66,
68-70,
72-74,
76-79
98 Reset RESET IS with
Data Bus D0-D15 I/O24 Bidirectional. 16 bit data bus used to access
nSBHE I with pullup ISA - Byte High Enable input. Asserted (low)
nCE2 PCMCIA - Card Enable 2 input. Used to
pullup
pullup
by the system to indicate a data transfer on
the upper data byte.
select card on odd byte accesses.
ISA - Output. Optionally used by the
SMC91C95 to extend host cycles.
SMC91C95 to extend host cycles.
the SMC91C95 internal registers. The data
bus has weak internal pullups. Supports direct
connection to the system bus without external
buffering.
Input. Active high Reset. This input is not
considered active unless it is active for at least
100ns to filter narrow glitches. A POR circuit
generates an internal reset upon power up for
at least 15msec. All hardware reset
references in this spec relate to the OR
function of the POR and the RESET pin.
82 Address
Latch
nWrite
Enable
90 Interrupt INTR0 O24 ISA - Active high interrupt signal. The interrupt
BALE IS with
pullup
nWE PCMCIA - Write Enable input. Used for
10
ISA - Input. Address strobe. For systems that
require address latching, the falling edge of
BALE latches address lines and nSBHE.
writing into COR and CSR registers as well as
attribute memory space.
line selection is determined by the value of
INT SEL1-0 bits in the Configuration Register.
This interrupt is tri-stated when not selected.
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
nInterrupt
Request
91 Interrupt 1 INTR1 O24 ISA - Output. Active high interrupt signal. The
92 Interrupt 2 INTR2 O24 ISA - Output. Active high interrupt signal. The
nStatus
Changed
nIREQ PCMCIA - Active low interrupt request output.
Pin acts as a Ready pin during power-up. The
pin should be pulled low within 10us of the
application of the VCC or Reset (which ever
occurs later). It remains low(0) until the CIS is
loaded in the Internal SRAM. The high(1)
state indicates to the host controller that the
device is ready.
interrupt line selection is determined by the
value of INT SEL1-0 bits in the Configuration
Register. This interrupt is tri-stated when not
selected.
nINPACK PCMCIA - Output asserted to acknowledge
read cycles for an enabled function.
interrupt line selection is determined by the
value of INT SEL1-0 bits in the Configuration
Register. This interrupt is tri-stated when not
selected.
nSTSCHG PCMCIA - Status changed bit. Depending on
the setting of the RingEn bit (Modem CCSR),
this pin either reflects the ringing status (ExCA
mode) or the state of the Modem Changed bit.
The ringing status is obtained by stretching
the MRINGIN to convert a 20Hz toggle rate to
a constant level.
93 Interrupt 3 INTR3 O24 ISA - Output. Active high interrupt signal. The
interrupt line selection is determined by the
value of INT SEL1-0 bits in the Configuration
Register. This interrupt is tri-stated when not
selected.
85 nI/O 16 nIOCS16 OD24 ISA - Active low output asserted in 16 bit
mode when AEN is low and A4-A15 decode
to the SMC91C95 address programmed into
the high byte of the Base Address Register.
11
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
nIOIS16 PCMCIA - Active low output asserted
whenever the SMC91C95 is in 16 bit mode,
and “Enable Function” bit in the ECOR
register is high, nREG is low and A4-A15
decode to the LAN address specified in I/O
Base Registers 0 and 1 in PCMCIA attribute
space.
88 nI/O Read nIORD IS with
pullup
87 nI/O Write nIOWR IS with
pullup
86 nMemory
Read
nOutput
Enable
24 nModem
Reset
18 Modem
Interrupt
23 nModem
Chip Select
17 Modem
Ready
nMEMR IS with
pullup
nOE PCMCIA - Output Enable input used to read
nMRESET O4 Reset output to Modem. Asserted whenever
MINT I with pull
down
nMCS O4 Chip select output to modem.
MRDY I with pullup Modem ready input. Low indicates the modem
Input. Active low read strobe used to access
the SMC91C95 IO space.
Input. Active low write strobe used to access
the SMC91C95 IO space.
ISA - Active low signal used by the host
processor to read from the external ROM.
from the COR, CSR and attribute memory.
RESET pin is high, internal POR is active, or
SRESET bit is high (MCOR bit 7).
Interrupt input from Modem. Reflected in
INTR (CSR bit 1) and asserts the appropriate
interrupt pin if enabled.
is not ready, either after reset or exiting from
stop or sleep modes.
27 nModem
Powerdown
nMPWDN O4 Powerdown output to modem controller. This
pin is active (low) when either the PWRDWN
bit (CSR bit 2) is set or the modem is disabled
(not configured).
12
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
26 MIDLEN1 O4 Powerdown output to modem controller. This
pin is active (high) when either the PWRDWN
bit (CSR bit 2) is set or the modem is disabled
(not configured).
20 Modem Ring
Input
21 nModem
Ring Output
A
22 Modem Ring
Output B
14 Speaker
Input
15 Speaker
Output
MRINGIN I Ring input from the modem controller.
Toggles when ringing, low when not ringing.
nMRINGOA O4 Ring output signal. When there is no ringing
on the MRINGIN pin and the modem is not in
Powerdown mode this output is high. During
ringing this signal is the inverse of the
MRINGIN input. When the PWRDWN bit is
set or the function is disabled, this output is
low. This signal is activated about 12 msec
after removing Powerdown.
MRINGOB O4 Ring output signal. When the modem is not in
Powerdown mode (PWRDWN bit is zero and
the function is enabled) this output follows the
value of the MRINGIN input. When entering
Powerdown mode, a rising edge is generated
on the pin. A rising edge is also generated
when exiting Powerdown mode also. Refer to
Figure 2.
SPKRIN I with pullup Speaker Input. This is a digitized (single level)
audio input from the modem controller.
SPKROUT O4 tri-stable
with pullup
Speaker Output. This pin reflects the SPKRIN
pin when enabled by the AUDIO bit (Modem
CSR bit 3). When disabled this pin is tri-
stated.
28 nMPDOUT I Schmitt Used to control Powerdown mode. Tie to a
180K pull-up and a 0.1uF cap to ground.
Tie high when not used. This signal is used
in the RC time constant.
29 MFBK1 O4 with
pullup
13
Tie to nMPDOUT through a 5.1M resistor.
This signal is used in the RC time constant
in conjuction with the nMPDOUT pin.
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
16 n16 Bit
Modem
110 EEPROM
Clock
109 EEPROM
Chip Select
108 EEPROM
Data Out
107 EEPROM
Data In
103,
105, 106
9 nTransmit
I/O Base IOS0-IOS2 I with pullup Input. External switches can be connected to
LED
nMIS16 I with pullup Input. When low, it indicates a 16 bit modem,
otherwise the modem is 8 bit wide. Used to
determine if nIOIS16 (PCMCIA) and nIOCS16
(ISA) need to be asserted for modem cycles.
The value of this pin may change from cycle
to cycle.
EESK O4 Output. 4µs clock used to shift data in and out
of the serial EEPROM.
EECS O4 Output. Serial EEPROM chip select.
EEDO/
SDOUT
EEDI I with pull-
nTXLED OD16 Internal ENDEC - Transmit LED output.
O4 Output. Connected to the DI input of the serial
EEPROM.
Input. Connected to the DO output of the
down
serial EEPROM.
these lines to select between predefined
EEPROM configurations. The values of these
pins are readable. These pins are used in ISA
mode only. If in PCMCIA mode, these pins
are not used.
nTransmit
Enable
12 nRoard
Select LED
Receive
Data
nTXEN O162 External ENDEC - Active low Transmit
Enable output.
nBSELED OD16 Internal ENDEC - Board Select LED activated
by accesses to I/O space (nIORD or nIOWR
active with AEN low and valid address decode
for ISA, and with nREG low and and “Enable
Function” bit in the ECOR register is high for
PCMCIA). The pulse is stretched beyond the
access duration to make the LED visible.
RXD I with pullup External ENDEC - NRZ receive data input.
14
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
10 nReceive
LED
Receive
Clock
11 nLink LED nLNKLED OD16 Internal ENDEC - Link LED output.
Transmit
Data
111 Enable
EEPROM
115 nEnable 16
Bit
101
102
Crystal 1
Crystal 2
nRXLED OD16 Internal ENDEC - Receive LED output.
RXCLK I with pullup External ENDEC - Receive clock input.
TXD 0162 External ENDEC - Transmit Data output.
ENEEP I with pullup Input. This active high input enables the
EEPROM to be read or written by the
SMC91C95. Internally pulled up. Must be
connected to ground if no serial EEPROM is
used. In PCMCIA mode, a parallel EEPROM
is required if no serial EEPROM is used.
nEN16 I with pullup Input. When low the SMC91C95 is configured
for 16 bit bus operation. If left open the
SMC91C95 works in 8 bit bus mode. 16 bit
configuration can also be programmed via
serial EEPROM (In ISA Mode only) or via
software initialization of the CONFIGURATION
REGISTER.
XTAL1
XTAL2
Iclk An external parallel resonance 20 MHz crystal
should be connected across these pins. If an
external clock source is used, it should be
connected to XTAL1 and XTAL2 should be
left open.
123
124
2
3
AUI Receive RECP
RECN
AUI
Transmit
TXP/nCOLL
TXN/nCRS
Diff. Input AUI receive differential inputs.
Diff.
Output
I External ENDEC - (nXENDEC pin tied low).
15
Internal ENDEC - (nXENDEC pin open). In
this mode TXP and TXN are the AUI transmit
differential outputs. They must be externally
pulled up using 150 ohm resistors.
In this mode the pins are inputs used for
collision and carrier sense functions.
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
125
126
121
122
4
6
5
7
114 Powerdown PWRDWN I with pullup Internal ENDEC - Powerdown input. It keeps
99 nWakeup
AUI Collision COLP
COLN
TPE Receive TPERXP
TPERXN
TPE
Transmit
TPE
Transmit
Delayed
Transmit
Clock
Enable
TPETXP
TPETXN
TPETXDP
TPETXDN
TXCLK External ENDEC - Transmit clock input from
nWAKEUP-ENI with pullup Input. When pulled down, the device will
Diff. Input AUI collision differential inputs. A collision is
indicated by a 10 MHz signal at this input pair.
Diff. Input 10BASE-T receive differential inputs.
Diff. Output Internal ENDEC - 10BASE-T transmit
differential outputs.
Diff. Output 10BASE-T delayed transmit differential
outputs. Used in combination with TPETXP
and TPETXN to generate the 10BASE-T
transmit pre-distortion.
the SMC91C95 in powerdown mode when
high (open). Must be low for normal operation.
Refer to the Powerdown Matrix following for
further details.
external ENDEC
enable Magic Packet (MP) logic and put the
Ethernet function in powerdown mode. The
pin assertion will override the state of
WAKEUP_EN and PWRDN bits in CTR,
Pwrdwn bit in ECSR, and Enable Function bit
ECOR. When deasserted, the WAKEUP_EN
and PWRDN bits will be changed to (0),
Pwrdwn to (0), and Enable Function to (1).
100 Wakeup WAKEUP O4 Output. Asserted high if nWAKEUP_EN is
asserted and a valid Magic Packet (MP)
pattern is detected. The pin remains asserted
until nWAKEUP_EN is deasserted.
118 Bias
Resistor
RBIAS Analog Input A 22 kohm 1% resistor should be connected
between this pin and analog ground.
16
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
116 nExternal
ENDEC
13, 25,
37, 51,
62, 71,
80, 89,
104
1, 117,
120
19, 30,
44, 58,
67, 75,
84, 94,
112
8, 119,
127
O4 Output buffer with 2mA source and 4mA sink
O162 Output buffer with 2mA source and 16mA sink
O24 Output buffer with 12mA source and 24mA sink
OD16 Open drain buffer with 16mA sink
OD24 Open drain buffer with 24mA sink
I/O24 Bidirectional buffer with 12mA source and 24mA sink
I Input buffer with TTL levels
IS Input buffer with Schmitt Trigger Hysteresis
Iclk Clock input buffer
Power VDD +5V power supply pins
Analog
Power
Ground VSS Ground pins
Analog
Ground
nXENDEC I with pullup When tied low the SMC91C95 is configured
for external ENDEC. When tied high or left
open the SMC91C95 will use its internal
encoder/decoder.
AVDD +5V analog power supply pins
AVSS Analog ground pins
BUFFER TYPES
17
T
P
E
T
X
P
T
P
E
T
X
N
T
P
E
T
X
D
P
T
P
E
T
X
D
N
T
P
E
R
X
P
T
P
E
R
X
N
T
X
P
T
X
N
R
E
C
P
R
E
C
N
C
O
L
P
C
O
L
N
X
T
A
L
1
X
T
A
L
2
E
E
D
I
E
E
C
S
E
E
D
O
E
E
S
K
I
O
S
0
I
O
S
1
I
O
S
2
n
E
N
1
6
E
N
E
E
P
A
E
N
B
A
L
E
R
E
S
E
T
n
S
B
H
E
n
I
O
R
D
,
n
I
O
W
R
,
n
M
E
M
R
D
0
-
1
5
A
0
-
1
9
n
R
O
M
n
I
O
C
S
1
6
I
O
C
H
R
D
Y
I
N
T
R
0
-
3
4
D
I
A
G
N
O
S
T
I
C
L
E
D
s
SERIAL
E
E
P
R
O
M
4
2
0
M
H
z
3
S
Y
S
T
E
M
B
U
S
A
D
D
R
E
S
S
P
R
O
M
D
A
T
A
n
I
R
Q
4
N
/
C
R
B
I
A
S
B
U
F
F
E
R
SMC91C95
CABLE SIDE
10BASET AUI
Figure 1 - SMC91C95 System Block Diagram for ISA Bus with Boot PROM
18
PCMCIA CONNECTOR
nOE
D0-D7
A0-X
nCE1 nCE2 nREG nWE
A0-A9, A15
nIORD nIOWR
STSCHG
RESET
nIREQ
D0-D15
nIOIS16 nINPACK
nWAIT
nOE
nFWE
nFCS
nCEnWE
EXTENDED
ATTRIBUTE
EPROM
2816
(Optional)
SMC91C95
CS,SK,DI,DO
SERIAL EPROM
(ISA-Hy9346)
(PCMCIA-Hy93c66)
SPKROUT
nMRESET
MINT
nMCS
MRDY
MPWDN
MRINGIN
MRINGOB
SPKRIN
nRESET
INT
nCS
RDY
PWDN
RINGIN
RINGOUTB
SPKR
10BASE-T/AUI
INTERFACE
PHONE LINE
MODEM
CHIPSET
Figure 2 - SMC91C95 System Block Diagram for Dual Function PCMCIA Card
19
MODEM
TRANSCEIVER
DATA
BUS
ADDRESS
BUS
CONTROL
BUS
INTERFACE
ARBITER
CSMA/CD
ENDEC
AUI
MMU
10BASE-T
RAM
INTERFACE
MANAGEMENT
Figure 3 - SMC91C95 Internal Block Diagram
TWISTED PAIR
20
FUNCTIONAL DESCRIPTION
The SMC91C95 consists of an integrated Ethernet
controller mapped entirely in I/O space, as well as
support for an external Modem controller also
mapped in I/O space. In addition, PCMCIA
attribute memory space is decoded to interface an
external CIS ROM, with configuration registers as
per PCMCIA 3.X extensions implemented on-chip
in attribute space above the CIS ROM decode
area. The PCMCIA Configuration Registers are
accessible also in I/O space to allow non-PCMCIA
dual function designs.
Table 1 - Bus Transactions in ISA Mode
A0 nSBHE D0-D7 D8-D15
8 BIT MODE
(nEN16=1)
(16 BIT=0) 1 X odd byte 16 BIT MODE 0 0 even byte odd byte
otherwise 0 1 even byte -
0 X even byte -
1 0 - odd byte
1 1 invalid cycle
The Ethernet controller function includes a built-in
6kbyte RAM for packet storage. This RAM buffer
is accessed by the CPU through two sequential
access regions of 3 kbytes each. The RAM access
is internally arbitrated by the SMC91C95 and
dynamically allocated between transmit and
receive packets using 256 byte pages. The
Ethernet controller functionality is identical to the
SMC91C94 except where indicated otherwise.
21
Table 2 - Bus Transactions in PCMCIA Mode
A0 nCE1 nCE2 D0-D7 D8-D15
8 BIT MODE
((IOis8=1) + (nEN16=1).(16BIT=0))
16 BIT MODE 0 0 0 even byte odd byte
otherwise 0 0 1 even byte -
16BIT = CONFIGURATION REGISTER bit 7
IOis8 = ECSR register bit 5
nEN16 = pin nEN16
For the modem function, the transactions are similarxcept that the modem is assumed to be 8 bit wide
unless (IOis8=0) and (nMIS16=0).
NOTE: The IOis8 value should be identical in MCSR and ECSR if both functions are enabled.
8 Bit mode = (IOis8=1)+(nMIS16=1)
0 0 X even byte -
1 0 X odd byte X 1 X NO CYCLE
1 0 1 odd byte
X 1 0 - odd byte
X 1 1 NO CYCLE
22
Table 3 - SMC91C95 Address Spaces
SIGNALS
ISA PCMCIAON-CHIP DEPTH WIDTH
USED
PCMCIA
Attribute
Memory
nOE nWE N Y N
(external
ROM)
Up to 32k
locations, only
even bytes are
8 bits on even
addresses
usable
PCMCIA
Configuration
Registers
Modem I/O
nOE nWE N Y Y 64 locations, only
8 bits
even bytes are
usable
nIORD nIOWR Y Y N 8 locations 8 bit
Space
Ethernet I/O
nIORD nIOWR Y Y Y 16 locations 8 or 16 bits
Space (1)
(1) This space also allows access to the PCMCIA Configuration Register through Banks 4 and 5
(SMC91C95 only).
Except for the bus interface, the functional
behavior of the SMC91C95 after initial
configuration is identical for ISA and PCMCIA
In the system memory space, up to 64 kbytes are
decoded by the SMC91C95 as expansion ROM.
The ROM expansion area is 8 bits wide.
modes.
Device configuration is done using a serial
The SMC91C95 includes an arbitrated shared
memory of 6 kbytes accessed by the CPU. The
MMU unit allocates RAM memory to be used for
EEPROM, with support for modifications to the
EEPROM at installation time. A Flash ROM is
supported for PCMCIA attribute memory.
transmit and receive packets, using 256 byte
pages.
The CSMA/CD core implements the 802.3 MAC
layer protocol. It has two independent interfaces,
The arbitration is transparent to the CPU in every
sense. There is no speed penalty for ISA type of
the data path and the control path. Both interfaces
are 16 bits wide.
machines due to arbitration. There are no
restrictions on what locations can be accessed at
any time. RAM accesses as well as MMU
requests are arbitrated.
The control path provides a set of registers used to
configure and control the block. These registers
are accessible by the CPU through the
SMC91C95’s I/O space. The data path is of
The RAM is accessed by mapping it into I/O space
for sequential access. Except for the RAM
accesses and the MMU request/release
commands, I/O accesses are not arbitrated.
sequential access nature and typically works in
one direction at any given time. An internal DMA
type of interface connects the data path to the
device RAM through the arbiter and MMU.
The I/O space is 16 bits wide. Provisions for 8 bit
systems are handled by the bus interface.
The CSMA/CD data path interface is not
accessible to the host CPU.
23
The internal DMA interface can arbitrate for RAM
access and request memory from the MMU when
necessary.
An encoder/decoder block interfaces the
CSMA/CD block on the serial side. The encoder
will do the Manchester encoding of the transmit
data at 10 Mbps, while the decoder will recover the
receive clock and decode received data.
Carrier and Collision detection signals are also
handled by this block and relayed to the CSMA/CD
block.
The encoder/decoder block can interface the
network through the AUI interface pairs or it can be
programmed to use the internal 10BASE-T
transceiver and connect to a twisted pair network.
The TX area is seen by the CPU as a window
through which packets can be loaded into memory
before queuing them in the TX FIFO of packets.
The TX area can also be used to examine the
transmit completion status after packet
transmission.
The RX area is associated to the output of the RX
FIFO of packets, and is used to access receive
packet data and status information.
The logical address is specified by loading the
address pointer register. The pointer can
automatically increment on accesses.
All accesses to the RAM are done via I/O space.
A bit in the address pointer also specifies if the
address refers to the TX or RX area.
The twisted pair interface takes care of the
medium dependent signaling for 10BASE-T type of
networks. It is responsible for line interface (with
external pulse transformers and pre-distortion
resistors), collision detection as well as the link
integrity test function.
The SMC91C95 provides a 16-bit data path into
RAM. The RAM is private and can only be
accessed by the system via the arbiter. RAM
memory is managed by the MMU. Byte and word
accesses to the RAM are supported.
If the system to SRAM bandwidth is insufficient,
the SMC91C95 will automatically use its
IOCHRDY line for flow control. However, for ISA
buses, IOCHRDY will never be negated.
BUFFER MEMORY
The logical addresses for RAM access are divided
into TX area and RX area. Each one of the areas
is 1.536 kbytes long and accommodates one
maximum size Ethernet packet.
In the TX area, the host CPU has access to the
next transmit packet being prepared for
transmission. In the RX area, it has access to the
first receive packet not processed by the CPU yet.
The FIFO of packets, existing beneath the TX and
RX areas, is managed by the MMU. The MMU
dynamically allocates and releases memory to be
used by the transmit and receive functions.
The MMU related parameters for the SMC91C95
are:
RAM size 6 kbytes (internal)
Max. number of packets 24
Max. pages per packet 6
Max. number of pages 24
Page size 256 bytes
24
RCV
BIT
RCV VS. TX
AREA
SELECTION
POINTER
REGISTER
11-BIT
LOGICAL
ADDRESS
2K TX
AREA
PHYSICAL
MEMORY
TX PACKET
NUMBER
PAGE =
256 bytes
MMU
RX PACKET
NUMBER
2K RX
AREA
MMU
FIGURE 4 - MAPPING AND PAGING VS. RECEIVE AND TX AREA
25
PACKET NUMBER
LINEAR ADDRESS MMU MAPPING
REGISTER
CPU
SIDE
TX FIFO
PACKET #A
STATUS
COUNT
DATA
STATUS
COUNT
MEMORY
B
A
TX COMPLETION
FIFO
FIFO PORTS
REGISTER
PACKET #B
TO
CSMA
PACKET #C
DATA
STATUS
COUNT
DATA
FIGURE 5 - TRANSMIT QUEUES AND MAPPING
C
B
C
26
FIFO PORTS
LINEAR ADDRESS MMU MAPPING
REGISTER
STATUS
COUNT
MEMORY
D
CPU
SIDE
RX FIFO
PACKET #D
PACKET #E
FROM
CSMA
FIGURE 6 - RECEIVE QUEUE AND MAPPING
DATA
STATUS
COUNT
DATA
E
D
E
27
BUS INTERFACE
ARBITER
MMU
BUFFER RAM
CSMA/CD
ENDEC
TWISTED PAIR
TRANSCEIVER
AUI
10BASET
DATA BUS
ADDRESS
BUS
CONTROL
EEPROM
EEPROM
WRITE
DATA
REG.
READ
DATA
REG.
TX
FIFO
TX
COMPL
FIFO
RX
FIFO
DMA
INTERFACE
ADDRESSDATA
FIGURE 7 - SMC91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATH
28
PACKET FORMAT IN BUFFER MEMORY
LAST DATA BYTE (if odd)
CONTROL BYTE
The packet format in memory is similar for the
TRANSMIT and RECEIVE areas. The first
word is reserved for the status word, the next
bit15
RAM
OFFSET
(DECIMAL)
word is used to specify the total number of
bytes, and that in turn is followed by the data
area. The data area holds the packet itself, and
its length is determined by the byte count. The
packet memory format is word oriented.
bit0
0
2
RESERVED
STATUS WORD
4
1536 Max
FIGURE 8 - DATA PACKET FORMAT
TRANSMIT PACKET RECEIVE PACKET
STATUS WORD Written by CSMA upon transmit
completion (see Status
Register).
BYTE COUNT Written by CPU. Written by CSMA.
DATA AREA Written by CPU. Written by CSMA.
CONTROL BYTE Written by CPU to control
ODD/EVEN data bytes.
BYTE COUNT (always even)
DATA AREA
Written by CSMA upon receive
completion (see RX Frame
Status Word).
Written by CSMA. Also has
ODD/EVEN bit.
29
BYTE COUNT - Divided by two, it defines the
total number of words including the STATUS
WORD, the BYTE COUNT WORD, the DATA
AREA and the CONTROL BYTE.
The receive byte count always appears as even;
the ODDFRM bit of the receive status word
indicates if the low byte of the last word is relevant.
The data area contains six bytes of DESTINATION
ADDRESS followed by six bytes of SOURCE
ADDRESS, followed by a variable-length number
of bytes. On transmit, all bytes are provided by the
CPU, including the source address. The
SMC91C95 does not insert its own source
address. On receive, all bytes are provided by the
CSMA side.
The transmit byte count least significant bit will be
assumed 0 by the controller regardless of the value
written in memory.
The 802.3 Frame Length word (Frame Type in
Ethernet) is not interpreted by the SMC91C95. It is
treated transparently as data both for transmit and
receive operations.
DATA AREA - The data area starts at offset 4 of
the packet structure and can extend up to 1536
bytes.
CONTROL BYTE - The CONTROL BYTE
always resides on the high byte of the last word.
For transmit packets the CONTROL BYTE is
written by the CPU as:
X X ODD CRC 0 0 0 0
ODD - If set, indicates an odd number of bytes,
with the last byte being right before the CONTROL
BYTE. If clear, the number of data bytes is even
CRC - When set, CRC will be appended to the
frame. This bit has only meaning if the NOCRC bit
in the TCR is set.
and the byte before the CONTROL BYTE is not
transmitted.
For receive packets the CONTROL BYTE is
written by the controller as:
0 1 ODD 0 0 0 0 0
ODD - If set, indicates an odd number of bytes,
with the last byte being right before the CONTROL
and the byte before the CONTROL BYTE should
be ignored.
BYTE. If clear, the number of data bytes is even
30
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