SMC Networks ARM720T-LH79520 User Manual
ARM720T_LH79520 – Sharp LH79520 SoC
Summary
Core Reference
CR0162 (v2.0) March 10, 2008
Altium Designer's ARM720T_LH79520 component is a 32-bit Wishbone-co mpatible RISC
processor.
Although placed in an Altium Designer-based FPGA project just like any other 32-bit
processor component, the ARM720T_LH79520 is essentially a Wishbone-c ompliant wrapper
that allows communication with, and use of, the discrete ARM720T processor encapsulated
within the Sharp Bluestreak LH79520 device. You can think of the wrapper as being the
'means' by which to facilitate use of external memory and peripheral devices – defined within an FPGA – with the discrete
processor.
The ARM720T_LH79520 wrapper can be used in FPGA designs targetin g any physical FPGA device – you are not constrained
to a particular vendor or platform.
with ARM720T 32-bit RISC Processor
This document provides information on Altium Designer's Wishbone wrapper support
for the discrete Sharp Bluestreak® LH79520 – a fully integrated 32-bit System-onChip (SoC), based on an ARM720T 32-bit RISC processor core.
The ARM720T macrocell within the
physical LH79520 is built around an
ARM7TDMI-S core processor. This
processor is an implementation of the
ARM architecture v4T.
Features
• 3-stage pipelined RISC processor
• 4GByte address space
• 32-bit ARM instruction set
• Wishbone I/O and memory ports for simplified peripheral connection
• Full Viper-based software development tool chain – C compiler/assembler/source-level
debugger/profiler
• C-code compatible with other Altium Designer 8-bit and 32-bit Wishbone-compliant
processors, for easy design migration.
For further information on ARM720T features, refer to the following documents, available from
www.arm.com:
•
ARM720T Technical Reference Manual
ARM7TDMI-S Technical Reference Manual
•
For further information on LH79520 features, refer to the following documents, available from
•
LH79520 Product Brief
LH79520 Data Sheet
•
LH79520 System-on-Chip User's Guide
•
Code written for the ARM720T is
binary-compatible with other members
of the ARM7 family of processors. It is
also forward-compatible with ARM9,
ARM9E, and ARM10 processor
families.
www.sharpsma.com:
Available Devices
From a schematic document, the ARM720T_LH79520 device can be found in the FP GA Processors integrated library (FPGA
Processors.IntLib
From an OpenBus System document, the ARM720T_LH79520 component can be found in the
the
OpenBus Palette panel.
CR0162 (v2.0) March 10, 2008 1
), located in the \Library\Fpga folder of the installation.
Processor Wrappers region of
ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Proces sor
RISC Processor Background
RISC, or Reduced Instruction Set Computer, is a term that is conventionally used to describe a type of microprocessor
architecture that employs a small but highly-optimized set of instructions, rather than the large set of more specialized
instructions often found in other types of architectures. This other type of processor is traditionally referred to as CISC, or
Complex Instruction Set Computer.
History
The early RISC processors came from research projects at Stanford a nd Berkel ey unive rsities in th e l ate 1970s a nd earl y 1 980s.
These processors were designed with a similar philosophy, which has become known as RISC. The basi c design architecture of
all RISC processors has generally followed the characteristics that came from these early research projects and which can be
summarized as follows:
•
One instruction per clock cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is
due to the optimization of each instruction on the CPU and a technique called pipelining. This technique allows each
instruction to be processed in a set number of stages. This in turn allows for the simultaneous execution of a number of
different instructions, each instruction being at a different stage in the pipeline.
•
Load/Store machine with a large number of internal registers: The RISC design philosop hy typically uses a large
number (commonly 32) of registers. Most instructions operate on these registers, with access to memory made using a very
limited set of Load and Store instructions. This limits the need for continuous access to slow memory for loading and storing
data.
•
Separate Data Memory and Instruction Memory access paths: Different stages of the pipeline perform simultaneou s
accesses to memory. This Harvard style of architecture can either be used with two completely different memory spaces, a
single dual-port memory space or, more commonly, a single memory space with separate data and instruction caches for
the two pipeline stages.
Over the last 20-25 years, RISC processors have been steadily improved and optimized. In one sense, the origin al simplicity of
the RISC architecture has been lost – replaced by super-scalar, multiple-pipelined hardware, often running in the giga hertz
range.
“Soft” FPGA Processors
With the advent of low-cost, high-capacity programmable logic devices, there has been something of a resurgence in the use of
processors with simple RISC architectures. Register-rich FPGAs, with their synchronous design requirements, have found the
ideal match when paired with these simple pipelined processors.
As a result, most 32-bit FPGA soft processors are adopting this approach. They could even be considered as “Retroprocessors”.
Why use “Soft” Processors?
There are a number of benefits to be gained from using soft processors on reconfigurable hardware. The following sections
explore some of the more significant of these benefits in more detail.
Field Reconfigurable Hardware
For certain specific applications, the ability to change the design once it is in the field can be a significant competitive advantage.
Applications in general can benefit from this ability also. It allows commitment to shipping early in the development cycle. It also
allows field testing to be used to help drive the latter part of the design cycle without requiring new “board-spins” based on the
outcome. This is very similar to the way in which alpha, beta, pre-release and release cycles currently drive the closure of
software products.
The ability to update embedded software in a device in the field has long b een an advantage enjoyed by designers of
embedded systems. With FPGAs, this has now become a reality for the hardware side of the design. For end-users, this
translates as “Field Upgradeable Hardware”.
Faster Time to Market
FPGAs offer the fastest time to market due to their programmable nature. Design problems, or feature changes, can be made
quickly and simply by changing the FPGA design – with no changes in the board-level design.
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Proces sor
Improving and Extending Product Life-Cycles
Fast time to market is usually synonymous with a weaker feature set – a traditional trade-off. With FPGA-based system designs
you can have the best of both worlds. You can get your product to market quickly with a limited feature set, then follow-up with
more extensive features over time, upgrading the product while it is already in the field.
This not only extends product life-cycles but also lowers the risk of entry, allowing new protocols to be added dynamically and
hardware bugs to be fixed without product RMA.
Creating Application-Specific Coprocessors
Algorithms can easily be moved between hardware and software implementations. This allows the design to be initially
implemented in software, later off-loading intensive tasks into dedicated hardware, in order to meet performance objec tives.
Again, this can happen even after commitment to the board-level design.
Implementing Multiple Processors within a Single Device
Extra processors can be added within a single FPGA device, simply by modifying the desi gn with which the device is
programmed. Once again, this can be achieved after the board-level design has been finalized and a commitment to production
made.
Lowering System Cost
Processors, peripherals, memory and I/O interfaces can be integrated into a single FPGA device, greatly reducing system
complexity and cost. Once the FPGA-based embedded application moves to 32-bit, cost becom es an ev en more p o werful driver.
As large FPGAs become cheaper, both Hybrids and soft cores move into the same general cost area as dedicated processors.
At the heart of this argument is also the idea that once you have paid for the FPGA, any extra IP that you place in the device is
free functionality.
Avoiding Processor Obsolescence
As products mature, processor supply may become an increasing problem, particularly where the processor is one of many
variants supplied by the semiconductor vendor. Switching to a new processor usually requires design software changes or
logical hardware changes.
With FPGA implementations, the design can be easily moved to a different device with little or no change to the hardware logic
and probably no change to the application software. Peripherals ar e created dynamically in the hardware, so lack of availability
of specific processor variants is never a problem.
The ARM720T_LH79520
Altium Designer's support for the Sharp Bluestreak LH79520 offers you the best of both worlds – allowing you to create designs
that themselves reside within an FPGA device, whilst incorporating the processing power of the ARM720T within the physic al
LH79520 device. Your design may simply provide an extensi on of the ARM720T to external memory and peripheral devices, the
interfacing to which is specified in the design downloaded to the FPGA. Alternatively, you may have a hybrid design, making
use not only of a physical processor (and member of the widely regarded ARM7 family), but also one or more 'soft' processors
defined within your FPGA design and resident on the target FPGA device. Performance critical code might typically be handled
by the physical processor.
The ARM720T is a 32-bit RISC machine that follows the classic RISC architecture previously described. It is a load/store
machine with 31 general purpose registers and 6 status registers.
All instructions are 32-bits wide and most execute in a single clock cycle.
The ARM720T_LH79520 also features a user-definable amount of zero- wait state block RAM, with true dual-port access.
Wishbone Bus Interfaces
The ARM720T_LH79520 uses the Wishbone bus standard. T his standard is formally described
as a “System-on-Chip Interconnection Architecture for Portable IP Cores”. The current standard
is the
Revision B.3 Specification, a copy of which is included as part of the software installation
and can be found by navigating to the Documentation Library » Designing with
FPGAs
The Wishbone standard is not copyrighted and resides in the public domain. It may be freely
copied and distributed by any means. Furthermore, it may be used for the design and productio n
of integrated circuit components without royalties or other financial obligations.
section of the Knowledge Center panel.
Remember that the
ARM720T_LH79520 is the
'Wishbone wrapper' placed in your
FPGA design. The actual
ARM720T resides in the physical
LH79520 device – external to the
FPGA device to which that design
is targeted.
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Proces sor
Wishbone OpenBUS Processor Wrappers
To normalize access to hardware and peripherals, each of the 32-bit processors supporte d in Altium Designer has a Wishbone
OpenBUS-based FPGA core that 'wraps' around the processor. This enables peripherals defined in the FPGA to be used
transparently with any type of processor. An FPGA OpenBUS wrapper around discret e, hard-wired peripherals also allows them
to be moved seamlessly between processors.
The OpenBUS wrappers can be implemented in any FPGA and allow the designer to implement FPGA-based portable cores,
taking advantage of the device driver system in Altium Designer for both FPGA-based soft-core peripherals as well as
connections to off-chip discrete peripherals and memory devices.
Processor Abstraction System
Use of OpenBUS wrappers creates a plug-in processor abstraction system that normalizes the interface to interrupt systems
and other hardware specific elements. The system provides an identical interface to the processor's interrupt system, whether
soft or hard-vectored. This allows different processors to be used transparently with identical source code bases.
Design Migration
With each 32-bit processor encased in a Wishbone OpenBUS wrapper, an embedded software design can be seamlessly
moved between soft-core processors, hybrid hard-core processors and discrete processors.
The Wishbone OpenBUS wrapper around the ARM720T_LH79520 processor makes it architecturally similar to the other 32-bit
processors included with Altium Designer, both in terms of its memory map and its pinout. This allows for easy migration from
the ARM720T_LH79520 to any of the following devices:
•
TSK3000A – 32-bit RISC processor, device and vendor-independent. (Refer to the TSK3000A 32-bit RISC Processor core
reference).
PPC405A – 'hard' PowerPC® 32-bit RISC processor immersed on the Xilinx Virtex-II Pro. (Refer to the PPC405A 32-bit
•
RISC Processor
MicroBlaze™ – 32-bit RISC processor targeted to Xilinx FPGA platforms. (Refer to the MicroBlaze 32-bit RISC Processor
•
core reference).
• Nios® II – 32-bit RISC processor targeted to Altera FPGA platforms. (Refer to the Nios II 32-bit RISC Processor core
reference).
•
CoreMP7 – 32-bit RISC processor targeted to Actel FPGA platforms.
•
PPC405CR – AMCC® PowerPC 32-bit RISC processor. (Refer to the PPC405CR - AMCC PowerPC 32-bit RISC Processor
core reference).
Altium Designer also features Wishbone-compliant versions of its TSK52x 8-bit processor. These Wishbone variants, along with
true C-code compatibility between these and the ARM720T_LH79520, allow designs to be easily moved between the 8- and 32bit worlds.
For further information on the TSK52x, refer to the
core reference).
TSK52x MCU core reference.
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Proces sor
Architectural Overview
Symbol
Figure 1. Symbols used for the ARM720T_LH79520 in both schematic (left) and OpenBus System (right).
As can be seen from the schematic symbol in Figure 1, the ARM720T_LH79520 wrapper that is placed in an FPGA design
essentially has three interfaces. The Wishbone External Memory and Peripheral I/O interfaces are identical to those of all other
32-bit processors supported by Altium Designer.
The third interface provides connection to the physical LH79520 itself. More specifically, it caters for:
• Data and Address bus signals to/from the LH79520's External Bus Interface (EBI)
• Control signals from the LH79520's Static Memory Controller (SMC)
• Clock, Reset and Interrupt signals.
The corresponding signals from the physical LH79520 must be hardwired to the desired p ins of the ph ysical FPGA device. To
wire from the ARM720T_LH79520 Wishbone wrapper to the physical pins of the FPGA device requires the use of the relevant
port-plugin component (
ARM720T_LH79520 in an FPGA design
CR0162 (v2.0) March 10, 2008 5
PROCESSOR_ARM7_LH79520). For more information, refer to the section Placing an
.
ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Proces sor
Pin Description
The following pin description is for the processor when used on the schematic. In an OpenBus System, although the same
signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The interface signals to the
physical processor will be made available as sheet entries, associated with the parent sheet symbol used to reference the
underlying OpenBus System.
Table 1. ARM720T_LH79520 pin description
Name Type Polarity/Bus size Description
Control Signals
CLK_I
RST_I
INT_I
ME_STB_O
ME_CYC_O
ME_ACK_I
ME_ADR_O
ME_DAT_I
ME_DAT_O
ME_SEL_O
ME_WE_O
ME_CLK_O
ME_RST_O
I Rise
I High
I 32
External Memory Interface Signals
O High
O High
I High
O 32
I 32
O 32
O 4
O Level Write enable signal. Used to indicate whether the current local bus
O Rise
O High
External (system) clock. This signal is internally wired to the
ARM7_SYS_CLK output.
External (system) reset. This signal is internally wired to the
ARM7_SYS_RESET output
Interrupt Signals
Interrupt lines. The least significant 5 lines are routed through to the
physical device on the PER_INT bus (see
Strobe signal. When asserted, indicates the start of a valid Wishbone
data transfer cycle
Cycle signal. When asserted, indicates the start of a valid Wishbone
bus cycle. This signal remains asserted until the end of the bus
cycle, where such a cycle can include multiple data transfers
Standard Wishbone device acknowledgement signal. When this
signal goes High, an external Wishbone slave memory device has
finished execution of the requested action and the current bus cycle
is terminated
Standard Wishbone address bus, used to select an address in a
connected Wishbone slave memory device for writing to/reading
from
Data received from an external Wishbone slave memory device
Data to be sent to an external Wishbone slave memory device
Select output, used to determine where data is placed on the
ME_DAT_O line during a Write cycle and from where on the
ME_DAT_I line data is accessed during a Read cycle. Each of the
data ports is 32-bits wide with 8-bit granularity, meaning data
transfers can be 8-, 16- or 32-bit. The four select bits allow targeting
of each of the four active bytes of a port, with bit 0 corresponding to
the low byte (7..0) and bit 3 corresponding to the high byte (31..24)
cycle is a Read or Write cycle.
0 = Read
1 = Write
External (system) clock signal (identical to CLK_I), made available
for connecting to the CLK_I input of a slave memory device. Though
not part of the standard Wishbone interface, this signal is provided
for convenience when wiring your design
Reset signal made available for connection to the RST_I input of a
slave memory device. This signal goes High when an external reset
is issued to the processor on its RST_I pin. When this signal goes
Low, the reset cycle has completed and the processor is active
again. Though not part of the standard Wishbone interface, this
signal is provided for convenience when wiring your design
Interrupts).
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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Proces sor
Name Type Polarity/Bus size Description
Peripheral I/O Interface Signals
IO_STB_O
IO_CYC_O
O High
O High
Strobe signal. When asserted, indicates the start of a valid Wishbone
data transfer cycle
Cycle signal. When asserted, indicates the start of a valid Wishbone
bus cycle. This signal remains asserted until the end of the bus
cycle, where such a cycle can include multiple data transfers
IO_ACK_I
I High
Standard Wishbone device acknowledgement signal. When this
signal goes High, an external Wishbone slave peripheral device has
finished execution of the requested action and the current bus cycle
is terminated
IO_ADR_O
O 24
Standard Wishbone address bus, used to select an internal register
of a connected Wishbone slave peripheral device for writing
to/reading from
IO_DAT_I
IO_DAT_O
IO_SEL_O
I 32
O 32
O 4
Data received from an external Wishbone slave peripheral device
Data to be sent to an external Wishbone slave peripheral device
Select output, used to determine where data is placed on the
IO_DAT_O line during a Write cycle and from where on the
IO_DAT_I line data is accessed during a Read cycle. Each of the
data ports is 32-bits wide with 8-bit granularity, meaning data
transfers can be 8-, 16- or 32-bit. The four select bits allow targeting
of each of the four active bytes of a port, with bit 0 corresponding to
the low byte (7..0) and bit 3 corresponding to the high byte (31..24)
IO_WE_O
O Level Write enable signal. Used to indicate whether the current local bus
cycle is a Read or Write cycle.
0 = Read
1 = Write
IO_CLK_O
O Rise
External (system) clock signal (identical to CLK_I), made available
for connecting to the CLK_I input of a slave peripheral device.
Though not part of the standard Wishbone interface, this signal is
provided for convenience when wiring your design
IO_RST_O
O High
Reset signal made available for connection to the RST_I input of a
slave peripheral device. This signal goes High when an external
reset is issued to the processor on its RST_I pin. When this signal
goes Low, the reset cycle has completed and the processor is active
again. Though not part of the standard Wishbone interface, this
signal is provided for convenience when wiring your design
Physical LH79520 Interface Signals
PER_DATA
PER_ADDR
PER_WEB
IO 32
I 26
I 4/Low
Data Bus
Address Bus
Static Memory Controller Byte Lane Enable/Byte Write Enable.
These 4 control bits are used to configure the width of the data
transfer between the LH79520'S Static Memory Controller and the
external memory/peripheral. Data transfers can be 8-, 16- or 32-bit.
The four select bits allow targeting of each of the four active byte
lanes, with bit 0 corresponding to the low byte (7..0) and bit 3
corresponding to the high byte (31..24)
PER_WE
I Low
Static Memory Controller Write Enable. Used to control whether
external memory/peripheral is being read or written.
0 = Write
1 = Read
PER_CS
PER_OE
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I 6/Low
I Low
Static Memory Controller Chip Select. These 6 bits are used to
enable six independently configurable banks of external memory.
Static Memory Controller Output Enable
ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Proces sor
Name Type Polarity/Bus size Description
PER_RESET
ARM7_SYS_RESE
T
PER_CLK
ARM7_SYS_CLK
PER_READY
PER_INT
I Low
O Low
I Rise
O Rise
O Low
O 5/High
Reset signal from the LH79520.
Reset signal to the LH79520 (internally connected from the RST_I
line).
Clock signal from the LH79520
External Clock signal to the LH79520 (internally connected from the
CLK_I line).
Static Memory Controller External Wait Control
External Interrupt lines. These lines appear as interrupts 0 to 4 when
handled by the physical device's Vectored Interrupt Controller (see
Interrupts).
Configuring the Processor
The architecture of the ARM720T_LH79520 can be configured after placement on the schematic sheet, or OpenBus System
document, using the
you are working:
•
In the Schematic document – simply right-click over the device and choose the command to configure the processor from
the context menu that appears. Alternatively, click on the Configure button, available in the
the device.
•
In the OpenBus System document – access the dialog by right-clicking over the component and choosing the command to
configure the processor from the menu that appears. Alternatively, double-click on the component to access the dialog
directly.
Configure (32-bit Processors) dialog (Figure 2). Access to this dialog depends on the docume nt in which
Component Properties dialog for
Figure 2. Options to configure the architecture of the ARM720T_LH79520.
The drop-down field at the top-right of the dialog enables you to choose the type of processor you want to work with. As the
pinouts for the Wishbone interfaces between the 32-bit processors are the same, you can easily change the processor used in
your design without having to extensively rewire the extern al interfaces.
As you select the processor type, the
options available. The symbol on the schematic will also change to reflect the type of processor and configuration options
chosen.
For the ARM720T_LH79520, a single architectural option is available that allows you to define the size of the internal memory
for the processor. This memory, also referred to as ‘Low’ or ‘Boot’ memory is implemented using true dual port FPGA Block
RAM and will contain the boot part of a software application and the interrupt and exception han dlers.
Configure (32-bit Processors) dialog will change accordingly to refl ect the architectural
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Speed-critical (or latency-sensitive) parts of an application should also be p laced in this memory space.
The following memory sizes are available to choose from:
• 1KB (256 x 32-bit Words)
2KB (512 x 32-bit Words)
•
4KB (1K x 32-bit Words)
•
8KB (2K x 32-bit Words)
•
16KB (4K x 32-bit Words)
•
32KB (8K x 32-bit Words)
•
64KB (16K x 32-bit Words)
•
128KB (32K x 32-bit Words)
•
256KB (64K x 32-bit Words)
•
512KB (128K x 32-bit Words)
•
1MB (256K x 32-bit Words)
•
When the component is placed on a schematic sheet, your configuration choice
will be reflected in the
Current Configuration region of the processor’s
schematic symbol (Figure 3).
Note: There are no options to remove MDU or Debug Hardware for the
ARM720T_LH79520. These architectural features are permanently installed in
the actual ARM720T within the physical LH79520 device.
For further information with respect to real-time debugging of the processor, refer
to the
On-Chip Debugging section of this reference.
Figure 3. Current configuration settings for the
processor.
CR0162 (v2.0) March 10, 2008 9
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