0.1COPYRIGHT NOTICE AND DISCLAIMER................................................................................................................................0-3
0.2WELCOME TO THE AR-B1462 CPU BOARD...........................................................................................................................0-3
0.3BEFORE YOU USE THIS GUIDE...............................................................................................................................................0-3
0.4RETURNING YOUR BOARD FOR SERVICE............................................................................................................................0-3
0.5TECHNICAL SUPPORT AND USER COMMENTS...................................................................................................................0-3
2.3.1I/O Port Address Map..........................................................................................................................................................2-3
2.4REAL-TIME CLOCK AND NON-VOLATILE RAM......................................................................................................................2-5
3.SETTING UP THE SYSTEM............................................................................................................................ 3-1
3.2.1FDD Port Connector (CN8).................................................................................................................................................3-2
3.2.2Hard Disk (IDE) Connector .................................................................................................................................................3-3
3.2.3Parallel Port Connector (CN9)............................................................................................................................................3-4
4.1CONNECTING THE CRT MONITOR.........................................................................................................................................4-1
6.SOLID STATE DISK ....................................................................................................................................... 6-1
6.4ROM DISK INSTALLATION........................................................................................................................................................6-6
6.4.5Combination of ROM and RAM Disk................................................................................................................................6-12
7.6AUTO-DETECT HARD DISKS....................................................................................................................................................7-7
7.8.1Auto Configuration with Optimal Setting.............................................................................................................................7-8
7.8.2Auto Configuration with Fail Safe Setting...........................................................................................................................7-8
7.9.1Save Settings and Exit........................................................................................................................................................7-8
7.9.2Exit Without Saving .............................................................................................................................................................7-9
Acrosser Technology makes no representations or warranties with respect to the contents hereof and specifically
disclaims any implied warranties of merchantability or fitness for any particular purpose. Furthermore, Acrosser
Technology reserves the right to revise this publication and to make changes from time to time in the contents
hereof without obligation of Acrosser Technology to notify any person of such revisions or changes.
Possession, use, or copying of the software described in this publication is authorized only pursuant to a valid
written license from Acrosser or an authorized sublicensor.
(C) Copyright Acrosser Technology Co., Ltd., 1997. All rights Reserved.
Acrosser, ALI, AMI, HMC, IBM PC/AT, Windows 3.1, Windows 95, Windows NT, AMD, Cyrix, Intel…are registered
trademarks.
All other trademarks and registered trademarks are the property of their respective holders.
This document was produced with Adobe Acrobat 3.01.
0.2 WELCOME TO THE AR-B1462 CPU BOARD
This guide introduces the Acrosser AR-B1462 CPU board.
Use the information describes this card’ s functions, features, and how to start, set up and operate your ARB1462. You also could find general system information here.
0.3 BEFORE YOU USE THIS GUIDE
If you have not already installed this AR-B1462, refer to the Chapter 3, “Setting Up the System” in this guide.
Check the packing list, make sure the accessories in the package.
The AR-B1462 diskette provides the newest information about the card. Please refer to the README.DOC fileof the enclosed utility diskette. It contains the modification and hardware & software information, and adding
the description or modification of product function after manual published.
0.4 RETURNING YOUR BOARD FOR SERVICE
If your board requires servicing, contact the dealer from whom you purchased the product for service information.
If you need to ship your board to us for service, be sure it is packed in a protective carton. We recommend that
you keep the original shipping container for this purpose.
You can help assure efficient servicing of your product by following these guidelines:
1. Include your name, address, telephone and facsimile number where you may be reached during the day.
2. A description of the system configuration and/or software at the time is malfunction.
3. A brief description is in the symptoms.
0.5 TECHNICAL SUPPORT AND USER COMMENTS
User’ s comments are always welcome as they assist us in improving the usefulness of our products and the
understanding of our publications. They form a very important part of the input used for product enhancement
and revision.
We may use and distribute any of the information you supply in any way we believe appropriate without incurring
any obligation. You may, of course, continue to use the information you supply.
If you have suggestions for improving particular sections or if you find any errors, please indicate the manual title
and book number.
Please send your comments to Acrosser Technology Co., Ltd. or your local sales representative.
Internet electronic mail to: webmaster@acrosser.com
0-3
AR-B1462 User¡¦s Guide
0.6 ORGANIZATION
This information for users covers the following topics (see the Table of Contents for a detailed listing):
l Chapter 1, “Overview”, provides an overview of the system features and packing list.
l Chapter 2, “System Controller” describes the major structure.
l Chapter 3, “Setting Up the System”, describes how to adjust the jumper, and the connectors setting.
l Chapter 4, “CRT/LCD Flat Panel Display”, describes the configuration and installation procedure using
the LCD and CRT display.
l Chapter 5, “Installation”, describes setup procedures including information on the utility diskette.
l Chapter 6, “Solid State Disk”, describes the various type SSDs’ installation steps.
l Chapter 7, “BIOS Console”, providing the BIOS options setting.
l Chapter 8, Specifications & SSD Types Supported
l Chapter 9, Placement & Dimensions
l Chapter 10, Programming RS-485 & Index
0.7 STATIC ELECTRICITY PRECAUTIONS
Before removing the board from its anti-static bag, read this section about static electricity precautions.
Static electricity is a constant danger to computer systems. The charge that can build up in your body may be
more than sufficient to damage integrated circuits on any PC board. It is, therefore, important to observe basic
precautions whenever you use or handle computer components. Although areas with humid climates are much
less prone to static build-up, it is always best to safeguard against accidents may result in expensive repairs. The
following measures should generally be sufficient to protect your equipment from static discharge:
• Touch a grounded metal object to discharge the static electricity in your body (or ideally, wear a grounded
wrist strap).
• When unpacking and handling the board or other system component, place all materials on an antic static
surface.
• Be careful not to touch the components on the board, especially the “golden finger” connectors on the bottom
of every board.
0-4
AR-B1462 User¡¦s Guide
1. OVERVIEW
This chapter provides an overview of your system features and capabilities. The following topics are covered:
l Introduction
l Packing List
l Features
1.1 INTRODUCTION
The AR-B1462 is a disk size industrial grade CPU card that has been designed to withstand continuous operation
in harsh environments. The total on-board memory for the AR-B1462 can be configured from 1MB to 128MB by
using all 72-pin type DRAM SIMM devices.
The 8 layers PCB CPU card is equipped with a IDE HDD interface, a floppy disk drive adapter, 1 parallel port, 4
serial ports and a watchdog timer. Its dimensions are as compact as 146mmX203mm. It highly condensed
features make it an ideal cost/performance solution for high-end commercial and industrial applications where CPU
speeding and mean time between failure is critical.
The AR-B1462 provides 2 bus interfaces, ISA bus and PC/104 compatible expansion bus. Based on the PC/104
expansion bus, you could easy install thousands of PC/104 module from hundreds venders around the world. You
could also directly connect the power supply to the AR-B1462 on-board power connector in standalone
applications.
A watchdog timer has a software programmable time-out interval, is also provided on this CPU card. It ensures
that the system does not hang-up if a program can not execute normally.
A super I/O chip (SMC37C669) is embedded in the AR-B1462 card. It combines functions of a floppy disk drive
adapter, a hard disk drive (IDE) adapter, four serial (with 16C550 UART) adapters and 1 parallel adapter. The I/O
port configurations can be done by set the BIOS setup program.
As an UART, the chip supports serial to parallel conversion on data characters received from a peripheral device
or a MODEM, and parallel to serial conversion on data character received from the CPU. The UART includes a
programmable baud rate generator, complete MODEM control capability and a processor interrupt system. As a
parallel port, the SMC37C669 provides the user with a fully bi-directional parallel centronics-type printer interface.
The special device is the AR-B1462 provides one audio connector, the sound system is built-in 16bit PnP sound
blaster with DOS and Windows drivers. In the same time the AR-B1462 provides network connectors that are 10M
bps NE2000 compatible. We designed the connectors for easily setup.
The super VGA controller supports CRT color monitor, STN, Dual-Scan, TFT, monochrome and colored panels. It
can be connected to create a compact video solution for the industrial environment. And provides the touch screen
header on the serial port 4 for multiple function.
Note: Just the AR-B1462A supported the audio function and supported 2MB on-board VRAM. The AR-B1462 only
supported 1MB on-board VRAM.
1-1
AR-B1462 User¡¦s Guide
1.2 PACKING LIST
The accessories are included with the system. Before you begin installing your AR-B1462 board, take a moment
to make sure that the following items have been included inside the AR-B1462 package.
l The quick setup manual
l 1 AR-B1462 CPU card
l 1 Hard disk drive interface cable
l 1 Floppy disk drive interface cable
l 1 Parallel port interface cable
l 1 AUI cable
l 1 PS/2 mouse cable
l 1 Keyboard adapter
l 1 RJ-45 network cable
l 1 20-pin RS-485/RS-422 adapter cable
l 1 10-pin to DB-15 VGA
l 4 phone-jack to DB-9 adapter
l 4 Software utility diskettes
If use the AR-B1462A CPU card, the card added the audio function the accessories also added as follows.
l 1 AR-B9425 card
l 1 audio adapter cable
1.3 FEATURES
The system provides a number of special features that enhance its reliability, ensure its availability, and improve its
expansion capabilities, as well as its hardware structure.
l All-In-One designed 486DX/DX2/DX4 CPU card.
l Supports 25 to 133 MHz 3.3V/3.45V/5V CPU with voltage regulator.
l Supports ISA bus and PC/104 bus.
l Supports 512KB cache on board.
l Supports two 72-pin DRAM SIMMs up to 128MB DRAM on board.
l Supports D.O.C. up to 72MB.
l Legal AMI BIOS.
l IDE hard disk drive interface.
l Floppy disk drive interface.
l Bi-direction parallel interface.
l 4 serial ports with 16C550 UART.
l Programmable watchdog timer.
l Build-in 16bit PnP sound blaster with DOS and Windows drivers
l Supports 10M bps NE2000 compatible chips.
l On-board built-in buzzer.
l 8 layers PCB.
1-2
AR-B1462 User¡¦s Guide
2. SYSTEM CONTROLLER
This chapter describes the major structure of the AR-B1462 CPU board. The following topics are covered:
l DMA Controller
l Keyboard Controller
l Interrupt Controller
l Real-Time Clock and Non-Volatile RAM
l Timer
l Serial Port
l Parallel Port
2.1 DMA CONTROLLER
The equivalent of two 8237A DMA controllers are implemented in the AR-B1462 board. Each controller is a fourchannel DMA device that will generate the memory addresses and control signals necessary to transfer
information directly between a peripheral device and memory. This allows high speeding information transfer with less
CPU intervention. The two DMA controllers are internally cascaded to provide four DMA channels for transfers to
8-bit peripherals (DMA1) and three channels for transfers to 16-bit peripherals (DMA2). DMA2 channel 0 provides
the cascade interconnection between the two DMA devices, thereby maintaining IBM PC/AT compatibility.
Following is the system information of DMA channels:
The 8042 processor is programmed to support the keyboard serial interface. The keyboard controller receives
serial data from the keyboard, checks its parity, translates scan codes, and presents it to the system as a byte data
in its output buffer. The controller can interrupt the system when data is placed in its output buffer, or wait for the
system to poll its status register to determine when data is available.
Data can be written to the keyboard by writing data to the output buffer of the keyboard controller.
Each byte of data is sent to the keyboard controller in series with an odd parity bit automatically inserted. The
keyboard controller is required to acknowledge all data transmissions. Therefore, another byte of data will not be
sent to keyboard controller until acknowledgment is received for the previous byte sent. The “output buffer full”
interruption may be used for both send and receive routines.
2-1
AR-B1462 User¡¦s Guide
2.3 INTERRUPT CONTROLLER
The equivalent of two 8259 Programmable Interrupt Controllers (PIC) are included on the AR-B1462 board. They
accept requests from peripherals, resolve priorities on pending interrupts in service, issue interrupt requests to the
CPU, and provide vectors which are used as acceptance indices by the CPU to determine which interrupt service
routine to execute.
Following is the system information of interrupt levels:
InInterrupt Level
NMI
CTRL1
IRQ 0
IRQ 1
IRQ 2
IRQ 3
IRQ 4
IRQ 5
IRQ 6
IRQ 7
Description
Parity check
CTRL2
System timer interrupt from timer 8254
Keyboard output buffer full
IRQ8 : Real time clock
IRQ9 : Rerouting to INT 0Ah from hardware IRQ2
IRQ10 : Reserved for LAN
IRQ11 : Serial port 4
IRQ12 : spare (PS/2 mouse)
IRQ13 : Math. coprocessor
IRQ14 : Hard disk adapter
IRQ15 : spare (Watchdog Timer)
Serial port 2
Serial port 1
Serial port 3
Floppy disk adapter
Parallel port 1
Figure 2-1 Interrupt Controller
2-2
2.3.1 I/O Port Address Map
Hex RangeDevice
000-01FDMA controller 1
020-021Interrupt controller 1
022-023System -- ALI M1489/M1487
The AR-B1462 contains a real-time clock compartment that maintains the date and time in addition to storing
configuration information about the computer system. It contains 14 bytes of clock and control registers and 114
bytes of general purpose RAM. Because of the use of CMOS technology, it consumes very little power and can be
maintained for long period of time using an internal Lithium battery. The contents of each byte in the CMOS RAM
are listed as follows:
AddressDescription
00Seconds
01Second alarm
02Minutes
03Minute alarm
04Hours
05Hour alarm
06Day of week
07Date of month
08Month
09Year
0AStatus register A
0BStatus register B
0CStatus register C
0DStatus register D
0EDiagnostic status byte
0FShutdown status byte
10Diskette drive type byte, drive A and B
11Fixed disk type byte, drive C
12Fixed disk type byte, drive D
13Reserved
14Equipment byte
15Low base memory byte
16High base memory byte
17Low expansion memory byte
18High expansion memory byte
19-2DReserved
2E-2F2-byte CMOS checksum
30Low actual expansion memory byte
31High actual expansion memory byte
32Date century byte
33Information flags (set during power on)
34-7FReserved for system BIOS
Table 2-5 Real-Time Clock & Non-Volatile RAM
2.5 TIMER
The AR-B1462 provides three programmable timers, each with a timing frequency of 1.19 MHz.
Timer 0The output of this timer is tied to interrupt request 0. (IRQ 0)
Timer 1This timer is used to trigger memory refresh cycles.
Timer 2This timer provides the speaker tone.
Application programs can load different counts into this timer to generate various sound frequencies.
2-5
AR-B1462 User¡¦s Guide
2.6 SERIAL PORT
The ACEs (Asynchronous Communication Elements ACE1 to ACE4) are used to convert parallel data to a serial
format on the transmit side and convert serial data to parallel on the receiver side. The serial format, in order of
transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one,
one and half (five-bit format only) or two stop bits. The ACEs are capable of handling divisors of 1 to 65535, and
produce a 16x clock for driving the internal transmitter logic.
Provisions are also included to use this 16x clock to drive the receiver logic. Also included in the ACE a completed
MODEM control capability, and a processor interrupt system that may be software tailored to the computing time
required handle the communications link.
The following table is summary of each ACE accessible register
0base + 1Interrupt enable
Xbase + 2Interrupt identification (read only)
Xbase + 3Line control
Xbase + 4MODEM control
Xbase + 5Line status
Xbase + 6MODEM status
Xbase + 7Scratched register
1base + 0Divisor latch (least significant byte)
1base + 1Divisor latch (most significant byte)
Table 2-6 ACE Accessible Registers
(1) Receiver Buffer Register (RBR)
Bit 0-7: Received data byte (Read Only)
(2) Transmitter Holding Register (THR)
Bit 0-7: Transmitter holding data byte (Write Only)
(3) Interrupt Enable Register (IER)
Bit 0: Enable Received Data Available Interrupt (ERBFI)
Bit 1: Enable Transmitter Holding Empty Interrupt (ETBEI)
Bit 2: Enable Receiver Line Status Interrupt (ELSI)
Bit 3: Enable MODEM Status Interrupt (EDSSI)
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
(4) Interrupt Identification Register (IIR)
Bit 0: “0” if Interrupt Pending
Bit 1: Interrupt ID Bit 0
Bit 2: Interrupt ID Bit 1
Bit 3: Must be 0
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
2-6
(5) Line Control Register (LCR)
Word Length
Bit 0: Word Length Select Bit 0 (WLS0)
Bit 1: Word Length Select Bit 1 (WLS1)
WLS1WLS0
005 Bits
016 Bits
107 Bits
118 Bits
Bit 2: Number of Stop Bit (STB)
Bit 3: Parity Enable (PEN)
Bit 4: Even Parity Select (EPS)
Bit 5: Stick Parity
Bit 6: Set Break
Bit 7: Divisor Latch Access Bit (DLAB)
(6) MODEM Control Register (MCR)
Bit 0: Data Terminal Ready (DTR)
Bit 1: Request to Send (RTS)
Bit 2: Out 1 (OUT 1)
Bit 3: Out 2 (OUT 2)
Bit 4: Loop
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
AR-B1462 User¡¦s Guide
(7) Line Status Register (LSR)
Bit 0: Data Ready (DR)
Bit 1: Overrun Error (OR)
Bit 2: Parity Error (PE)
Bit 3: Framing Error (FE)
Bit 4: Break Interrupt (BI)
Bit 5: Transmitter Holding Register Empty (THRE)
Bit 6: Transmitter Shift Register Empty (TSRE)
Bit 7: Must be 0
(8) MODEM Status Register (MSR)
Bit 0: Delta Clear to Send (DCTS)
Bit 1: Delta Data Set Ready (DDSR)
Bit 2: Training Edge Ring Indicator (TERI)
Bit 3: Delta Receive Line Signal Detect (DSLSD)
Bit 4: Clear to Send (CTS)
Bit 5: Data Set Ready (DSR)
Bit 6: Ring Indicator (RI)
Bit 7: Received Line Signal Detect (RSLD)
2-7
AR-B1462 User¡¦s Guide
(9) Divisor Latch (LS, MS)
Bit 0:Bit 0Bit 8
Bit 1:Bit 1Bit 9
Bit 2:Bit 2Bit 10
Bit 3:Bit 3Bit 11
Bit 4:Bit 4Bit 12
Bit 5:Bit 5Bit 13
Bit 6:Bit 6Bit 14
Bit 7:Bit 7Bit 15
Table 2-7 Serial Port Divisor Latch
LSMS
Desired Baud RateDivisor Used to Generate 16x Clock
300384
600192
120096
180064
240048
360032
480024
960012
144008
192006
288004
384003
576002
1152001
2.7 PARALLEL PORT
(1) Register Address
Port AddressRead/WriteRegister
base + 0WriteOutput data
base + 0ReadInput data
base + 1ReadPrinter status buffer
base + 2WritePrinter control latch
Table 2-8 Registers’ Address
(2) Printer Interface Logic
The parallel portion of the SMC37C669 makes the attachment of various devices that accept eight bits of parallel
data at standard TTL level.
(3) Data Swapper
The system microprocessor can read the contents of the printer’ s Data Latch through the Data Swapper by reading
the Data Swapper address.
2-8
AR-B1462 User¡¦s Guide
(4) Printer Status Buffer
The system microprocessor can read the printer status by reading the address of the Printer Status Buffer. The bit
definitions are described as follows:
12345670
XXX
-ERROR
SLCT
PE
-ACK
-BUSY
Figure 2-2 Printer Status Buffer
NOTE: X presents not used.
Bit 7: This signal may become active during data entry, when the printer is off-line during printing, or when the
print head is changing position or in an error state. When Bit 7 is active, the printer is busy and can not
accept data.
Bit 6: This bit represents the current state of the printer’ s ACK signal. A0 means the printer has received the
character and is ready to accept another. Normally, this signal will be active for approximately 5
microseconds before receiving a BUSY message stops.
Bit 5: A1 means the printer has detected the end of the paper.
Bit 4: A1 means the printer is selected.
Bit 3: A0 means the printer has encountered an error condition.
2-9
AR-B1462 User¡¦s Guide
(5) Printer Control Latch & Printer Control Swapper
The system microprocessor can read the contents of the printer control latch by reading the address of printer
control swapper. Bit definitions are as follows:
12345670
XX
STROBE
AUTO FD XT
INIT
SLDC IN
IRQ ENABLE
DIR(write only)
Figure 2-3 Bit’ s Definition
NOTE: X presents not used.
Bit 5: Direction control bit. When logic 1, the output buffers in the parallel port are disabled allowing data driven
from external sources to be read; when logic 0, they work as a printer port. This bit is write only.
Bit 4: A1 in this position allows an interrupt to occur when ACK changes from low state to high state.
Bit 3: A1 in this bit position selects the printer.
Bit 2: A0 starts the printer (50 microseconds pulse, minimum).
Bit 1: A1 causes the printer to line-feed after a line is printed.
Bit 0: A0.5 microsecond minimum highly active pulse clocks data into the printer. Valid data must be present for
a minimum of 0.5 microseconds before and after the strobe pulse.
2-10
AR-B1462 User¡¦s Guide
3. SETTING UP THE SYSTEM
This section describes pin assignments for system’ s external connectors and the jumpers setting.
l Overview
l System Setting
l Ethernet Controller
3.1 OVERVIEW
The AR-B1462 is a half size industrial grade CPU card that has been designed to withstand continuous operation
in harsh environments. This section provides hardware’ s jumpers setting, the connectors’ locations, and the pin
assignment.
Note: Just the AR-B1462A supported the audio function and supported 2MB on-board VRAM. The AR-B1462 only
Jumper pins allow you to set specific system parameters. Set them by changing the pin location of jumper blocks.
(A jumper block is a small plastic-encased conductor [shorting plug] that slips over the pins.) To change a jumper
setting, remove the jumper from its current location with your fingers or small needle-nosed pliers. Place the
jumper over the two pins designated for the desired setting. Press the jumper evenly onto the pins. Be careful not
to bend the pins.
We will show the locations of the AR-B1462 jumper pins, and the factory-default setting.
CAUTION: Do not touch any electronic component unless you are safely grounded. Wear a grounded wrist strap
or touch an exposed metal part of the system unit chassis. The static discharges from your fingers can
permanently damage electronic components.
3.2.1 FDD Port Connector (CN8)
The AR-B1462 provides a 34-pin header type connector for supporting up to two floppy disk drives.
To enable or disable the floppy disk controller, please use the BIOS Setup program.
A 40-pin header type connector (CN5) is provided to interface with up to two embedded hard disk drives (IDE AT
bus). This interface, through a 40-pin cable, allows the user to connect up to two drives in a “daisy chain” fashion.
To enable or disable the hard disk controller, please use the BIOS Setup program. The following table illustrates
the pin assignments of the hard disk drive’ s 40-pin connector.
CN5
-IDERST 12 GROUND
D7 3
D6 5
D5 7
D4 9
D3 11
D2 13
D1 15
D0 17
GROUND 19
Not Used 21
-IOW 23
-IOR 25
-IORDY 27
Not Used 29
IRQ 14 31
HDA1 33
HDA0 35
-HDCS0 37
-HDLED 39
Figure 3-3 CN5: Hard Disk (IDE) Connector
4 D8
6 D9
8 D10
10 D11
12 D12
14 D13
16 D14
18 D15
20 Not Used
22 GROUND
24 GROUND
26 GROUND
28 Not Used
30 GROUND
32 -IO16
34 Not Used
36 HDA2
38 -HDCS1
40 GROUND
Caution: When the CN5 is used to connect the hard disk drive, if you find it can not make partition, please
change the hard disk cable to below 35cm in length.
(2) 44-Pin Hard Disk (IDE) Connector (CN7)
AR-B1462 also provides IDE interface 44-pin connector to connect with the hard disk device.
CN7
-IDERST 12 GROUND
D7 3
D6 5
D5 7
D4 9
D3 11
D2 13
D1 15
D0 17
GROUND 19
Not Used 21
-IOW 23
-IOR 25
-IORDY 27
Not Used 29
IRQ 14 31
HDA1 33
HDA0 35
-HDCS0 37
-HDLED 39
VCC 41
GROUND 43
Figure 3-4 CN7: Hard Disk (IDE) Connector
4 D8
6 D9
8 D10
10 D11
12 D12
14 D13
16 D14
18 D15
20 Not Used
22 GROUND
24 GROUND
26 GROUND
28 Not Used
30 GROUND
32 -IO16
34 Not Used
36 HDA2
38 -HDCS1
40 GROUND
42 VCC
44 Not Used
3-3
AR-B1462 User¡¦s Guide
3.2.3 Parallel Port Connector (CN9)
To use the parallel port, an adapter cable has to be connected to the CN9 (26-pin header type) connector. This
adapter cable is mounted on a bracket and is included in your AR-B1462 package. The connector for the parallel
port is a 25 pin D-type female connector.
BUSCLK [Output]The BUSCLK signal of the I/O channel is asynchronous to
RSTDRV [Output]This signal goes high during power-up, low line-voltage or
SA0 - SA19
[Input / Output]
LA17 - LA23
[Input/Output]
SD0 - SD15
[Input/Output]
BALE [Output]The Buffered Address Latch Enable is used to latch SA0 -
-IOCHCK [Input]The I/O Channel Check is an active low signal which
IOCHRDY
[Input, Open collector]
IRQ 3-7, 9-12, 14, 15
-IOR
[Input/Output]
-IOW [Input/Output] The I/O write signal is an active low signal which instructs
-SMEMR [Output]The System Memory Read is low while any of the low 1
-MEMR
[Input/Output]
-SMEMW [Output]The System Memory Write is low while any of the low 1
-MEMW
[Input/Output]
DRQ 0-3, 5-7 [Input] DMA Request channels 0 to 3 are for 8-bit data transfers.
-DACK 0-3, 5-7
[Output]
AEN [output]The DMA Address Enable is high when the DMA controller
-REFRESH
[Input/Output]
TC [Output]Terminal Count provides a pulse when the terminal count
SBHE [Input/Output] The System Bus High Enable indicates the high byte SD8 -
the CPU clock.
hardware reset
The System Address lines run from bit 0 to 19. They are
latched onto the falling edge of "BALE"
The Unlatched Address line run from bit 17 to 23
System Data bit 0 to 15
SA19 onto the falling edge. This signal is forced high
during DMA cycles
indicates that a parity error exist on the I/O board
This signal lengthens the I/O, or memory read/write cycle,
and should be held low with a valid address
The Interrupt Request signal indicates I/O service request
[Input]
attention. They are prioritized in the following sequence :
(Highest) IRQ 9, 10, 11, 12, 13, 15, 3, 4, 5, 6, 7 (Lowest)
The I/O Read signal is an active low signal which instructs
the I/O device to drive its data onto the data bus
the I/O device to read data from the data bus
mega bytes of memory are being used
The Memory Read signal is low while any memory location
is being read
mega bytes of memory is being written
The Memory Write signal is low while any memory location
is being written
DMA Request channels 5 to 7 are for 16-bit data transfers.
DMA request should be held high until the corresponding
DMA has been completed. DMA request priority is in the
following sequence:(Highest) DRQ 0, 1, 2, 3, 5, 6, 7
(Lowest)
The DMA Acknowledges 0 to 3, 5 to 7 are the
corresponding acknowledge signals for DRQ 0 to 3 and 5
to 7
is driving the address bus. It is low when the CPU is driving
the address bus
This signal is used to indicate a memory refresh cycle and
can be driven by the microprocessor on the I/O channel
for any DMA channel is reached
SD15 on the data bus
3-6
NameDescription
-MASTER [Input]The MASTER is the signal from the I/O processor which
gains control as the master and should be held low for a
maximum of 15 microseconds or system memory may be
lost due to the lack of refresh
-MEMCS16
[Input, Open collector]
-IOCS16
[Input, Open collector]
OSC [Output]The Oscillator is a 14.31818 MHz signal used for the color
-ZWS
[Input, Open collector]
Table 3-2 I/O Channel Signal’ s Description
The Memory Chip Select 16 indicates that the present data
transfer is a 1-wait state, 16-bit data memory operation
The I/O Chip Select 16 indicates that the present data
transfer is a 1-wait state, 16-bit data I/O operation
graphic card
The Zero Wait State indicates to the microprocessor that
the present bus cycle can be completed without inserting
additional wait cycle
3.2.5 LED Header (LM1)
The AR-B1462 provides one module for various LEDs’ headers.
LM1
1
3
5
7
2
+5V Power LED Header
4
Watchdog LED Header
6
LAN LED Header
8
HDD LED Header
AR-B1462 User¡¦s Guide
Figure 3-10 LM1: LED Header
3.2.6 Serial Port
(1) RS-422/RS-485 Select
SW1-9 & SW1-10 selects COM B port, and adjusts the CN15 connector is RS-485 or RS-232C. M5 selects COM A
port for using DB2 for RS-232C or connects External RS-485.