SLS SL74LV32, SL74LV32D, SL74LV32N Datasheet

TECHNICAL DATA

Semiconductor

Quad 2-Input OR Gate

The SL74LV32 is low-voltage Si-gate CMOS device and is pin and

function compatible with 74HC/HCT32A.

The SL74LV32 provides the 2-input AND function.

• Optimized for Low Voltage applications: 1.2 to 3.6 V

• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

• Low Input Current

SL74LV32

ORDERING INFORMATION

SL74LV32N Plastic
SL74LV32D SOIC
IZ74LV32 Chip

TA = -40° ÷ 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

A1

B1

Y1

A2

B2

Y2

A3
B3

A4

B4

PIN 14 =VCC

PIN 7 = GND

Y3

Y4

FUNCTION TABLE

Input Output

A B Y = A*B

L L L

L H H
H L H
H H H

H - high level
L - low level

SLS

System Logic

1

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC supply voltage (Referenced to GND) -0.5 ÷ +5.0 V

IIK *1 DC input diode current ±20 mA

IOK *2 DC output diode current ±50 mA

SL74LV32

IO *3 DC output source or sink current

±25 mA

-bus driver outputs

ICC DC VCC current for types with

±50 mA

- bus driver outputs

I

DC GND current for types with

GND

±50 mA

- bus driver outputs

PD Power dissipation per package, plastic DIP+

SOIC package+

750
500

Tstg Storage temperature -65 ÷ +150 °C

TL Lead temperature, 1.5 mm from Case for 10 se conds

260 °C

(Plastic DIP ), 0.3 mm (SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C

SOIC Package: : - 8 mW/°C from 70° to 125°C

*1: VI < -0.5V or V

> VCC+0.5V

I

*2: Vo < -0.5V or Vo > VCC+0.5V
*3: -0.5V < Vo < VCC+0.5V

RECOMMENDED OPERATING CONDITIONS

mW

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 1.2 3.6 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -40 +125 °C

tr, tf Input Rise and Fall Time VCC =1.2 V

VCC =2.0 V
V

=3.0 V

CC

V

=3.6 V

CC

0
0
0
0

1000

700
500
400

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, VIN and V
V

)≤VCC.

OUT

should be constrained to the range GND≤(VIN or

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.

SLS

System Logic

2