SLS SL74LV14, SL74LV14D, SL74LV14N Datasheet

TECHNICAL DATA

Semiconductor

SL74LV14

Hex Schmitt-Trigger Inverter

The 74LV14 is a low -voltage Si-gate CMOS device and is pin and

function compatible with 74HC/HCT14.

The 74LV14 provides six inverting buffers with Schmitt-trigger action.

• Wide Operating Voltage: 1.0 to 5.5 V

• Optimized for Low Voltage applications: 1.0 to 3.6 V

• Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V

• Low input current

LOGIC DIAGRAM

ORDERING INFORMATION

SL74LV14N Plastic
SL74LV14D SOIC
SL74LV14 Chip

TA = -40° ÷ 125° C for all packages

PIN ASSIGNMENT

FUNCTION TABLE

Input Output

A

L H

H L

PIN 14 =VCC
PIN 7 = GND

Y= A

SLS

System Logic

1

SL74LV14

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC supply voltage (Referenced to GND) -0.5 ~ +7.0 V

IIK*1 DC input diode current ±20 mA

IOK*2 DC output diode current ±50 mA

Io*3 DC output source or sink current

±25 mA

-bus driver outputs

I

DC GND current for types with

GND

±50 mA

- bus driver outputs

ICC DC VCC current for types with

±50 mA

- bus driver outputs

PD Power dissipation per paskade, plastic DIP+

SOIC package+

750
500

Tstg Storage temperature -65 ~ +150 °C

TL Lead temperature, 1.5 mm from Case for 10 seconds

260 °C

(Plastic DIP ), 0.3 mm (SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C

SOIC Package: : - 8 mW/°C from 70° to 125°C

*1: VI < -0.5V or V

> VCC+0.5V

I

*2: Vo < -0.5V or Vo > VCC+0.5V
*3: -0.5V < Vo < VCC+0.5V

RECOMMENDED OPERATING CONDITIONS

mW

Symbol Parameter Min Max Unit

VCC DC Supply Vol tage (Referenced to GND) 1.0 5.5 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -40 +125 °C

tr, tf Input Rise and Fall Time 1.0 V ≤VCC <2.0 V

2.0 V ≤VCC <2.7 V

2.7 V ≤VCC <3.6 V

3.6 V ≤VCC ≤5.5 V

0
0
0
0

500
200
100

50

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.

System Logic

SLS

2