SLS SL74LS161D, SL74LS161N Datasheet

Semiconductor

Synchronous 4 Bit Counters; Binary,
Direct Reset

This synchronous, presettable counter features an internal carry
look-ahead for application in high-speed counting designs.
Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change conicident with each other
when so instructed by the count-enable inputs and internal gating.

This mode of operation eliminates the output counting spikes that
are normally associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip -flops on the rising (positive­going) edge of the clock input wave form.

This counter is fully programmable; that is the outputs may be
preset to either level. As presetting is synchronous setting up a low
level at the load input disables the counter and causes the outputs to
agree with the setup data after the next clock pulse regardless of the
levels of the enable inputs.

The carry look-ahead circuitry provides for cascading counters for
n-bit synchronous applications without additional gating. Instrumental
in accomplishiing this function are two counter-enable inputs and a
ripple carry output. Both countenable inputs (ENABLE P and
ENABLE T) must be high to count, and ENABLE T is fed forward to
enable the ripple carry output. The ripple carry output thus enabled
will produce a high-level output pulse with a duration approximately
equal to the high level portion of the QA output. The high-level
overflow ripple carry pulse can be enable successive cascaded
stages. Transitions at the ENPor ENT are allowed regardless of the
level of the clock input.

• Internal Look -Ahead for Fast Counting

• Carry Output for n-Bit Cascading

• Synchronous Counting

• Synchronously Programmable

• Load Control Line

• Diode-Clamped Inputs

ORDERING INFORMATION

SL74LS161

SL74LS161N Plastic

SL74LS161D SOIC

TA = 0° to 70° C for all

packages

PIN ASSIGNMENT

SLS

LOGIC DIAGRAM

PIN 16 =VCC

PIN 8 = GND

System Logic

SL74LS161

Semiconductor

Reset Load Enable P Enable T Clock Q0 Q1 Q2 Q3 Function

L X X X X L L L L Reset to “0”
H L X X P0 P1 P2 P3 Preset Data
H H X L No change No count
H H L X No change No count
H H H H Count up Count
H X X X No change No count

X=don’t care
P0,P1,P2,P3 = logic level of Data inputs
Ripple Carry Out = Enabl e T • Q0 • Q1 • Q2 • Q3

FUNCTION TABLE

Inputs Outputs

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC Supply Voltage 7.0 V
VIN Input Voltage 7.0 V

V

Output Voltage 5.5 V

OUT

Tstg Storage Temperature Range -65 to +150 °C

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC Supply Voltage 4.75 5.25 V
VIH High Level Input Voltage 2.0 V

VIL Low Level Input Voltage 0.8 V
IOH High Level Output Current -0.4 mA
IOL Low Level Output Current 8.0 mA

f

Clock frequency 0 25 MHz

clock

t

Width of clock pulse 25 ns

w(clock)

t

Width of reset pulse 20 ns

w(reset)

Data inputs P0, P1, P2, P3 20

tsu Setup time Enable P or T 20 ns

Load 20

th Hold time at any input 3 ns

TA Ambient Temperature Range 0 +70 °C

System Logic

SLS