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SL74HCT573
Octal 3-State Noninverting Transparent Latch
High-Performance Silicon-Gate CMOS
The SL74HCT573 is identical in pinout to the LS/ALS573. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High-Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeti ng the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches,
but when Output Enable is high, all device outputs are forced to the
high-impedance state. Thus, data may be latched even when the
outputs are not enabled.
• TTL/NMOS-Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
SL74HCT573N Plastic
SL74HCT573D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Output
Enable
L H H H
L H L L
Inputs Output
Latch
Enable
D Q
L L X no change
H X X Z
X = don’t care
Z = high impedance
System Logic
SLS
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SL74HCT573
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±20 mA
I
DC Output Current, per Pin ±35 mA
OUT
ICC DC Supply Current, VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
260 °C
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns
mW
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
OUT
)≤VCC.
should be constrained to the range
OUT
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
System Logic
SLS