SLS SL74HCT125D, SL74HCT125N Datasheet

Semiconductor

Quad 3-State Noninverting Buffers

SL74HCT125

High-Performance Silicon-Gate CMOS

The SL74HCT125 is identical in pinout to the LS/ALS125. The
SL74HCT125 may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.

The SL74HCT125 noninverting buffers are designed to be used with
3-state memory address drivers, clock drivers, and other bus-oriented
systems. The devices have four separate output enables that are active­low.

• TTL/NMOS Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 µA

LOGIC DIAGRAM

ORDERING INFORMATION

SL74HCT125N Plastic

SL74HCT125D SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

SLS

System Logic

PIN 14 =V

PIN 7 = GND

CC

FUNCTION TABLE

Inputs Output

A OE Y

H L H

L L L

X H Z

X = don’t care
Z = high impedance

SL74HCT125

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±20 mA

I

DC Output Current, per Pin ±35 mA

OUT

ICC DC Supply Current, VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750
500

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which dam age to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns

mW

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. Fo r proper operation, VIN and V
GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.

System Logic

SLS