SLS SL74HC4046D, SL74HC4046N Datasheet
SL74HC4046
Semiconductor
Phase-Locked Loop
High-Performance Silicon-Gate CMOS
The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC4046 phase-locked loop contains three phase
comparators, a voltage-controlled oscillator (VCO) and unity gain opamp DEM
COMPIN, and SIGIN. Input SIG
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The self-bias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator 1
(an exclusive OR gate) provides a digital error signal PC1
maintains 90 degrees phase shift at the center frequency between SIG
and COMPIN signals (both at 50% duty cycle). Phase comparator 2
(with leading-edge sensing logic) provides digital error signals PC2
and PCP
COMPIN signals (duty cycle is immaterial). The linear VCO produces an
output signal VCO
input VCO
C1A, C1B, R1 and R2. The unity gain op-amp output DEM
signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all on-amps
to minimize standby power consumption.
Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication,
frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency
conversion and motor speed control.
• Low Power Consumption Characteristic of CMOS Device
• Operating Speeds Similary to LS/ALSTTL
• Wide Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 µA Maximum (except SIG
COMPIN)
• Low Quiescent Current: 80 µA Maximum (VCO disabled)
• High Noise Immunity Characteristic of CMOS Devices
• Diode Protection on all Inputs
. The comparators have two common signal inputs,
OUT
and COMP
IN
and maintains a 0 degree phase shift between SIG
OUT
whose frequency is determined by the voltage of
OUT
signal and the capacitor and resistors connected to pins
IN
can be used directly
IN
OUT
IN
and
OUT
IN
ORDERING INFORMATION
IN
OUT
and
SL74HC4046N Plastic
SL74HC4046D SOIC
TA = -55° to 125° C for all packages
with an external resistor is used where the VCOIN
PIN ASSIGNMENT
and
Pin No. Symbol Name and Function
1 PCP
2 PC1
Phase Comparator Pulse Output
OUT
Phase Comparator 1 Output
OUT
3 COMPIN Comparator Input
4 VCO
VCO Output
OUT
5 INH Inhibit Input
6 C1A Capacitor C1 Connection A
7 C1B Capacitor C1 Connection B
8 GND Ground (0 V) VSS
9 VCOIN VCO Input
10 DEM
Demodulator Output
OUT
11 R1 Resistor R1 Connection
12 R2 Resistor R2 Connection
13 PC2
Phase Comparator 2 Output
OUT
14 SIGIN Signal Input
15 PC3
Phase Comparator 3 Output
OUT
16 VCC Positive Supply Voltage
SLS
System Logic
SL74HC4046
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±20 mA
I
DC Output Current, per Pin ±25 mA
OUT
ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
260 °C
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) VCO only 3.0 6.0 V
VCC DC Supply Voltage (Referenced to GND) NON-VCO 2.0 6.0 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
V
=6.0 V
CC
0
0
0
1000
500
400
mW
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
OUT
)≤VCC.
should be constrained to the range
OUT
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
System Logic
SLS
SL74HC4046
Semiconductor
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
VIH Minimum High-Level
Input Voltage DC
Coupled
SIG
, COMPIN
IN
VIL Maximum Low -Level
Input Voltage DC
Coupled
SIG
, COMP
IN
IN
VOH Minimum High-Level
Output Voltage
PCP
OUT
, PCn
OUT
VIN= VIH or VIL
VOL Maximum Low -Level
Output Voltage Qa-Qh
PCP
OUT
, PCn
OUT
VIN= VIH or VIL
IIN Maximum Input
Leakage Current
SIG
, COMPIN
IN
V
= 0.1 V or VCC-0.1 V
OUT
I
≤ 20 µA
OUT
2.0
4.5
6.0
V
=0.1 V or VCC-0.1 V
OUT
I
≤ 20 µA
OUT
2.0
4.5
6.0
VIN=VIH or VIL
I
≤ 20 µA
OUT
2.0
4.5
6.0
I
≤ 4.0 mA
OUT
I
≤ 5.2 mA
OUT
VIN=VIH or VIL
I
≤ 20 µA
OUT
4.5
6.0
2.0
4.5
6.0
I
OUT
I
OUT
≤ 4.0 mA
≤ 5.2 mA
4.5
6.0
VIN=VCC or GND 2.0
3.0
4.5
6.0
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±3.0
±7.0
±18.0
±30.0
≤85
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±4.0
±9.0
±23.0
±38.0
≤125
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±5.0
±11.0
±27.0
±45.0
Unit
V
V
V
V
µA
IOZ Maximum Three-State
Leakage Current
PC2
OUT
ICC Maximum Quiescent
Supply Current
(per Package)
(VCO disabled)
Pins 3,5 and 14 at VCC
Pin 9 at GND; Input
Leacage at
Pin 3 and 14 to be
excluded
Output in High-Impedance
State
VIN= VIL or VIH
V
OUT=VCC
or GND
VIN=VCC or GND
I
=0µA
OUT
6.0 ±0.5 ±5.0 ±10 µA
6.0 4.0 40 160 µA
System Logic
SLS
SL74HC4046
Semiconductor
[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS(C
VCC Guaranteed Limit
=50pF,Input tr=tf=6.0 ns)
L
Symbol Parameter V 25 °C to
-55°C
t
, t
t
t
t
t
t
PLH
PLH
PLH
PLZ
PZL
TLH
Maximum Propagation Delay, SIGIN/COMPIN to
PHL
PC1
(Figure 1)
OUT
, t
Maximum Propagation Delay, SIGIN/COMPIN to
PHL
PCP
(Figure 1)
OUT
, t
Maximum Propagation Delay , SIGIN/COMPIN to
PHL
PC3
(Figure 1)
OUT
, t
Maximum Propagation Delay , SIGIN/COMPIN
PHZ
Output Disable Time to PC2
OUT
(Figures 2 and 3)
, t
Maximum Propagation Delay , SIGIN/COMPIN
PZH
Output Enable Time to PC2
OUT
(Figures 2 and 3)
, t
Maximum Output Transition Time (Figure 1) 2.0
THL
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
175
35
30
340
68
58
270
54
46
200
40
34
230
46
39
75
15
13
[VCO Section]
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
≤85°C ≤125°C Unit
220
44
37
425
85
72
340
68
58
250
50
43
290
58
49
95
19
16
265
53
45
510
102
87
405
81
69
300
60
51
345
69
59
110
22
19
ns
ns
ns
ns
ns
ns
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C to-55°C ≤85°C ≤125°C Unit
VIH Minimum High-Level
Input Voltage INH
VIL Maximum Low -Level
Input Voltage INH
VOH Minimum High-Level
Output Voltage
VCO
OUT
VIN= VIH or VIL
VOL Maximum Low-Level
Output Voltage
VCO
OUT
VIN= VIH or VIL
V
= 0.1 V or
OUT
VCC-0.1 V
I
≤ 20 µA
OUT
V
=0.1 V or VCC-
OUT
0.1 V
I
≤ 20 µA
OUT
VIN=VIH or VIL
I
≤ 20 µA
OUT
I
≤ 4.0 mA
OUT
I
≤ 5.2 mA
OUT
VIN=VIH or VIL
I
≤ 20 µA
OUT
I
≤ 4.0 mA
OUT
I
≤ 5.2 mA
OUT
3.0
4.5
6.0
3.0
4.5
6.0
3.0
4.5
6.0
4.5
6.0
3.0
4.5
6.0
4.5
6.0
2.1
3.15
4.2
0.90
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
2.1
3.15
4.2
0.90
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
2.1
3.15
4.2
0.90
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
V
V
V
V
SLS
System Logic
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