SLS SL74HC166D, SL74HC166H Datasheet

SL74HC166

System Logic
Semiconductor

SLS

8-Bit Serial or Parallel-Input/
Serial-Output Shift Register

High-Performance Silicon-Gate CMOS

The SL74HC166 is identical in pinout to the LS/ALS166. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.

This device is a parallel-in or serial-in, serial-out shift register with
gated clock inputs and an overriding clear input. The shift/load input
establishes the parallel-in or serial-in mode. When high, this input
enables the serial data input and couples the eight flip -flops for serial
shifting with each clock pulse. Synchronous loading occurs on the
next clock pulse when this is low and the parallel data inputs are
enabled. Serial data flow is inhibited during parallel loading. Clocking is
done on the low-to-high level edge of the clock pulse via a two input
positive NOR gate, which permits one input to be used as a clock
enable or clock inhibit function. Clocking is inhibited when either of the
clock inputs are held high, holding either input low enables the other
clock input. This will allow the system clock to be free running and
the register stopped on command with the other clock input. A
change from low-to-high on the clock inhibit input should only be
done when the clock input is high. A buffered direct clear input
overrides all other inputs, including the clock, andsets all flip -flop to
zero.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

SL74HC166N Plastic

SL74HC166D SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 16 =VCC

PIN 8 = GND

SL74HC166

System Logic
Semiconductor

SLS

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

V

OUT

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

IIN DC Input Current, per Pin ±20 mA

I

OUT

DC Output Current, per Pin ±25 mA

ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750
500

mW

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

260 °C

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

VIN, V

OUT

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V

VCC =4.5 V
V

CC

=6.0 V

0
0
0

1000

500
400

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V

OUT

should be constrained to the range

GND≤(VIN or V

OUT

)≤VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.