SLS SL74HC03D, SL74HC03N Datasheet

SL74HC03

Semiconductor

Quad 2-Input NAND Gate with Open-Drain
Outputs

High-Performance Silicon-Gate CMOS

The SL74HC03 is identical in pinout to the LS/ALS03. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.

The SL74HC03 NAND gate has, as its output, a high-performance
MOS N-Channel transistor. This NAND gate can, therefore, with a
suitable pullup resistor, be used in wired-AND applications.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

LOGIC DIAGRAM

ORDERING INFORMATION

SL74HC03N Plastic

SL74HC03D SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

PIN 14 =VCC

PIN 7 = GND

FUNCTION TABLE

Inputs Output

A B Y

L L Z
L H Z

Z= High Impedance

H L Z
H H L

SLS

System Logic

SL74HC03

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±20 mA

I

DC Output Current, per Pin ±25 mA

OUT

ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipati on in Still Air, Plastic DIP+

SOIC Package+

750
500

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V

VCC =4.5 V
V

=6.0 V

CC

0
0
0

1000

500
400

mW

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.

System Logic

SLS