SLS SL4516BD, SL4516BN Datasheet

Semiconductor

Presettable Up/Down Counter

High-Voltage Silicon-Gate CMOS

The SL4516B Presettable Binary Up/Down Counter consists of four
synchronously clocked D-type flip-flops (with a gating structure to
provide T-type flip-flop capability) connected as counters. This
counter can be cleared by a high level on the RESET line, and can be
preset to any binary number present on the jam inputs by a high level
on the PRESET ENABLE line.

If the CARRY-IN input is held low, the counter advances up or
down on each positive-going clock transition. Synchronous cascading
is accomplished by connecting all clock inputs in parallel and
connecting the CARRY -OUT of a less significant stage to the CARRY­IN of a more significant stage.

The SL4516B can be cascaded in the ripple mode by connecting the
CARRY -OUT to the clock of the next stage. If the UP/DOWN input
changes during a terminal count, the CARRY-OUT must be gated with

the clock, and the UP/DOWN input must change while the clock
is high. This method provides a clean clock signal to the
subsequent counting stage.

• Operating Voltage Range: 3.0 to 18 V

• Maximum input current of 1 µA at 18 V over full package-

temperature range; 100 nA at 18 V and 25°C

• Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

SL4516B

ORDERING INFORMATION

SL4516BN Plastic

SL4516BD SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

SLS

LOGIC DIAGRAM

System Logic

PIN 16=VCC

PIN 8= GND

FUNCTION TABLE

Inputs Outputs

CL CI U/D PE R Mode

X H X L L NO COUNT

L H L L COUNT UP
L L L L COUNT

DOWN
X X X H L PRESET
X X X X H RESET

X = don’t care

SL4516B

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±10 mA
PD Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

PD Power Dissipation per Output Transistor 100 mW

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

750
500

260 °C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 3.0 18 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

mW

This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.

OUT

)≤VCC.

should be constrained to the range

OUT

System Logic

SLS