Sitronix ST7735R operation manual

ST

ST7735R

262K Color Single-Chip TFT Controller/Driver

1 Introduction

The ST7735R is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 396 source line and 162
gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial
Peripheral Interface (SPI), 8-bit/9-bit/16-bit/18-bit parallel interface. Display data can be stored in the on-chip display data
RAM of 132 x 162 x 18 bits. It can perform display data RAM read/write operation with no external operation clock to
minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal,
it is possible to make a display system with fewer components.

2 Features

Single chip TFT-LCD Controller/Driver with RAM
On-chip Display Data RAM (i.e. Frame Memory)

132 (H) x RGB x 162 (V) bits

LCD Driver Output Circuits:

Source Outputs: 132 RGB channels
Gate Outputs: 162 channels
Common electrode output

Display Colors (Color Mode)

Full Color: 262K, RGB=(666) max., Idle Mode OFF
Color Reduce: 8-color, RGB=(111), Idle Mode ON

Programmable Pixel Color Format (Color Depth) for
Various Display Data input Format

12-bit/pixel: RGB=(444) using the 384k-bit frame memory
and LUT
16-bit/pixel: RGB=(565) using the 384k-bit frame memory
and LUT
18-bit/pixel: RGB=(666) using the 384k-bit frame memory
and LUT

Various Interfaces

Parallel 8080-series MCU Interface
(8-bit, 9-bit, 16-bit & 18-bit)
Parallel 6800-series MCU Interface
(8-bit, 9-bit, 16-bit & 18-bit)
3-line serial interface
4-line serial interface

Display Features

Support both normal-black & normal-white LC
Software programmable color depth mode

Built-in Circuits

DC/DC converter
Adjustable VCOM generation
Non-volatile (NV) memory to store initial register setting
Oscillator for display clock generation
Factory default value (module ID, module version, etc) are
stored in NV memory
Timing controller

Built-in NV Memory for LCD Initial Register Setting

7-bits for ID2
8-bits for ID3
7-bits for VCOM adjustment

Wide Supply Voltage Range

I/O Voltage (VDDI to DGND): 1.65V~3.7V (VDDI ≤ VDD)
Analog Voltage (VDD to AGND): 2.3V~4.8V

On-Chip Power System

Source Voltage (GVDD to AGND): 3.0V~4.5V
VCOM level (VCOM to AGND): -0.4V to -2.0V
Gate driver HIGH level (VGH to AGND): +10.0V to +15V
Gate driver LOW level (VGL to AGND): -13V to -7.5V

Operating Temperature: -30°C to +85°C

ST7735R

Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.

Parallel Interface: 8080,6800(8-bit/9-bit/16-bit/18-bit)
Serial Interface: 3-line, 4-line

V0.2 1 2009-8-5

ST7735R

3 Pad arrangement

3.1 Output Bump Dimension

Boundary (Include scribe Lane)

C K

H

J

Item Symbol Size

Bump pitch A 16 um

Bump width C 16 um

Bump height H 98 um

Bump gap1 (Vertical) J 19 um

Bump gap2 (Horizontal) K 16 um

L

A

Bump area C x H 1568 um2

Chip Boundary (include scribe Lane) L 59 um

V0.2 2 2009-08-05

ST7735R

3.2 Input Bump Dimension

C2

H

Bump pitch 1 A1 67 um

Bump pitch 2 A2 50 um
Bump width 1 C1 33 um
Bump width 2 C2 38 um

Bump height H 88 um

Bump gap K 22 um

Bump gap1 K1 17 um

C2

K

Item Symbol Size

A1

K2

L

A2

K1 K1

Boundary (Include scribe Lane)

C1

Bump gap2 K2 34 um
Bump area 1 C1 X H 2904 um2
Bump area 2 C2 X H 3344 um2

Chip Boundary(include scribe Lane) L 59 um

V0.2 3 2009-08-05

ST7735R

3.3 Alignment Mark Dimension

10 5

80

20 1515 1515

20 1515 1515
80

80

105

2015 1515 15
80

2015 1515 15

V0.2 4 2009-08-05

ST7735R

No.1

No.185

No.186

No.759

3.4 Chip Information

Chip size (um x um): 10080 x 670
PAD coordinate: pad center
Coordinate origin: chip center
Chip thickness (um): 300(TYP)
Bump height (um): 15(TYP)
Bump hardness (HV): 75(TYP)

V0.2 5 2009-08-05

ST7735R

1

-

4750 -

231 51

-

2250 -

231 101

550 -

231

2

-

4700 -

231 52

-

2200 -

231 102

600 -

231

3

-

4650 -

231 53

-

2150 -

231 103

650 -

231

4

-

4600 -

231 54

-

2100 -

231 104

700 -

231

5

-

4550 -

231 55

-

2050 -

231 105

750 -

231

6

-

4500 -

231 56

-

2000 -

231 106

800 -

231

7

-

4450 -

231 57

-

1950 -

231 107

850 -

231

8

-

4400 -

231 58

-

1900 -

231 108

900 -

231

9

-

4350 -

231 59

-

1850 -

231 109

950 -

231

10

-

4300 -

231 60

-

1800 -

231 110

1000 -

231

11

-

4250 -

231 61

-

1750 -

231 111

1050 -

231

12

-

4200 -

231 62

-

1700 -

231 112

1100 -

231

13

-

4150 -

231 63

-

1630 -

231 113

1150 -

231

14

-

4100 -

231 64

-

1570 -

231 114

1200 -

231

15

-

4050 -

231 65

-

1510 -

231 115

1250 -

231

16

-

4000 -

231 66

-

1450 -

231 116

1300 -

231

17

-

3950 -

231 67

-

1390 -

231 117

1350 -

231

18

-

3900 -

231 68

-

1330 -

231 118

1400 -

231

19

-

3850 -

231 69

-

1270 -

231 119

1450 -

231

20

-

3800 -

231 70

-

1210 -

231 120

1500 -

231

21

-

3750 -

231 71

-

1150 -

231 121

1550 -

231

22

-

3700 -

231 72

-

1090 -

231 122

1600 -

231

23

-

3650 -231 73

-

1030 -

231 123

1650 -

231

24

-

3600 -

231 74

-

970 -

231 124

1700 -

231

25

-

3550 -

231 75

-

910 -

231 125

1750 -

231

26

-

3500 -

231 76

-

850 -

231 126

1800 -

231

27

-

3450 -

231 77

-

790 -

231 127

1850 -

231

28

-

3400 -

231 78

-

730 -

231 128

1900 -

231

29

-

3350 -

231 79

-

670 -

231 129

1950 -

231

30

-

3300 -

231 80

-

610 -

231 130

2000 -

231

31

-

3250 -

231 81

-

550 -

231 131

2050 -

231

32

-

3200 -

231 82

-

490 -

231 132

2100 -

231

33

-

3150 -

231 83

-

430 -

231 133

2150 -

231

34

-

3100 -

231 84

-

370 -

231 134

2200 -

231

35

-

3050 -

231 85

-

310 -

231 135

2250 -231

36

-

3000 -

231 86

-

250 -

231 136

2300 -

231

37

-

2950 -

231 87

-

190 -

231 137

2350 -

231

38

-

2900 -

231 88

-

130 -

231 138

2400 -

231

39

-

2850 -

231 89

-70 -231 139

2450 -

231

40

-

2800 -

231 90

0 -

231 140

2500 -

231

41

-

2750 -

231 91

50 -

231 141

2550 -

231

42

-

2700 -

231 92

100 -

231 142

2600 -

231

43

-

2650 -

231 93

150 -

231 143

2650 -

231

44

-

2600 -

231 94

200 -

231 144

2700 -

231

45

-

2550 -

231 95

250 -

231 145

2750 -

231

46

-

2500 -

231 96

300 -

231 146

2800 -

231

47

-

2450 -

231 97

350 -

231 147

2850 -

231

48

-

2400 -

231 98

400 -

231 148

2900 -

231

49

-

2350 -

231 99

450 -

231 149

2950 -

231

50

-

2300 -

231

100

500 -

231 150

3000 -

231

4 Pad Center Coordinates

No. PAD Name

Dummy
VDDIO
EXTC
DGNDO
IM[0]
VDDIO
IM[1]
DGNDO
P68
VDDIO
TEST1P
DGNDO
TEST2P
VDDIO
SRGB
DGNDO
SMX
VDDIO
SMY
DGNDO
Dummy
VDDIO
Dummy
DGNDO
Dummy
VDDIO
Dummy
DGNDO
Dummy
VDDIO
LCM
DGNDO
Dummy
VDDIO
Dummy
DGNDO
GM[1]
VDDIO
GM[0]
DGNDO
Dummy
GS
SPI4W
VDDIO
TESTOP[8]
TESTOP[7]
TESTOP[6]
TESTOP[5]
TESTOP[4]
OSC

X Y No. PAD Name

VDD
VDD
VDD
VDD
VDD
VDD
AGND
AGND
AGND
AGND
AGND
AGND
RDX
D_CX
TESEL
DGNDO
D[17]
D[16]
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[1]
D[3]
D[5]
D[7]
TE
RESX
CSX
D[6]
D[4]
D[2]
IM[2]
D[0]
WRX
Dummy
Dummy
Dummy
Dummy
TESTOP[3]
TESTOP[2]
TESTOP[1]
DGND
DGND
DGND
DGND

X Y

No. PAD Name

DGND
DGND
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VPP
VPP
VPP
GVDD
GVDD
GVDD
VCC
Dummy
Dummy
GVCL
Dummy
AVDD
AVDD
AVDD
AVDD
AVDD
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
AGND
AGND
AGND
AVCL
AVCL

X Y

V0.2 6 2009-08-05

ST7735R

151

3050 -

231

201

4532 227

251

3732 227

152

3100 -

231

202

4516 110

252

3716 110

153

3150 -

231

203

4500 227

253

3700 227

154

3200 -

231

204

4484 110

254

3684 110

155

3250 -

231

205

4468 227

255

3668 227

156

3300 -

231

206

4452 110

256

3652 110

157

3350 -

231

207

4436 227

257

3636 227

158

3400 -

231

208

4420 110

258

3620 110

159

3450 -

231

209

4404 227

259

3604 227

160

3500 -231

210

4388 110

260

3588 110

161

3550 -

231

211

4372 227

261

3572 227

162

3600 -

231

212

4356 110

262

3556 110

163

3650 -

231

213

4340 227

263

3540 227

164

3700 -

231

214

4324 110 264

3524 110

165

3750 -

231

215

4308 227

265

3508 227

166

3800 -

231

216

4292 110

266

3492 110

167

3850 -

231

217

4276 227

267

3476 227

168

3900 -

231

218

4260 110

268

3460 110

169

3950 -231

219

4244 227

269

3444 227

170

4000 -

231

220

4228 110

270

3428 110

171

4050 -

231

221

4212 227

271

3412 227

172

4100 -

231

222

4196 110

272

3396 110

173

4150 -

231

223

4180 227 273

3380 227

174

4200 -

231

224

4164 110

274

3364 110

175

4250 -

231

225

4148 227

275

3348 227

176

4300 -

231

226

4132 110

276

3332 110

177

4350 -

231

227

4116 227

277

3316 227

178

4400 -

231

228

4100 110

278

3300 110

179

4450 -

231

229

4084 227

279

3284 227

180

4500 -

231

230

4068 110

280

3268 110

181

4550 -

231

231

4052 227

281

3252 227

182

4600 -

231

232

4036 110

282

3236 110

183

4650 -

231

233

4020 227

283

3220 227

184

4700 -

231

234

4004 110

284

3204 110

185

4750 -

231

235

3988 227

285

3188 227

186

4772 110

236

3972 110

286

3172 110

187

4756 227

237

3956 227

287

3156 227

188

4740 110

238

3940 110

288

3140 110

189

4724 227

239

3924 227

289

3124 227

190

4708 110

240

3908 110

290

3108 110

191

4692 227

241

3892 227

291

3092 227

192

4676 110

242

3876 110

292

3076 110

193

4660 227

243

3860 227

293

3060 227

194

4644 110

244

3844 110

294

3044 110

195

4628 227

245

3828 227

295

3028 227

196

4612 110

246

3812 110

296

3012 110

197

4596 227

247

3796 227

297

2996 227

198

4580 110

248

3780 110

298

2980 110

199

4564 227

249

3764 227

299

2964 227

200

4548 110

250

3748 110 300

2948 110

No. PAD Name

AVCL
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
VGL
Dummy
Dummy
VGH
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
Dummy
VCOM
VCOM
VCOM
Dummy
Dummy
Dummy
G162
G160
G158
G156
G154
G152
G150
G148
G146
G144
G142
G140
G138

X Y

No. PAD Name

G136
G134
G132
G130
G128
G126
G124
G122
G120
G118
G116
G114
G112
G110
G108
G106
G104
G102
G100
G98
G96
G94
G92
G90
G88
G86
G84
G82
G80
G78
G76
G74
G72
G70
G68
G66
G64
G62
G60
G58
G56
G54
G52
G50
G48
G46
G44
G42
G40
G38

X Y

No. PAD Name

G36
G34
G32
G30
G28
G26
G24
G22
G20
G18
G16
G14
G12
G10
G8
G6
G4
G2
Dummy
Dummy
Dummy
Dummy
S396
S395
S394
S393
S392
S391
S390
S389
S388
S387
S386
S385
S384
S383
S382
S381
S380
S379
S378
S377
S376
S375
S374
S373
S372
S371
S370
S369

X Y

V0.2 7 2009-08-05

ST7735R

301

2932 227 351

2132 227

401

1332 227

302

2916 110 352

2116 110

402

1316 110

303

2900 227 353

2100 227

403

1300 227

304

2884 110 354

2084 110

404

1284 110

305

2868 227 355

2068 227

405

1268 227

306

2852 110 356

2052 110

406

1252 110

307

2836 227 357

2036 227

407

1236 227

308

2820 110 358

2020 110 408

1220 110

309

2804 227 359

2004 227

409

1204 227

310

2788 110 360

1988 110

410

1188 110

311

2772 227 361

1972 227

411

1172 227

312

2756 110 362

1956 110

412

1156 110

313

2740 227 363

1940 227

413

1140 227

314

2724 110 364

1924 110

414

1124 110

315

2708 227 365

1908 227

415

1108 227

316

2692 110

366

1892 110

416

1092 110

317

2676 227 367

1876 227

417

1076 227

318

2660 110 368

1860 110

418

1060 110

319

2644 227 369

1844 227

419

1044 227

320

2628 110 370

1828 110

420

1028 110

321

2612 227 371

1812 227

421

1012 227

322

2596 110 372

1796 110

422

996 110

323

2580 227 373

1780 227

423

980 227

324

2564 110 374

1764 110

424

964 110

325

2548 227 375

1748 227

425

948 227

326

2532 110 376

1732 110

426

932 110

327

2516 227 377

1716 227

427

916 227

328

2500 110 378

1700 110

428

900 110

329

2484 227 379

1684 227

429

884 227

330

2468 110 380

1668 110

430

868 110

331

2452

227 381

1652 227

431

852 227

332

2436 110 382

1636 110

432

836 110

333

2420 227 383

1620 227

433

820 227

334

2404 110 384

1604 110

434

804 110

335

2388 227 385

1588 227

435

788 227

336

2372 110 386

1572 110

436

772 110

337

2356 227 387

1556 227

437

756 227

338

2340 110 388

1540 110

438

740 110

339

2324 227 389

1524 227

439

724 227

340

2308 110 390

1508 110

440

708 110

341

2292 227

391

1492 227

441

692 227

342

2276 110

392

1476 110

442

676 110

343

2260 227

393

1460 227

443

660 227

344

2244 110

394

1444 110

444

644 110

345

2228 227

395

1428 227

445

628 227

346

2212 110

396

1412 110

446

612 110

347

2196 227

397

1396 227

447

596 227

348

2180 110

398

1380 110

448

580 110

349

2164 227

399

1364 227

449

564 227

350

2148 110

400

1348 110

450

548 110

No. PAD Name

S368
S367
S366
S365
S364
S363
S362
S361
S360
S359
S358
S357
S356
S355
S354
S353
S352
S351
S350
S349
S348
S347
S346
S345
S344
S343
S342
S341
S340
S339
S338
S337
S336
S335
S334
S333
S332
S331
S330
S329
S328
S327
S326
S325
S324
S323
S322
S321
S320
S319

X Y No. PAD Name

S318
S317
S316
S315
S314
S313
S312
S311
S310
S309
S308
S307
S306
S305
S304
S303
S302
S301
S300
S299
S298
S297
S296
S295
S294
S293
S292
S291
S290
S289
S288
S287
S286
S285
S284
S283
S282
S281
S280
S279
S278
S277
S276
S275
S274
S273
S272
S271
S270
S269

X Y

No. PAD Name

S268
S267
S266
S265
S264
S263
S262
S261
S260
S259
S258
S257
S256
S255
S254
S253
S252
S251
S250
S249
S248
S247
S246
S245
S244
S243
S242
S241
S240
S239
S238
S237
S236
S235
S234
S233
S232
S231
S230
S229
S228
S227
S226
S225
S224
S223
S222
S221
S220
S219

X Y

V0.2 8 2009-08-05

ST7735R

451

532 227

501

-

644 110

551

-

1444 110

452

516 110

502

-

660 227

552

-

1460 227

453

500 227

503

-

676 110

553

-

1476 110

454

484 110

504

-

692 227

554

-

1492 227

455

468 227

505

-

708 110

555

-

1508 110

456

452 110

506

-

724 227

556

-

1524 227

457

436 227

507

-740 110

557

-

1540 110

458

420 110

508

-

756 227

558

-

1556 227

459

404 227

509

-

772 110

559

-

1572 110

460

388 110

510

-

788 227

560

-

1588 227

461

372 227

511

-

804 110

561

-

1604 110

462

356 110

512

-

820 227

562

-

1620 227

463

340 227

513

-

836 110

563

-

1636 110

464

324 110

514

-

852 227

564

-

1652 227

465

308 227

515

-

868 110

565

-

1668 110

466

292 110

516

-

884 227

566

-

1684 227

467

276 227

517

-

900 110

567

-

1700 110

468

260 110

518

-

916 227

568

-

1716 227

469

244 227

519

-

932 110

569

-

1732 110

470

228 110

520

-

948 227

570

-

1748 227

471

212 227

521

-

964 110

571

-

1764 110

472

196 110

522

-

980 227

572

-

1780 227

473

-

196 110

523

-

996 110

573

-

1796 110

474

-

212 227

524

-

1012 227

574

-

1812 227

475

-

228 110 525

-

1028 110

575

-

1828 110

476

-

244 227

526

-

1044 227

576

-

1844 227

477

-

260 110

527

-

1060 110

577

-

1860 110

478

-

276 227

528

-

1076 227

578

-

1876 227

479

-

292 110

529

-

1092 110

579

-

1892 110

480

-

308 227

530

-

1108 227

580

-

1908 227

481

-

324 110

531

-

1124 110

581

-

1924 110

482

-

340 227

532

-

1140 227

582

-

1940 227

483

-

356 110

533

-

1156 110

583

-

1956 110

484

-372 227

534

-

1172 227

584

-

1972 227

485

-

388 110

535

-

1188 110

585

-

1988 110

486

-

404 227

536

-

1204 227

586

-

2004 227

487

-

420 110

537

-

1220 110

587

-

2020 110

488

-

436 227

538

-

1236 227 588

-

2036 227

489

-

452 110

539

-

1252 110

589

-

2052 110

490

-

468 227

540

-

1268 227

590

-

2068 227

491

-

484 110

541

-

1284 110

591

-

2084 110

492

-

500 227

542

-

1300 227

592

-

2100 227

493

-

516 110

543

-

1316 110

593

-

2116 110

494

-

532 227

544

-

1332 227

594

-

2132 227

495

-

548 110

545

-

1348 110

595

-

2148 110

496

-

564 227

546

-

1364 227

596

-

2164 227

497

-

580 110

547

-

1380 110

597

-

2180 110

498

-

596 227

548

-

1396 227

598

-

2196 227

499

-

612 110

549

-

1412 110

599

-

2212 110

500

-

628 227

550

-

1428 227

600

-

2228 227

No. PAD Name

S218
S217
S216
S215
S214
S213
S212
S211
S210
S209
S208
S207
S206
S205
S204
S203
S202
S201
S200
S199
Dummy
Dummy
Dummy
Dummy
S198
S197
S196
S195
S194
S193
S192
S191
S190
S189
S188
S187
S186
S185
S184
S183
S182
S181
S180
S179
S178
S177
S176
S175
S174
S173

X Y No. PAD Name

S172
S171
S170
S169
S168
S167
S166
S165
S164
S163
S162
S161
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S140
S139
S138
S137
S136
S135
S134
S133
S132
S131
S130
S129
S128
S127
S126
S125
S124
S123

X Y

No. PAD Name

S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73

X Y

V0.2 9 2009-08-05

ST7735R

601

-

2244 110

651

-

3044 110

701

-

3844 110

602

-

2260 227

652

-

3060 227

702

-

3860 227

603

-

2276 110

653

-

3076 110

703

-

3876 110

604

-

2292 227

654

-

3092 227

704

-

3892 227

605

-

2308 110 655

-

3108 110

705

-

3908 110

606

-

2324 227

656

-

3124 227

706

-

3924 227

607

-

2340 110

657

-

3140 110

707

-

3940 110

608

-

2356 227

658

-

3156 227

708

-

3956 227

609

-

2372 110

659

-

3172 110

709

-3972 110

610

-

2388 227

660

-

3188 227

710

-

3988 227

611

-

2404 110

661

-

3204 110

711

-

4004 110

612

-

2420 227

662

-

3220 227

712

-

4020 227

613

-

2436 110

663

-

3236 110

713

-

4036 110

614

-

2452 227

664

-

3252 227

714

-

4052 227

615

-

2468 110

665

-

3268 110

715

-

4068 110

616

-

2484 227

666

-

3284 227

716

-

4084 227

617

-

2500 110

667

-

3300 110

717

-

4100 110

618

-

2516 227

668

-

3316 227

718

-

4116 227

619

-

2532 110

669

-

3332 110

719

-

4132 110

620

-

2548 227

670

-

3348 227

720

-

4148 227

621

-

2564 110

671

-

3364 110

721

-

4164 110

622

-

2580 227

672

-

3380 227

722

-

4180 227

623

-

2596 110

673

-

3396 110

723

-

4196 110

624

-

2612 227

674

-

3412 227

724

-

4212 227

625

-

2628 110

675

-

3428 110

725

-

4228 110

626

-

2644 227

676

-

3444 227

726

-

4244 227

627

-

2660 110

677

-

3460 110

727

-

4260 110

628

-

2676 227

678

-

3476 227

728

-

4276 227

629

-

2692 110

679

-

3492 110

729

-

4292 110

630

-

2708 227

680

-

3508 227

730

-

4308 227

631

-

2724 110

681

-

3524 110

731

-

4324 110

632

-

2740 227

682

-

3540 227

732

-

4340 227

633

-

2756 110

683

-

3556 110

733

-

4356 110

634

-

2772 227

684

-

3572 227

734

-

4372 227

635

-

2788 110

685

-

3588 110

735

-

4388 110

636

-

2804 227

686

-

3604 227

736

-

4404 227

637

-

2820 110

687

-

3620 110

737

-

4420 110

638

-

2836 227

688

-

3636 227

738

-

4436 227

639

-

2852 110

689

-

3652 110

739

-

4452 110

640

-

2868 227

690

-

3668 227

740

-

4468 227

641

-

2884 110

691

-

3684 110

741

-

4484 110

642

-

2900 227

692

-

3700 227

742

-

4500 227

643

-

2916 110

693

-

3716 110

743

-

4516 110

644

-

2932 227

694

-

3732 227

744

-

4532 227

645

-

2948 110

695

-

3748 110

745

-

4548 110

646

-

2964 227

696

-

3764 227

746

-

4564 227

647

-

2980 110

697

-

3780 110

747

-

4580 110

648

-

2996 227

698

-

3796 227

748

-

4596 227

649

-

3012 110

699

-

3812 110

749

-

4612 110

650

-

3028 227

700

-

3828 227

750

-

4628 227

No. PAD Name

S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23

X Y No. PAD Name

S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
Dummy
Dummy
Dummy
Dummy
G1
G3
G5
G7
G9
G11
G13
G15
G17
G19
G21
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47

X Y

No. PAD Name

G49
G51
G53
G55
G57
G59
G61
G63
G65
G67
G69
G71
G73
G75
G77
G79
G81
G83
G85
G87
G89
G91
G93
G95
G97
G99
G101
G103
G105
G107
G109
G111
G113
G115
G117
G119
G121
G123
G125
G127
G129
G131
G133
G135
G137
G139
G141
G143
G145
G147

X Y

V0.2 10 2009-08-05

ST7735R

751

-

4644 110

752

-

4660 227

753

-

4676 110

754

-

4692 227

755

-

4708 110

756

-

4724 227

757

-

4740 110

758

-

4756 227

759

-4772 110

ALIGNMENT_R

4841 -

220

ALIGNMENT_

L -

4841 -

220

No. PAD Name X Y

G149
G151
G153
G155
G157
G159
G161
Dummy
Dummy

V0.2 11 2009-08-05

ST7735R

5 Block diagram

396 Source Buffer

DAC

Level Shifter

GVCL

GVDD

Voltage

Reference

Gamma Circuit

162 Gate Buffer

Level Shifter

Gate

Decoder

Data Latch

Display Ram

132 x 162 x 18 bits

Color conversion

LUT table

Instruction

Register

MCU IF

Gamma Table

Display control

NVM

Vcom generator

OSC

Booster 1/2/4

VCOM

TESEL

SDA

D[17:0]

SRGB

WRX (R/WX)

GS

LCM

RDX (E)

CSX

DC/X (SCL)

SMX

SMY

EXTC

IM [2:0]

AVDD

VDDI

VGH

VGL

VDD

AVCL

V0.2 12 2009-08-05

ST7735R

6 Driver IC Pin Description

6.1 Power Supply Pin
Name

VDD I Power supply for analog, digital system and booster circuit. VDD

VDDI I Power supply for I/O system. VDDI
AGND
DGND

6.2 Interface logic pin
Name I/O Description Connect pin

P68 I

IM2 I

I/O Description Connect pin

I System ground for analog system and booster circuit. GND
I System ground for I/O system and digital system. GND

-8080/6800 MCU interface mode select.

-P68=’1’, select 6800 MCU parallel interface.

-P68=’0’, select 8080 MCU parallel interface.

-If not used, please fix this pin at DGND level.
MCU Parallel interface bus and Serial interface select
IM2=’1’, Parallel interface
IM2=’0’, Serial interface

- MCU parallel interface type selection

-If not used, please fix this pin at VDDI or DGND level.

DGND/VDDI

DGND/VDDI

IM1,IM0

SPI4W

RESX I

CSX I

D/CX

(SCL)

IM1 IM0 Parallel interface

I

I

I

0 0 MCU 8-bit parallel
0 1 MCU 16-bit parallel
1 0 MCU 9-bit parallel
1 1 MCU 18-bit parallel

- SPI4W=’0’, 3-line SPI enable.

- SPI4W=’1’, 4-line SPI enable.

-If not used, please fix this pin at DGND level.

-This signal will reset the device and it must be applied to properly
initialize the chip.

-Signal is active low.

-Chip selection pin

-Low enable.

-Display data/command selection pin in MCU interface.

-D/CX=’1’: display data or parameter.

-D/CX=’0’: command data.

-In serial interface, this is used as SCL.

DGND/VDDI

DGND/VDDI

MCU

MCU

MCU

-If not used, please fix this pin at VDDI or DGND level.

RDX I

V0.2 13 2009-08-05

-Read enable in 8080 MCU parallel interface.

-If not used, please fix this pin at VDDI or DGND level.

MCU

ST7735R

WRX

(D/CX)

D[17:0] I/O

TE O

OSC O

Note1. When in parallel mode, no use data pin must be connected to “1” or “0”.
Note2. When CSX=”1”, there is no influence to the parallel and serial interface.

-Write enable in MCU parallel interface.

I

-In 4-line SPI, this pin is used as D/CX (data/ command selection).

-If not used, please fix this pin at VDDI or DGND level.

-D[17:0] are used as MCU parallel interface data bus.

-D0 is the serial input/output signal in serial interface mode.

-In serial interface, D[17:1] are not used and should be fixed at VDDI or
DGND level.

-Tearing effect output pin to synchronies MCU to frame rate, activated
by S/W command.

-If not used, please open this pin.

-Monitoring pin of internal oscillator clock and is turned ON/OFF by
S/W command.

-When this pin is inactive (function OFF), this pin is DGND level.

-If not used, please open this pin.

MCU

MCU

MCU

-

V0.2 14 2009-08-05

ST7735R

6.3 Mode selection pin

Name

EXTC

GM1,

GM0

SRGB

I/O Description Connect pin

-During normal operation, please open this pin.
EXTC Enable/disable modification of extend command

I

I

I

0 Normal operation mode
1 Use NVM command set

-Panel resolution selection pins.

G

G

M

M

1

0
0 0
1 1

-RGB direction select H/W pin for color filter setting.
SRGB RGB arrangement

0
1

132RGB x 162 (S1~S396 & G1~G162 output)
128RGB x 160 (S7~S390 & G2~G161 output)

Selection of panel resolution

S1, S2, S3 filter order = ’R’, ’G’, ’B’
S1, S2, S3 filter order = ‘B’, ‘G’, ‘R’

Open

VDDI/DGND

VDDI/DGND

SMX I

SMY I

LCM I

-Module source output direction H/W selection pin.

SMX Scanning direction of source output

GM= ‘00’ GM= ‘11’
0 S1 -> S396 S7 -> S390
1 S396 -> S1 S390 -> S7

-Module Gate output direction H/W selection pin.
SMY Scanning direction of gate output

GM= ‘00’ GM= ‘11’
0 G1 -> G162 G2 -> G161
1 G162 -> G1 G161 -> G2

-Liquid crystal (LC) type selection pins.
LCM Selection of LC type

0 Normally white LC type
1 Normally black LC type

VDDI/DGND

VDDI/DGND

VDDI/DGND

-Gamma curve selection pin.

GS Selection of gamma curve

GS I

V0.2 15 2009-08-05

0 GC0=1.0, GC1=2.5, GC2=2.2, GC3=1.8
1 GC0=2.2, GC1=1.8, GC2=2.5, GC3=1.0

VDDI/DGND

ST7735R

VPP I When writing NVM, it needs external power supply voltage (7.5V).

Input pin to select horizontal line number in TE signal.
This pin is only for GM[1:0]=’00’ mode

TESEL

6.4 Driver output pins
Name I/O

S1 to S396 O - Source driver output pins. -

G1 to G162 O - Gate driver output pins. -

AVDD O

AVCL O

I

TESEL

0 TE output 162 lines
1 TE output 160 lines

Power pin for analog circuits.
Connect a capacitor for stabilization.

- A power supply pin for generating GVCL.

- Connect a capacitor for stabilization.

Selection of gamma curve

Description

VDDI/DGND

Connect pin

Capacitor

Capacitor

VGH O - Power output pin for gate driver

VGL O - Power output (Negative) pin for gate driver

- A power output of grayscale voltage generator.

GVDD O

GVCL O

VCOM O - A power supply for the TFT-LCD common electrode.

VCC O

VDDIO O - VDDI voltage output level for monitoring. -

DGNDO O - DGND voltage output level for monitoring. -

- When internal GVDD generator is not used, connect an external
power supply (AVDD-0.5V) to this pin.

- A power output(Negative) of grayscale voltage generator.

- When internal GVCL generator is not used, connect an external
power supply (AVCL+0.5V) to this pin.

- Monitoring pin of internal digital reference voltage.

- Please open these pins.

-

Common
electrode

V0.2 16 2009-08-05

ST7735R

6.5 Test pins
Name I/O

TEST2P

TEST1P
TESTOP[8]
TESTOP[7]
TESTOP[6]
TESTOP[5]
TESTOP[4]
TESTOP[3]
TESTOP[2]
TESTOP[1]

Dummy -

Description Connect pin

-These test pins for Driver vender test used.

I

-Please connect these pins to DGND.

-These test pins for Driver vender test used.

O

-Please open these pins.

-These pins are dummy (have no function inside).

-Can allow signal traces pass through these pads on TFT glass.

-Please open these pins.

DGND

Open

Open

V0.2 17 2009-08-05

ST7735R

7 Driver electrical characteristics

7.1 Absolute operation range
Item Symbol Rating Unit

Supply voltage VDD - 0.3 ~ +4.6 V

Supply voltage (Logic) VDDI - 0.3 ~ +4.6 V

Supply voltage (Digital) VCC -0.3 ~ +1.95 V

Driver supply voltage VGH-VGL -0.3 ~ +30.0 V

Logic input voltage range VIN 0.3 ~ VDDI + 0.3 V

Logic output voltage range VO 0.3 ~ VDDI + 0.3 V

Operating temperature range TOPR -30 ~ +85

Storage temperature range TSTG -40 ~ +125

Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be degraded. Absolute

maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the
product within the recommend range.

℃
℃

V0.2 18 2009-08-05

ST7735R

7.2 DC characteristic

Parameter

System voltage VDD Operating voltage

Interface operation

voltage

Gate driver high voltage VGH 10 15 V

Gate driver low voltage VGL -12.4 -7.5 V

Gate driver supply voltage

Logic-high input voltage VIH 0.7VDDI

Logic-low input voltage VIL VSS 0.3VDDI

Logic-high output voltage VOH IOH = -1.0mA 0.8VDDI

Logic-low output voltage VOL IOL = +1.0mA VSS 0.2VDDI

Logic-high input current IIH VIN = VDDI 1 uA

Logic-low input current IIL VIN = VSS -1 uA

Symbo

Condition

l

Power & operation voltage

VDDI I/O supply voltage

| VGH-VGL | 17.5 27.5 V

Input / Output

Specification

Min Typ Max

2.3 2.75 4.8 V

1.65 1.8 3.7 V

VDDI V Note 1

VDDI V Note 1

Unit Related

V Note 1

V Note 1

Pins

Note 1
Note 1

Input leakage current IIL IOH = -1.0mA -0.1 +0.1 uA

VCOM voltage

VCOM amplitude VCOM

Source output range Vsout

Gamma reference voltage GVDD

Source output settling

Tr

time

Output offset voltage Voffset

Notes:

1. TA= -30 to 85℃.

2. Source channel loading= 2KΩ+12pF/channel, Gate channel loading=5KΩ+40pF/channel.

3. The Max. value is between measured point of source output and gamma setting value.

Below with 99%

-2 -0.425 V
Source driver

0.1 GVDD V

3.0 5.0 V

20 us Note 2

precision

35 mV

Note 1

Note 3

V0.2 19 2009-08-05

ST7735R

7.3 Power consumption

Ta=25℃, Frame rate = 60Hz, the registers setting are IC default setting.

Current consumption

Operation mode Image

Typical Maximum

IDDI

(mA)

Note 1

TBD TBD TBD TBD

Normal mode

Note 2
Note 1

TBD TBD TBD TBD
TBD TBD TBD TBD

Partial + Idle mode (40 lines)

Note 2

TBD TBD TBD TBD

Sleep-in mode N/A TBD TBD TBD TBD

Notes:

1. All pixels black.

2. All pixels white.

3. The Current Consumption is DC characteristics of ST7735R.

4. Typical: VDDI=1.8V, VDD=2.75V; Maximum: VDDI=1.65 to 3.7V, VDD=2.3 to 4.8V

IDD

(mA)

IDDI

(mA)

IDD

(mA)

V0.2 20 2009-08-05

ST7735R

8 Timing chart

8.1 Parallel interface characteristics: 18, 16, 9 or 8-bit bus (8080 series MCU interface)

Figure 8.1.1 Parallel interface timing characteristics (8080 series MCU interface)
Ta=25 ℃, VDDI=1.65~3.7V, VDD=2.3~4.8V

Signal Symbol Parameter Min Max Unit Description
D/CX

CSX

WRX

RDX (ID)

RDX (FM)

D[17:0]

TAST Address setup time 10 ns
TAHT Address hold time (Write/Read) 10 ns
TCHW Chip select “H” pulse width 0 ns
TCS Chip select setup time (Write) 15 ns
TRCS Chip select setup time (Read ID) 45 ns
TRCSFM Chip select setup time (Read FM) 355 ns
TCSF Chip select wait time (Write/Read) 10 ns
TCSH Chip select hold time 10 ns
TWC Write cycle 66 ns
TWRH Control pulse “H” duration 15 ns
TWRL Control pulse “L” duration 15 ns
TRC Read cycle (ID) 160 ns
TRDH Control pulse “H” duration (ID) 90 ns
TRDL Control pulse “L” duration (ID) 45 ns
TRCFM Read cycle (FM) 450 ns
TRDHFM Control pulse “H” duration (FM) 90 ns
TRDLFM Control pulse “L” duration (FM) 355 ns
TDST Data setup time 10 ns
TDHT Data hold time 10 ns
TRAT Read access time (ID) 40 ns
TRATFM Read access time (FM) 340 ns
TODH Output disable time 20 80 ns

-

-

When read ID data

When read from frame
memory

For CL=30pF

Table 8.1.1 8080 parallel Interface Characteristics

V0.2 21 2009-08-05

ST7735R

8.1.2 Rising and falling timing for input and output signal

Figure 8.1.3 Chip selection (CSX) timing

Figure

Figure 8.1.4 Write-to-read and read-to-write timing

Note: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%

and 70% of VDDI for Input signals.

V0.2 22 2009-08-05

ST7735R

8.2 Parallel interface characteristics: 18, 16, 9 or 8-bit bus (6800 series MCU interface)

Figure 8.2.1Parallel interface timing characteristics (6800-series MCU interface)
Ta=25 ℃, VDDI=1.65~3.7V, VDD=2.3~4.8V

Signal Symbol Parameter Min Max Unit Description

T

Address setup time 10 ns

D/CX

AST

T

Address hold time (Write/Read) 10 ns

AHT

T

Chip select “H” pulse width 0 ns

CHW

-

TCS Chip select setup time (Write) 15 ns
T

Chip select setup time (Read ID) 45 ns

CSX

RCS

T

Chip select setup time (Read FM) 355 ns

RCSFM

T

Chip select wait time (Write/Read) 10 ns

CSF

T

Chip select hold time 10 ns

CSH

-

TWC Write cycle 66 ns

WRX

T

Control pulse “H” duration 15 ns

WRH

T

Control pulse “L” duration 15 ns

WRL

TRC Read cycle (ID) 160 ns

RDX (ID)

RDX (FM)

D[17:0]

T

Control pulse “H” duration (ID) 90 ns

RDH

T

Control pulse “L” duration (ID) 45 ns

RDL

T

Read cycle (FM) 450 ns

RCFM

T

Control pulse “H” duration (FM) 90 ns

RDHFM

T

Control pulse “L” duration (FM) 355 ns

RDLFM

T

Data setup time 10 ns

DST

T

Data hold time 10 ns

DHT

T

Output disable time 20 80 ns

ODH

When read ID data

When read from frame
memory

For maximum CL=30pF
For minimum CL=8pF

Table 8.2.1 6800 parallel Interface Characteristics

Note: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%

and 70% of VDDI for Input signals.

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8.3 Serial interface characteristics (3-line serial)

V

CSX

SCL

IH

V

IL

T

T

CSS

SCYCW/TSCYCR

T

SHW/TSHR

T

SLW/TSLR

T

CHW

T

CSH

T

V

SCC

IH

V

IL

SDA

SDA

(DOUT)

T

SDS

V

IH

V

IL

T

SDH

V

T

ACC

T

OH

V

IH

V

IL

IH

V

IL

Figure 8.3.1 3-line serial interface timing
Ta=25 ℃, VDDI=1.65~3.7V, VDD=2.3~4.8V

Signal Symbol Parameter Min Max Unit Description

TCSS Chip select setup time (write) 15 ns
TCSH Chip select hold time (write) 15 ns

CSX

TCSS Chip select setup time (read) 60 ns
TSCC Chip select hold time (read) 65 ns
TCHW Chip select “H” pulse width 40 ns
TSCYCW Serial clock cycle (Write) 66 ns
TSHW SCL “H” pulse width (Write) 15 ns

SCL

TSLW SCL “L” pulse width (Write) 15 ns
TSCYCR Serial clock cycle (Read) 150 ns
TSHR SCL “H” pulse width (Read) 60 ns
TSLR SCL “L” pulse width (Read) 60 ns

SDA
(DIN)
(DOUT)

TSDS Data setup time 10 ns
TSDH Data hold time 10 ns
TACC Access time 10 50 ns
TOH Output disable time 15 50 ns

For maximum CL=30pF
For minimum CL=8pF

Table 8.3.1 3-line Serial Interface Characteristics

Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%

and 70% of VDDI for Input signals.

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8.4 Serial interface characteristics (4-line serial)

Figure 8.4.1 4-line serial interface timing
Ta=25 ℃, VDDI=1.65~3.7V, VDD=2.3~4.8V

Signal Symbol Parameter MIN MAX Unit Description

TCSS Chip select setup time (write) 45 ns
TCSH Chip select hold time (write) 45 ns

CSX

SCL

D/CX

SDA
(DIN)
(DOUT)

TCSS Chip select setup time (read) 60 ns
TSCC Chip select hold time (read) 65 ns
TCHW Chip select “H” pulse width 40 ns
TSCYCW Serial clock cycle (Write) 66 ns
TSHW SCL “H” pulse width (Write) 15 ns
TSLW SCL “L” pulse width (Write) 15 ns
TSCYCR Serial clock cycle (Read) 150 ns
TSHR SCL “H” pulse width (Read) 60 ns
TSLR SCL “L” pulse width (Read) 60 ns
TDCS D/CX setup time 10 ns
TDCH D/CX hold time 10 ns
TSDS Data setup time 10 ns
TSDH Data hold time 10 ns
TACC Access time 10 50 ns
TOH Output disable time 15 50 ns

-write command & data
ram

-read command & data
ram

For maximum CL=30pF
For minimum CL=8pF

Table 8.4.1 4-line Serial Interface Characteristics

Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%

and 70% of VDDI for Input signals.

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9 Function description

9.1 Interface type selection

The selection of given interfaces are done by setting IM2, IM1, and IM0 pins as shown in following table.

P68 IM2 IM1 IM0 Interface Read back selection

- 0 - - 3-line serial interface Via the read instruction
0 1 0 0 8080 MCU 8-bit parallel RDX strobe (8-bit read data and 8-bit read parameter)
0 1 0 1 8080 MCU 16-bit parallel RDX strobe (16-bit read data and 8-bit read parameter)
0 1 1 0 8080 MCU 9-bit parallel RDX strobe (9-bit read data and 8-bit read parameter)
0 1 1 1 8080 MCU 18-bit parallel RDX strobe (18-bit read data and 8-bit read parameter)

- 0 - - 3-line serial interface Via the read instruction
1 1 0 0 6800 MCU 8-bit parallel E strobe (8-bit read data and 8-bit read parameter)
1 1 0 1 6800 MCU 16-bit parallel E strobe (16-bit read data and 8-bit read parameter)
1 1 1 0 6800 MCU 9-bit parallel E strobe (9-bit read data and 8-bit read parameter)
1 1 1 1 6800 MCU 18-bit parallel E strobe (18-bit read data and 8-bit read parameter)

Table 9.1.1 Selection of MCU interface

P68 IM2 IM1 IM0 Interface RDX WRX D/CX Read back selection

- 0 - - 3-line serial interface Note1 Note1 SCL D[17:1]: unused, D0: SDA
0 1 0 0 8080 8-bit parallel RDX WRX D/CX D[17:8]: unused, D7-D0: 8-bit data

0 1 0 1 8080 16-bit parallel RDX WRX D/CX
0 1 1 0 8080 9-bit parallel RDX WRX D/CX D[17:9]: unused, D8-D0: 9-bit data

0 1 1 1 8080 18-bit parallel RDX WRX D/CX D17-D0: 18-bit data

- 0 - - 3-line serial interface Note1 D/CX SCL D[17:1]: unused, D0: SDA
1 1 0 0 6800 8-bit parallel E WRX RS D[17:8]: unused, D7-D0: 8-bit data

1 1 0 1 6800 16-bit parallel E WRX RS
1 1 1 0 6800 9-bit parallel E WRX RS D[17:9]: unused, D8-D0: 9-bit data

1 1 1 1 6800 18-bit parallel E WRX RS D17-D0: 18-bit data

Table 9.1.2 Pin connection according to various MCU interface

D[17:16]: unused, D15-D0: 16-bit
data

D[17:16]: unused, D15-D0: 16-bit
data

Note: Unused pins can be open, or connected to DGND or VDDI.

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9.2 8080-series MCU parallel interface (P68 = ‘0’)

The MCU can use one of following interfaces: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface,
19-line with 16-data parallel interface or 21-lines with 18-data parallel interface. The chip-select CSX (active low)
enables/disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write enable,
RDX is the parallel data read enable and D[17:0] is parallel data bus.

The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX=’1’,
D[17:0] bits is either display data or command parameter. When D/C=’0’, D[17:0] bits is command. The interface functions
of 8080-series parallel interface are given in following table.

IM2 IM1 IM0 Interface D/CX RDX WRX

0 1 ↑ Write 8-bit command (D7 to D0)

1 0 0

1 0 1

1 1 0

1 1 1

8-bit

parallel

16-bit

parallel

9-bit

parallel

18-bit

parallel

1 1 ↑ Write 8-bit display data or 8-bit parameter (D7 to D0)
1 ↑ 1 Read 8-bit display data (D7 to D0)
1 ↑ 1 Read 8-bit parameter or status (D7 to D0)
0 1 ↑ Write 8-bit command (D7 to D0)
1 1 ↑ Write 16-bit display data or 8-bit parameter (D15 to D0)
1 ↑ 1 Read 16-bit display data (D15 to D0)
1 ↑ 1 Read 8-bit parameter or status (D7 to D0)
0 1 ↑ Write 8-bit command (D7 to D0)
1 1 ↑ Write 9-bit display data or 8-bit parameter (D8 to D0)
1 ↑ 1 Read 9-bit display data (D8 to D0)
1 ↑ 1 Read 8-bit parameter or status (D7 to D0)
0 1 ↑ Write 8-bit command (D7 to D0)
1 1 ↑ Write 18-bit display data or 8-bit parameter (D17 to D0)
1 ↑ 1 Read 18-bit display data (D17 to D0)
1 ↑ 1 Read 8-bit parameter or status (D7 to D0)

Read back selection

Table 9.2.1 the function of 8080-series parallel interface

Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh

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9.2.1 Write cycle sequence

The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write
cycle (WRX high-low-high sequence) consists of 3 control signals (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit
is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is
low (=’0’) and vice versa it is data (=’1’).

WRX

D[17:0]

The host starts to control D[17:0]
lines when there is a falling edge
of the WRX.

Figure 9.2.1 8080-series WRX protocol

Note: WRX is an unsynchronized signal (It can be stopped).

D[17:0]

RESX

CSX

D/CX

RDX

WRX

1-byte

command

CMD CMD PA1 CMD PA

S P

“1”

“1”

2-byte

command

The display writes D[17:0] lines
when there is a rising edge of
WRX.

N-byte

command

1

The host stops to
control D[17:0] lines.

PA

PA

N-2

N-1

D[17:0]

Host D[17:0]
Host to LCD

Driver D[17:0]

CMD CMD PA1 CMD PA

S P

CMD CMD PA1 CMD PA

S P

Hi-Z

1

1

PA

PA

PA

N-2

N-2

PA

N-1

N-1

LCD to Host

CMD: write command code
PA: parameter or display data

Signals on D[17:0], D/CX, R/WX, E
pins during CSX=1 are ignored.

Figure 9.2.2 8080-series parallel bus protocol, write to register or display RAM

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9.2.2 Read cycle sequence

The read cycle (RDX high-low-high sequence) means that the host reads information from LCD driver via interface. The
driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising
edge of RDX.

Figure 9.2.3 8080-series RDX protocol

Note: RDX is an unsynchronized signal (It can be stopped).

Read parameter Read display data

D[17:0]

RESX

CSX

D/CX

RDX

WRX

D[17:0]

Host D[17:0]

Host to LCD

Driver D[17:0]

LCD to Host

CMD DM PA CMD DM & data Data DataS P

“1”

CMD DM PA CMD DM & data Data DataS P

CMD CMDS P

Hi-Z

CMD: write command code
PA: parameter or display data

Hi-Z Hi-Z

DM PA1 DM & data PA

Hi-Z

Signals on D[17:0], D/CX, R/WX, E
pins during CSX=1 are ignored.

PA

N-2

PS

N-1

Figure 9.2.4 8080-series parallel bus protocol, read data from register or display RAM

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9.3 6800-series MCU parallel interface (P68 = ‘1’)

The MCU uses one of following interface: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface,
19-lines with 16-data parallel interface, or 21-lines with 18-data parallel interface. The chip-select CSX(active low) enables
and disables the parallel interface. RESX (active low) is an external reset signal. The R/WX is the Read/Write flag and
D[17:0] is parallel data bus.

The LCD driver reads the data at the falling edge of E signal when R/WX= ‘1’ and Writes the data at the falling of the E
signal when R/WX=’0’. The D/CX is the data/command flag. When D/CX=’1’, D[17:0] bits are display RAM data or
command parameters. When D/C= ‘0’, D[17:0] bits are commands.

The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver. The
selection of this interface is done when P68 pin is high state (VDDI). Interface bus width can be selected with IM2, IM1 and
IM0.The interface functions of 6800-series parallel interface are given in Table 8.1.1.

P68 IM2 IM1 IM0 Interface D/CX R/WX E Function

0 0 ↓ Write 8-bit command (D7 to D0)

1 1 0 0 8-bit Parallel

1 1 0 1 16-bit Parallel

1 1 1 0 9-bit Parallel

1 1 1 1 18-bit Parallel

1 0 ↓ Write 8-bit display data or 8-bit parameter (D7 to D0)
1 1 ↓ Read 8-bit Display data (D7 to D0)
1 1 ↓ Read 8-bit parameter or status (D7 to D0)
0 0 ↓ Write 8-bit command (D7 to D0)
1 0 ↓ Write 16-bit display data or 8-bit parameter (D15 to D0)
1 1 ↓ Read 16-bit Display data (D15 to D0)
1 1 ↓ Read 8-bit parameter or status (D7 to D0)
0 0 ↓ Write 8-bit command (D7 to D0)
1 0 ↓ Write 9-bit display data or 8-bit parameter (D8 to D0)
1 1 ↓ Read 9-bit Display data (D8 to D0)
1 1 ↓ Read 8-bit parameter or status (D7 to D0)
0 0 ↓ Write 8-bit command (D7 to D0)
1 0 ↓ Write 18-bit display data or 8-bit parameter (D17 to D0)
1 1 ↓ Read 18-bit Display data (D17 to D0)
1 1 ↓ Read 8-bit parameter or status (D7 to D0)

Table 9.3.1 The function of 6800-series parallel interface
Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh.

9.3.1 Write cycle sequence

The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write
cycle (E low-high-low sequence) consists of 3 control signals (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a
control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low
(=’0’) and vice versa it is data (=’1’).

Figure 9.3.1 6800-Series Write Protocol
Note: E is an unsynchronized signal (It can be stopped)

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Figure 9.3.2 6800-series parallel bus protocol, write to register or display RAM

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9.3.2 9.3.2 Read cycle sequence

The read cycle (E low-high-low sequence) means that the host reads information from LCD driver via interface. The driver
sends data (D[17:0]) to the host when there is a rising edge of E and the host reads data when there is a falling edge of E.

Figure 9.3.3 6800-series read protocol

Note: E is an unsynchronized signal (It can be stopped)

Figure 9.3.4 6800-series parallel bus protocol, read data form register or display RAM

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9.4 Serial interface

The selection of this interface is done by IM2. See the Table 9.4.1.

IM2 4WSPI Interface Read back selection
0 0 3-line serial interface Via the read instruction (8-bit, 24-bit and 32-bit read parameter)

0 1 4-line serial interface Via the read instruction (8-bit, 24-bit and 32-bit read parameter)
Table 9.4.2 Selection of serial interface
The serial interface is either 3-lines/9-bits or 4-lines/8-bts bi-directional interface for communication between the micro

controller and the LCD driver. The 3-lines serial interface use: CSX (chip enable), SCL (serial clock) and SDA (serial data
input/output), and the 4-lines serial interface use: CSX (chip enable), D/CX (data/ command flag), SCL (serial clock) and
SDA (serial data input/output). Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no
communication is necessary.

9.4.1 Command Write Mode

The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-lines serial data
packet contains a control bit D/CX and a transmission byte. In 4-lines serial interface, data packet contains just
transmission byte and control bit D/CX is transferred by the D/CX pin. If D/CX is “low”, the transmission byte is interpreted
as a command byte. If D/CX is “high”, the transmission byte is stored in the display data RAM (memory write command), or
command register as parameter.

Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is initialized when
CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface
and indicates the start of data transmission.

Figure 9.4.1 Serial interface data stream format
When CSX is “high”, SCL clock is ignored. During the high period of CSX the serial interface is initialized. At the falling edge

of CSX, SCL can be high or low (see Figure 9.4.2). SDA is sampled at the rising edge of SCL. D/CX indicates whether the
byte is command (D/CX=’0’) or parameter/RAM data (D/CX=’1’). D/CX is sampled when first rising edge of SCL (3-lines
serial interface) or 8th rising edge of SCL (4-lines serial interface). If CSX stays low after the last bit of command/data byte,
the serial interface expects the D/CX bit (3-lines serial interface) or D7 (4-lines serial interface) of the next byte at the next
rising edge of SCL..

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Figure 9.4.3 3-line serial interface write protocol (write to register with control bit in transmission)

Figure 9.4.4 4-line serial interface write protocol (write to register with control bit in transmission)

9.4.2 Read Functions

The read mode of the interface means that the micro controller reads register value from the driver. To achieve read
function, the micro controller first has to send a command (read ID or register command) and then the following byte is
transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below
figure). The driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of
SCL. Thus the micro controller is supported to read at the rising edge of SCL.

After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL of
the last bit.

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9.4.3 3-line serial protocol

3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):

3-line serial protocol (for RDDID command: 24-bit read)

3-line Serial Protocol (for RDDST command: 32-bit read)

Figure 9.4.5 3-line serial interface read protocol

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9.4.4 4-line serial protocol

4-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):

4-line serial protocol (for RDDID command: 24-bit read)

4-line Serial Protocol (for RDDST command: 32-bit read)

Host Driver

Figure 9.4.6 4-line serial interface read protocol

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9.5 Data Transfer Break and Recovery

If there is a break in data transmission by RESX pulse, while transferring a command or frame memory data or multiple
parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have
reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next
activated after RESX have been HIGH state. See the following example

(MCU to driver)

Host

Figure 9.5.1 Serial bus protocol, write mode – interrupted by RESX

If there is a break in data transmission by CSX pulse, while transferring a command or frame memory data or multiple
parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have
reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next
activated. See the following example

Figure 9.5.2 Serial bus protocol, write mode – interrupted by CSX

If 1, 2 or more parameter commands are being sent and a break occurs while sending any parameter before the last one
and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the
parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is
ready to receive next byte as shown below.

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Figure 9.5.3 Write interrupts recovery (serial interface)

If a 2 or more parameter commands are being sent and a break occurs by the other command before the last one is sent,
then the parameters that were successfully sent are stored and the other parameter of that command remains previous
value.

Figure 9.5.4 Write interrupts recovery (both serial and parallel Interface)

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9.6 Data transfer pause

It will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the
data transmission. If the chip select line is released after a whole byte of a frame memory data or multiple parameter data
has been completed, then driver will wait and continue the frame memory data or parameter data transmission from the
point where it was paused. If the chip select Line is released after a whole byte of a command has been completed, then
the display module will receive either the command‘s parameters (if appropriate) or a new command when the chip select
line is next enabled as shown below.

This applies to the following 4 conditions:

1) Command-Pause-Command

2) Command-Pause-Parameter

3) Parameter-Pause-Command

4) Parameter-Pause-Parameter

9.6.1 Serial interface pause

Figure 9.6.1 Serial interface pause protocol (pause by CSX)

9.6.2 Parallel interface pause

Figure 9.6.2 Parallel bus pause protocol (paused by CSX)

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9.7 Data Transfer Modes

The module has three kinds color modes for transferring data to the display RAM. These are 12-bit color per pixel, 16-bit
color per pixel and 18-bit color per pixel. The data format is described for each interface. Data can be downloaded to the
frame memory by 2 methods.

9.7.1 Method 1

The image data is sent to the frame memory in successive frame writes, each time the frame memory is filled, the frame
memory pointer is reset to the start point and the next frame is written.

9.7.2 Method 2

The image data is sent and at the end of each frame memory download, a command is sent to stop frame memory write.
Then start memory write command is sent, and a new frame is downloaded.

Note 1: These apply to all data transfer Color modes on both serial and parallel interfaces.
Note 2: The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in

the frame memory.

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9.8 Data Color Coding

9.8.1 8-bit Parallel Interface (IM2, IM1, IM0= “100”)

Different display data formats are available for three Colors depth supported by listed below.

- 4k colors, RGB 4,4,4-bit input.

- 65k colors, RGB 5,6,5-bit input.

- 262k colors, RGB 6,6,6-bit input.

9.8.2 8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= “03h”

“1 ”

“1 ”

“1 ”“1 ”

RESX

“

“100”

”

““

“

“1”

““

””

”

””

R1, Bit 3 B1, Bit 3 G2, Bit 3 R3, Bit 30

8080-series control pins

IM[2:0]

CSX

D/CX

WRX

RDX

D7

D6

D5

D4

D3

D2

D1

D0

Look-up table for 4096 color data mapping (12 bits to 18 bits)

Frame memory

R1, Bit 2 B1, Bit 2 G2, Bit 2 R3, Bit 20

R1, Bit 1 B1, Bit 1 G2, Bit 1 R3, Bit 11

R1, Bit 0 B1, Bit 0 G2, Bit 0 R3, Bit 00

G1, Bit 3 R2, Bit 3 B2, Bit 3 G3, Bit 31

G1, Bit 2 R2, Bit 2 B2, Bit 2 G3, Bit 21

G1, Bit 1 R2, Bit 1 B2, Bit 1 G3, Bit 10

G1, Bit 0 R2, Bit 0 B2, Bit 0 G3, Bit 00

Pixel n Pixel n+1

12 bits 12 bits

18 bits

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-time transfer is used to transmit 1 pixel data with the 12-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

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9.8.3 8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= “05h”

There is 1 pixel (3 sub-pixels) per 2-byte

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“100”

““

“

“1”

”

““

””

”

””

8080-series control pins

D7
D6
D5
D4
D3
D2
D1
D0

Look-up table for 65k color data mapping (16 bits to 18 bits)

Frame memory

R1, Bit 4 G1, Bit 20

R1, Bit 3 G1, Bit 10

R1, Bit 2 G1, Bit 01

R1, Bit 1 B1, Bit 40

R1, Bit 0 B1, Bit 31

G1, Bit 5 B1, Bit 21

G1, Bit 4 B1, Bit 10

G1, Bit 3 B1, Bit 00

Pixel n Pixel n+1

16 bits 16 bits

18 bits

R1 G1 B1 R2 G2 B2 R3 G3 B3

R2, Bit 4 G2, Bit 2

R2, Bit 3 G2, Bit 1

R2, Bit 2 G2, Bit 0

R2, Bit 1 B2, Bit 4

R2, Bit 0 B2, Bit 3

G2, Bit 5 B2, Bit 2

G2, Bit 4 B2, Bit 1

G2, Bit 3 B2, Bit 0

Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for

Red and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

V0.2 42 2009-08-05

ST7735R

9.8.4 8-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= “06h”

There is 1 pixel (3 sub-pixels) per 3-bytes.

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“100”

““

“

“1”

”

““

””

”

””

8080-series control pins

D7
D6
D5
D4
D3
D2
D1
D0

0

0

1

0

1

1

R1, Bit 5

R1, Bit 4

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

- -0

- -0

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

Pixel n Pixel n+1

18 bits 18 bits

B1, Bit 5

B1, Bit 4

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0

- -

- -

R2, Bit 5

R2, Bit 4

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

V0.2 43 2009-08-05

ST7735R

9.8.5 16-Bit Parallel Interface (IM2,IM1, IM0= “101”)

Different display data formats are available for three colors depth supported by listed below.

- 4k colors, RGB 4,4,4-bit input

- 65k colors, RGB 5,6,5-bit input

- 262k colors, RGB 6,6,6-bit input

9.8.6 16-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= “03h”

There is 1 pixel (3 sub-pixels) per 1 byte

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“101”

”

““

””

“

“1”

”

““

””

8080-series control pins

D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

-

-

-

-

-

-

-

-

0

0

1

0

1

1

0

0

-

-

-

-

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0

Pixel n Pixel n+1

-

-

-

-

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 3

B2, Bit 2

B2, Bit 1

B2, Bit 0

-

-

-

-

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

B3, Bit 3

B3, Bit 2

B3, Bit 1

B3, Bit 0

Pixel n+2 Pixel n+3

-

-

-

-

R4, Bit 3

R4, Bit 2

R4, Bit 1

R4, Bit 0

G4, Bit 3

G4, Bit 2

G4, Bit 1

G4, Bit 0

B4, Bit 3

B4, Bit 2

B4, Bit 1

B4, Bit 0

12 bits 12 bits

Look-up table for 4096 color data mapping (12 bits to 18 bits)

18 bits

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information.

V0.2 44 2009-08-05

ST7735R

9.8.7 16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= “05h”

There is 1 pixel (3 sub-pixels) per 1 byte

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“101”

““

“

“1”

”

““

””

”

””

8080-series control pins

D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4

-

-

-

-

-

-

-

0

0

1

0

1

1

0

0

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 5

G2, Bit 4

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 3

B2, Bit 2

B2, Bit 1

B2, Bit 0

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 5

G3, Bit 4

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

B3, Bit 3

B3, Bit 2

B3, Bit 1

B3, Bit 0

R4, Bit 3

R4, Bit 2

R4, Bit 1

R4, Bit 0

G4, Bit 5

G4, Bit 4

G4, Bit 3

G4, Bit 2

G4, Bit 1

G4, Bit 0

B4, Bit 3

B4, Bit 2

B4, Bit 1

B4, Bit 0

Pixel n Pixel n+1

16 bits 16 bits

Pixel n+2 Pixel n+3

Look-up table for 65k color data mapping (16 bits to 18 bits)

18 bits

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0

for Red and Blue data.
Note 2: 1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

V0.2 45 2009-08-05

ST7735R

9.8.8 16-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= “06h”

There are 2 pixels (6 sub-pixels) per 3 bytes

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“101”

““

“

“1”

”

““

””

”

””

8080-series control pins

D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

-

-

-

-

-

-

-

-

0

0

1

0

1

1

0

0

R1, Bit 5

R1, Bit 4

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

- - - -

- - - -

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

- - - -

- - - -

B1, Bit 5

B1, Bit 4

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0

R2, Bit 5

R2, Bit 4

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 5

G2, Bit 4

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 5

B2, Bit 4

B2, Bit 3

B2, Bit 2

B2, Bit 1

B2, Bit 0

R3, Bit 5

R3, Bit 4

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 5

G3, Bit 4

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

Pixel n Pixel n+1

18 bits

18 bits

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

V0.2 46 2009-08-05

ST7735R

9.8.9 9-Bit Parallel Interface (IM2, IM1, IM0=“110”)

Different display data formats are available for three colors depth supported by listed below.

-262k colors, RGB 6,6,6-bit input

9.8.10 Write 9-bit data for RGB 6-6-6-bit input (262k-color)

There is 1 pixel (6 sub-pixels) per 3 bytes

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“110”

““

“

“1”

”

““

””

”

””

8080-series control

pins

D8
D7
D6
D5
D4
D3
D2
D1
D0

1

0

0

R1, Bit 5

R1, Bit 40

R1, Bit 30

R1, Bit 21

R1, Bit 10

R1, Bit 01

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 5

B1, Bit 4

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0

Pixel n Pixel n+1

18 bits 18 bits

R2, Bit 5-

R2, Bit 4

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 5

G2, Bit 4

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 5

B2, Bit 4

B2, Bit 3

B2, Bit 2

B2, Bit 1

B2, Bit 0

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note 1: The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

V0.2 47 2009-08-05

ST7735R

9.8.11 18-Bit Parallel Interface (IM2, IM1, IM0=“111”)

Different display data formats are available for three colors depth supported by listed below.

- 4k colors, RGB 4,4,4-bit input

- 65k colors, RGB 5,6,5-bit input

- 262k colors, RGB 6,6,6-bit input.

9.8.12 18-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h”

There is 1 pixel (3 sub-pixels) per 1 byte

““““ 1””””

RESX

““““ 111””””

IM[2:0]

CSX

D/CX

WRX

““““ 1””””

RDX

8080-series control pins

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

-

-

-

-

-

-

-

-

-

-

0

0

1

0

1

1

0

0

-

-

-

-

-

-

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0

Pixel n Pixel n+1

-

-

-

-

-

-

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 3

B2, Bit 2

B2, Bit 1

B2, Bit 0

-

-

-

-

-

-

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

B3, Bit 3

B3, Bit 2

B3, Bit 1

B3, Bit 0

Pixel n+2 Pixel n+3

-

-

-

-

-

-

R4, Bit 3

R4, Bit 2

R4, Bit 1

R4, Bit 0

G4, Bit 3

G4, Bit 2

G4, Bit 1

G4, Bit 0

B4, Bit 3

B4, Bit 2

B4, Bit 1

B4, Bit 0

12 bits 12 bits

Look-Up Table for 4096 Color data mapping (12 bits to 18 bits)

18 bits

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information.

V0.2 48 2009-08-05

ST7735R

9.8.13 18-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h”

There is 1 pixel (3 sub-pixels) per 1 byte

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“111”

““

“

“1”

”

““

””

”

””

8080-series control pins

D17
D16
D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1

-

-

-

-

-

-

-

-

-

-

0

0

1

0

1

1

0

-

-

R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4

B1, Bit 3

B1, Bit 2

B1, Bit 1

-

-

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 5

G2, Bit 4

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 3

B2, Bit 2

B2, Bit 1

-

-

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 5

G3, Bit 4

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

B3, Bit 3

B3, Bit 2

B3, Bit 1

-

-

R4, Bit 3

R4, Bit 2

R4, Bit 1

R4, Bit 0

G4, Bit 5

G4, Bit 4

G4, Bit 3

G4, Bit 2

G4, Bit 1

G4, Bit 0

B4, Bit 3

B4, Bit 2

B4, Bit 1

D0

0

B1, Bit 0

Pixel n Pixel n+1

16 bits 16 bits

B2, Bit 0

B3, Bit 0

Pixel n+2 Pixel n+3

B4, Bit 0

Look-up table for 65k color data mapping (16 bits to 18 bits)

18 bits

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0

for Red and Blue data.
Note 2: 1-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.

V0.2 49 2009-08-05

ST7735R

9.8.14 18-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h”

There is 1 pixel (3 sub-pixels) per 1 byte

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“111”

““

“

“1”

”

““

””

”

””

8080-series control pins

D17
D16
D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2

-

-

-

-

-

-

-

-

-

-

0

0

1

0

1

1

R1, Bit 5 R2, Bit 5 R3, Bit 5 R4, Bit 5

R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 5 B2, Bit 5 B3, Bit 5 B4, Bit 5

B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4

B1, Bit 3

B1, Bit 2

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 5

G2, Bit 4

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 3

B2, Bit 2

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 5

G3, Bit 4

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

B3, Bit 3

B3, Bit 2

R4, Bit 3

R4, Bit 2

R4, Bit 1

R4, Bit 0

G4, Bit 5

G4, Bit 4

G4, Bit 3

G4, Bit 2

G4, Bit 1

G4, Bit 0

B4, Bit 3

B4, Bit 2

D1
D0

0

0

B1, Bit 1

B1, Bit 0

Pixel n Pixel n+1

18 bits 18 bits

B2, Bit 1

B2, Bit 0

B3, Bit 1

B3, Bit 0

Pixel n+2 Pixel n+3

B4, Bit 1

B4, Bit 0

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data.
Note 2: 1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.

V0.2 50 2009-08-05

ST7735R

9.8.15 3-line serial Interface

Different display data formats are available for three colors depth supported by the LCM listed below.
4k colors, RGB 4-4-4-bit input
65k colors, RGB 5-6-5-bit input
262k colors, RGB 6-6-6-bit input

9.8.16 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h”

Note 1: Pixel data with the 12-bit color depth information
Note 2: The most significant bits are: Rx3, Gx3 and Bx3
Note 3: The least significant bits are: Rx0, Gx0 and Bx0

V0.2 51 2009-08-05

ST7735R

9.8.17 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h”

Note 1: Pixel data with the 16-bit color depth information
Note 2: The most significant bits are: Rx4, Gx5 and Bx4
Note 3: The least significant bits are: Rx0, Gx0 and Bx0

V0.2 52 2009-08-05

ST7735R

9.8.18 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h”

Note 1: Pixel data with the 18-bit color depth information
Note 2: The most significant bits are: Rx5, Gx5 and Bx5
Note 3: The least significant bits are: Rx0, Gx0 and Bx0

V0.2 53 2009-08-05

ST7735R

9.8.19 4-line serial Interface

Different display data formats are available for three colors depth supported by the LCM listed below.
4k colors, RGB 4-4-4-bit input
65k colors, RGB 5-6-5-bit input
262k colors, RGB 6-6-6-bit input

9.8.20 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h”

Note 1. pixel data with the 12-bit color depth information
Note 2. The most significant bits are: Rx3, Gx3 and Bx3
Note 3. The least significant bits are: Rx0, Gx0 and Bx0

V0.2 54 2009-08-05

ST7735R

9.8.21 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h”

Note 1. pixel data with the 16-bit color depth information
Note 2. The most significant bits are: Rx4, Gx5 and Bx4
Note 3. The least significant bits are: Rx0, Gx0 and Bx0

9.8.22 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h”

Note 1. pixel data with the 18-bit color depth information
Note 2. The most significant bits are: Rx5, Gx5 and Bx5
Note 3. The least significant bits are: Rx0, Gx0 and Bx0

V0.2 55 2009-08-05

ST7735R

9.9 Display Data RAM

9.9.1 Configuration (GM[1:0] = “00”)

The display module has an integrated 132x162x18-bit graphic type static RAM. This 384,912-bit memory allows storing
on-chip a 132xRGBx162 image with an 18-bpp resolution (262K-color). There will be no abnormal visible effect on the
display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory.

Figure 9.9.1Display data RAM organization

V0.2 56 2009-08-05

ST7735R

Gate Out

9.9.2 Memory to Display Address Mapping

9.9.3 When using 128RGB x 160 resolution (GM[1:0] = “11”, SMX=SMY=SRGB= ‘0’)

Pixel 1 Pixel 2 Pixel 127 Pixel 128

Source Out

RA SA

MY=' 0 ' MY=' 1 ' ML=' 0 ' ML=' 1 '
2 0 159 R0 G0 B0 R1 G1 B1 -------- R126 G126 B126 R127 G127 B127 0 159
3 1 158 -------- 1 158
4 2 157 -------- 2 157
5 3 156 -------- 3 156
6 4 155 -------- 4 155
7 5 154 -------- 5 154
8 6 153 -------- 6 153
9 7 152 -------- 7 152

|
|
|
|

|
154 152 7 -------- 152 7
155 153 6 -------- 153 6
156 154 5 -------- 154 5
157 155 4 -------- 155 4
158 156 3 -------- 156 3
159 157 2 -------- 157 2
160 158 1 -------- 158 1
161 159 0 -------- 159 0

|
|
|
|
|

MX=' 0 ' --------

CA

MX=' 1 ' --------

S7 S8 S9 S10 S11 S12 -------- S385 S386 S387 S388 S389 S390

RGB=0

|

|

|

|

|

|

|

|

|

|

RGB=1

RGB=0

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|

0 1 126 127

127 126 1 0

--------

RGB

Order

RGB=1

|
|
|
|
|

RGB=0

|

|

|

|

|

|

|

|

|

|

RGB=1

RGB=0

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|

RGB=1

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|
|
|
|
|

Note
RA = Row Address,
CA = Column Address
SA = Scan Address
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
ML = Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command

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Gate Out

9.9.4 When using 132RGB x 162 resolution (GM[1:0] = “00”, SMX=SMY=SRGB= ‘0’)

Pixel 1 Pixel 2 Pixel 131 Pixel 132

Source Out

RA SA

MY=' 0 ' MY=' 1 ' ML=' 0 ' ML=' 1 '
1 0 161 R0 G0 B0 R1 G1 B1 -------- R131 G131 B131 R132 G132 B132 0 161
2 1 160 -------- 1 160
3 2 159 -------- 2 159
4 3 158 -------- 3 158
5 4 157 -------- 4 157
6 5 156 -------- 5 156
7 6 155 -------- 6 155
8 7 154 -------- 7 154

|
|
|
|

|
155 154 7 -------- 154 7
156 155 6 -------- 155 6
157 156 5 -------- 156 5
158 157 4 -------- 157 4
159 158 3 -------- 158 3
160 159 2 -------- 159 2
161 160 1 -------- 160 1
162 161 0 -------- 161 0

|
|
|
|
|

MX=' 0 ' --------

CA

MX=' 1 ' --------

S1 S2 S3 S4 S5 S6 -------- S391 S392 S393 S394 S395 S396

RGB=0

|

|

|

|

|

|

|

|

|

|

RGB=1

RGB=0

|

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|

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|

|

|

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|

|

|

|

|

|

|

|

|

|

|

0 1 130 131

131 130 1 0

--------

RGB

Order

RGB=1

|
|
|
|
|

RGB=0

|

|

|

|

|

|

|

|

|

|

RGB=1

RGB=0

|

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RGB=1

|

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|

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|

Note
RA = Row Address,
CA = Column Address
SA = Scan Address
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
ML = Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command

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9.9.5 Normal Display On or Partial Mode On

9.9.6 When using 128RGB x 160 resolution (GM[1:0] = “11”)

In this mode, the content of the frame memory within an area where column pointer is 00h to 7Fh and page pointer is 00h to
9Fh is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0).

1). Example for Normal Display On (MX=MY=ML=’0’, SMX=SMY=’0’)

128 Columns

00h 01h ---- ---- 76h 77h ---- 7Fh 83h
00h 00 01 0Y 0Z 1
01h 10 11 1Y 1Z 2
02h 20 21 2Y 2Z 3

| 30 31 3Y 3Z |
| 40 41 4Y 4Z |
| 50 51 5Y 5Z |

160 Lines

| 60 6Z |
| |
| |
| |
| |
| |
| |

| X0 X1 X2 XX XY XZ 158
9Eh Y0 Y1 Y2 Y3 YW YX YY YZ 159
9Fh Z0 Z1 Z2 Z3 ZW ZX ZY ZZ 160

A0h
A1h

128 x 160 x18bit

Frame RAM

2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=9Bh, MX=MV=ML=’0’ ,SMX=SMY=’0’)

Scan
Order

128 Columns

00 01 02 03 0W 0X 0Y 0Z G2
10 11 12 13 1W 1X 1Y 1Z G3
20 21 22 2X 2Y 2Z G4
30 31 32 3X 3Y 3Z |
40 41 42 4X 4Y 4Z |
50 51 5Y 5Z |
60 6Z |

|

128RGB x 160

LCD Panel

S0 SZ |

U0 U1 UY UZ |
V0 V1 V2 VX VY VZ |
W0 W1 W2 WX WY WZ |

X0 X1 X2 XX XY XZ G159
Y0 Y1 Y2 Y3 YW YX YY YZ G160

Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G161

|
|
|

Display area =160 lines

128 Columns

Scan

128 Columns

Order

00h 01h ---- ---- 76h 77h ---- 7Fh 83h
00h 00 01 0Y 0Z 1
01h 10 11 1Y 1Z 2
02h 20 21 2Y 2Z 3

| 30 31 3Y 3Z |
| 40 41 4Y 4Z |
| 50 51 5Y 5Z |

160 Lines

| 60 6Z |
| |
| |
| |
| U0 U1 UY UZ |
| V0 V1 VX VY VZ |
| W0 W1 W2 WX WY WZ |

| X0 X1 X2 XX XY XZ 158
9Eh Y0 Y1 Y2 Y3 YW YX YY YZ 159
9Fh Z0 Z1 Z2 Z3 ZW ZX ZY ZZ 160

A0h
A1h

128 x 160 x18bit

Frame RAM

00 01 02 03 0W 0X 0Y 0Z G2
10 11 12 13 1W 1X 1Y 1Z G3
20 21 22 2X 2Y 2Z G4
30 31 32 3X 3Y 3Z |
40 41 42 4X 4Y 4Z |
50 51 5Y 5Z |
60 6Z |

128RGB x 160

LCD Panel

S0 SZ |

U0 U1 UY UZ |
V0 V1 V2 VX VY VZ |
W0 W1 W2 WX WY WZ |

X0 X1 X2 XX XY XZ G159
Y0 Y1 Y2 Y3 YW YX YY YZ G160

Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G161

Non-Display
area =4 lines

|
|

Display area

|

=152 lines

|

Non-Display
area =4 lines

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G160

G161

G162

9.9.7 When using 132RGB x 162 resolution (GM[1:0] = “00”)

In this mode, contents of the frame memory within an area where column pointer is 00h to 83h and page pointer is 00h to
A1h is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0)

1). Example for Normal Display On (MX=MY=ML=’0’, SMX=SMY=’0’)

132 Columns

Scan
Order

132 Columns

00h 01h ---- ---- ---- ---- ---- 81h 83h
00h 00 01 02 03 0W 0X 0Y 0Z 1
01h 10 11 12 13 1W 1X 1Y 1Z 2
02h 20 21 22 2X 2Y 2Z 3

| 30 31 32 3X 3Y 3Z |
| 40 41 42 4X 4Y 4Z |

162 Lines

| 50 51 5Y 5Z |
| 60 6Z |
| |
| |
| |
| |
| S0 SZ |

| U0 U1 UY UZ |
9Dh V0 V1 V2 VX VY VZ |
9Eh W0 W1 W2 WX WY WZ |
9Fh X0 X1 X2 XX XY XZ 160
A0h Y0 Y1 Y2 Y3 YW YX YY YZ 161
A1h Z0 Z1 Z2 Z3 ZW ZX ZY ZZ 162

132 x 162 x18 bit

Frame RAM

00 01 02 03 0W 0X 0Y 0Z G1
10 11 12 13 1W 1X 1Y 1Z G2
20 21 22 2X 2Y 2Z G3
30 31 32 3X 3Y 3Z |
40 41 42 4X 4Y 4Z |
50 51 5Y 5Z |
60 6Z |

132RGB x 162

LCD Panel

S0 SZ |

U0 U1 UY UZ |
V0 V1 V2 VX VY VZ |
W0 W1 W2 WX WY WZ |

X0 X1 X2 XX XY XZ G160
Y0 Y1 Y2 Y3 YW YX YY YZ G161

Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G162

2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=9Dh, MX=MV=ML=’0’ ,SMX=SMY=’0’)

132 Columns

Scan

132 Columns

Order

00h 01h ---- ---- ---- ---- ---- 81h 83h
00h 00 01 02 03 0W 0X 0Y 0Z 1
01h 10 11 12 13 1W 1X 1Y 1Z 2
02h 20 21 22 2X 2Y 2Z 3

| 30 31 32 3X 3Y 3Z |
| 40 41 42 4X 4Y 4Z |

162 Lines

| 50 51 5Y 5Z |
| 60 6Z |
| |
| |
| |
| |
| S0 SZ |
| U0 U1 UY UZ |
| V0 V1 V2 VX VY VZ |
| W0 W1 W2 WX WY WZ |

9Fh X0 X1 X2 XX XY XZ 160

A0h Y0 Y1 Y2 Y3 YW YX YY YZ 161
A1h Z0 Z1 Z2 Z3 ZW ZX ZY ZZ 162

132 x 162 x18 bit

Frame RAM

00 01 02 03 0W 0X 0Y 0Z G1
10 11 12 13 1W 1X 1Y 1Z G2
20 21 22 2X 2Y 2Z G3
30 31 32 3X 3Y 3Z |
40 41 42 4X 4Y 4Z |
50 51 5Y 5Z |
60 6Z |

13 2R G B x 1 62

13 2R G B x 1 62

13 2R G B x 1 6213 2R G B x 1 62

LC D Panel

LC D Panel

LC D PanelLC D Panel

S0 SZ |
U0 U1 UY UZ |
V 0 V 1 V 2 V X V Y V Z |

W0 W 1 W 2 W X W Y WZ |

X0 X1 X 2 XX X Y XZ
Y0 Y1 Y 2 Y3 YW Y X Y Y Y Z
Z0 Z1 Z 2 Z3 ZW Z X Z Y Z Z

|
|
|
|

Non-Displa
y area =4
lines

Display
area =155
lines

Non-Displa
y area
=4lines

Display area =162 lines

|
|
|
|

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9.10 Address Counter

The address counter sets the addresses of the display data RAM for writing and reading.
Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit),
according to the data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM.
The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=131 (83h) and Y=0 to
Y=161 (A1h). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined that
will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE
designating the end address.

For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h)
and XE=127 (83h), YE=161 (A1h).

In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps
around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address
increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next
row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS).

For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET and MADCTL” (see
section 10 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations
of flags are allowed. Section 9.10 show the available combinations of writing to the display RAM. When MX, MY and MV will
be changed the data bust be rewritten to the display RAM.

For each image condition, the controls for the column and row counters apply as section 9.11 below

Condition Column Counter Row Counter

When RAMWR/RAMRD command is accepted

Complete Pixel Read / Write action Increment by 1 No change

The Column counter value is larger than “End Column (XE)”

The Column counter value is larger than “End Column (XE)” and the Row

counter value is larger than “End Row (YE)”

Return to

“Start Column (XS)”

Return to

“Start Column (XS)”

Return to

“Start Column (XS)”

Return to

“Start Row (YS)”

Increment by 1

Return to

“Start Row (YS)”

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9.11 Memory Data Write/ Read Direction

The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be
written is controlled by “Memory Data Access Control” Command, bits B5 (MV), B6 (MX), B7 (MY) as described below.

Panel

Figure 9.11.1Data streaming order

9.11.1 When 128RGBx160 (GM= “11”)

MV MX MY

0 0 0 Direct to Physical Column Pointer Direct to Physical Row Pointer
0 0 1 Direct to Physical Column Pointer Direct to (159-Physical Row Pointer)
0 1 0 Direct to (127-Physical Column Pointer) Direct to Physical Row Pointer
0 1 1 Direct to (127-Physical Column Pointer) Direct to (159-Physical Row Pointer)
1 0 0 Direct to Physical Row Pointer Direct to Physical Column Pointer
1 0 1 Direct to (159-Physical Row Pointer) Direct to Physical Column Pointer
1 1 0 Direct to Physical Row Pointer Direct to (127-Physical Column Pointer)
1 1 1 Direct to (159-Physical Row Pointer) Direct to (127-Physical Column Pointer)

9.11.2 When 132RGBx162 (GM= “00”)

MV MX MY

0 0 0 Direct to Physical Column Pointer Direct to Physical Row Pointer
0 0 1 Direct to Physical Column Pointer Direct to (161-Physical Row Pointer)
0 1 0 Direct to (131-Physical Column Pointer) Direct to Physical Row Pointer
0 1 1 Direct to (131-Physical Column Pointer) Direct to (161-Physical Row Pointer)
1 0 0 Direct to Physical Row Pointer Direct to Physical Column Pointer
1 0 1 Direct to (161-Physical Row Pointer) Direct to Physical Column Pointer
1 1 0 Direct to Physical Row Pointer Direct to (131-Physical Column Pointer)
1 1 1 Direct to (161-Physical Row Pointer) Direct to (131-Physical Column Pointer)

Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7

(MY), B6 (MX), B5 (MV). The write order for each pixel unit is

CASET RASET

CASET RASET

One pixel unit represents 1 column and 1page counter value on the Frame Memory.

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9.11.3 Frame Data Write Direction According to the MADCTL parameters (MV, MX and MY)

Display Data

Direction

Normal 0 0 0

Y-Mirror 0 0 1

X-Mirror 0 1 0

MADCTL

Parameter

MV MX MY

Image in the Host

(MPU)

Image in the Driver

(DDRAM)

X-Mirror
Y-Mirror

X-Y Exchange 1 0 0

X-Y Exchange
Y-Mirror

X-Y Exchange
X-Mirror

0 1 1

1 0 1

1 1 0

X-Y Exchange
X-Mirror
Y-Mirror

1 1 1

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9.12 Tearing Effect Output Line

The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled
by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the
Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when
displaying video images.

9.12.1 Tearing Effect Line Modes

Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:

tvdh= The LCD display is not updated from the Frame Memory
tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)

Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 162
H-sync pulses per field.

thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)

Note: During Sleep In Mode, the Tearing Output Pin is active Low.

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9.12.2 Tearing Effect Line Timings

The Tearing Effect signal is described below:

Symbol Parameter min max unit description

tvdl Vertical Timing Low Duration 13 - ms

tvdh Vertical Timing High Duration 1000 - µs

thdl Horizontal Timing Low Duration 33 - µs

thdh Horizontal Timing Low Duration 25 500 µs

Table 9.12.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 60 Hz, Ta=25°C)

Note: The timings in Table 9.10.1 apply when MADCTL ML=0 and ML=1

The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.

The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect:

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9.12.3 Example 1: MPU Write is faster than panel read

Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of
the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame
refresh has a complete new image:

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9.12.4 Example 2: MPU write is slower than panel read

The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the
Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing
download during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position.

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9.13 Power ON/OFF Sequence

VDD must be powered on before the VDDI.
VDDI must be powered off before the VDD.
During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 120msec after RESX
has been released.
During power off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum 0msec after RESX has
been released.
CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX.

Note 1: There will be no damage to the display module if the power sequences are not met.
Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out

command. Also between receiving Sleep In command and Power Off Sequence.

Note 4: If RESX line is not held stable by host during Power On Sequence as defined in the sequence below, then it will be necessary to

apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not
guaranteed.

The power on/off sequence is illustrated below

TrPW 0ns TfPW 0ns

VDD

VDDI

CSX

RESX

(Power down in

sleep-out mode)

RESX

(Power down in

sleep-in mode)

H or L

Timing when the latter signal rises up to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross
point of 90% of 2.75V, not 90% of 2.6V.

Timing when the latter signal falls up to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross
point of 90% of 2.75V, not 90% of 2.6V.

Tf

Tr

30%

PW-CSX

= +/- no limit

Tr

PW-RESX

Tr

= + no limit

PW-RESX

Tf

PW-RESX1

= + no limit

PW-CSX

= min

120ms

30%

Tf
Tf

is applied to RESX falling in the Sleep Out Mode.

PW-RESx1

is applied to RESX falling in the Sleep In Mode.

PW-RESx2

= +/- no limit

Tf

PW-RESX2

= min 0ms

9.13.1 Uncontrolled Power Off

The uncontrolled power-off means a situation which removed a battery without the controlled power off sequence. It will
neither damage the module or the host interface.

If uncontrolled power-off happened, the display will go blank and there will not any visible effect on the display (blank
display) and remains blank until “Power On Sequence” powers it up.

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9.14 Power Level Definition

9.14.1 Power Level

6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption

1. Normal Mode On (full display), Idle Mode Off, Sleep Out.
In this mode, the display is able to show maximum 262,144 colors.

2. Partial Mode On, Idle Mode Off, Sleep Out.
In this mode part of the display is used with maximum 262,144 colors.

3. Normal Mode On (full display), Idle Mode On, Sleep Out.
In this mode, the full display area is used but with 8 colors.

4. Partial Mode On, Idle Mode On, Sleep Out.
In this mode, part of the display is used but with 8 colors.

5. Sleep In Mode
In this mode, the DC: DC converter, internal oscillator and panel driver circuit are stopped. Only the MCU interface and
memory works with VDDI power supply. Contents of the memory are safe.

6. Power Off Mode
In this mode, both VDD and VDDI are removed.

Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.

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9.14.2 Power Flow Chart

Normal display mode on = NOR ON
Partial display mode on = PTL ON
Idle mode off = IDM OFF
Idle mode on = IDM ON
Sleep out = SLP OUT
Sleep in = SLP IN

NOR ON

PTL ON

IDM ON IDM OFF

IDM ON IDM OFF

Sleep out

Normal display mode on

Idle mode off

Sleep out

Normal display mode on

Idle mode on

Sleep out

Partial display mode on

Idle mode off

SLP IN

SLP OUT

SLP IN

SLP OUT

SLP IN

SLP OUT

Power on sequence

HW reset

SW reset

Sleep in

Normal display mode on

Idle mode off

IDM ON IDM OFF

Sleep in

Normal display mode on

Idle mode on

Sleep in

Partial display mode on

Idle mode off

IDM ON IDM OFF

NOR ON

PTL ON

PTL ON

NOR ON

Sleep out

Partial display mode on

Idle mode on

SLP IN

SLP OUT

Sleep in

Partial display mode on

Idle mode on

PTL ON

NOR ON

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9.15 Reset Table

9.15.1 Reset Table (Default Value, GM[1:0]=“11”, 128RGB x 160)

Item After Power On After H/W Reset After S/W Reset

Frame memory Random No Change No Change

Sleep In/Out In In In

Display On/Off Off Off Off

Display mode (normal/partial) Normal Normal Normal

Display Inversion On/Off Off Off Off

Display Idle Mode On/Off Off Off Off

Column: Start Address (XS) 0000h 0000h 0000h

Column: End Address (XE) 007Fh 007Fh

Row: Start Address (YS) 0000h 0000h 0000h

Row: End Address (YE) 009Fh 009Fh

Gamma setting GC0 GC0 GC0

RGB for 4k and 65k Color Mode Random values Random values No Change

Partial: Start Address (PSL) 0000h 0000h 0000h

Partial: End Address (PEL) 009Fh 009Fh 009Fh

Tearing: On/Off Off Off Off

Tearing Effect Mode (*1) 0 (Mode1) 0 (Mode1) 0 (Mode1)

Memory Data Access Control (MY/MX/MV/ML/RGB) 0/0/0/0/0 0/0/0/0/0 No Change

Interface Pixel Color Format 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) No Change

RDDPM 08h 08h 08h

RDDMADCTL 00h 00h No Change

RDDCOLMOD 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) No Change

RDDIM 00h 00h 00h

RDDSM 00h 00h 00h

ID2 NV value NV value NV value
ID3 NV value NV value NV value

Note: TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only

007Fh (127d) (when MV=0)
009Fh (159d) (when MV=1)

009Fh (159d) (when MV=0)
007Fh (127d) (when MV=1)

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9.15.2 Reset Table (GM[1:0]= “00”, 132RGB x 162)

Item After Power On After H/W Reset After S/W Reset

Frame memory Random No Change No Change

Sleep In/Out In In In

Display On/Off Off Off Off

Display mode (normal/partial) Normal Normal Normal

Display Inversion On/Off Off Off Off

Display Idle Mode On/Off Off Off Off

Column: Start Address (XS) 0000h 0000h 0000h

Column: End Address (XE) 0083h 0083h

Row: Start Address (YS) 0000h 0000h 0000h

Row: End Address (YE) 00A1h 00A1h

Gamma setting GC0 GC0 GC0

RGB for 4k and 65k Color Mode Random values Random values No Change

Partial: Start Address (PSL) 0000h 0000h 0000h

Partial: End Address (PEL) 00A1h 00A1h 00A1h

Tearing: On/Off Off Off Off

Tearing Effect Mode (*1) 0 (Mode1) 0 (Mode1) 0 (Mode1)

Memory Data Access Control (MY/MX/MV/ML/RGB) 0/0/0/0/0 0/0/0/0/0 No Change

Interface Pixel Color Format 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) No Change

RDDPM 08h 08h 08h

RDDMADCTL 00h 00h No Change

RDDCOLMOD 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) No Change

RDDIM 00h 00h 00h

RDDSM 00h 00h 00h

ID2 NV value NV value NV value
ID3 NV value NV value NV value

Note: TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only

0083h (131d) (when MV=0)

00A1h (161d) (when MV=1)

00A1h (161d) (when MV=0)

0083h (131d) (when MV=1)

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9.16 Module Input/Output Pins

9.16.1 Output or Bi-directional (I/O) Pins

Output or Bi-directional pins After Power On After Hardware Reset After Software Reset
TE Low Low Low
D7 to D0 (Output driver) High-Z (Inactive) High-Z (Inactive) High-Z (Inactive)

Input pins
RESX See 9.14 Input valid Input valid Input valid See 9.14

CSX Input invalid Input valid Input valid Input valid Input invalid
D/CX Input invalid Input valid Input valid Input valid Input invalid
WRX Input invalid Input valid Input valid Input valid Input invalid
RDX Input invalid Input valid Input valid Input valid Input invalid
D7 to D0 Input invalid Input valid Input valid Input valid Input invalid

Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset.

During Power
On Process

After Power On

After Hardware
Reset

After Software
Reset

During Power
Off Process

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9.17 Reset Timing

Related Pins Symbol Parameter MIN MAX Unit

tRESW Reset pulse duration 10 - us

RESX

Table 9.17.1 Reset timing
Notes:

1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from NVM (or similar
device) to registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a rising
edge of RESX.

2. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below:

3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time
is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In -mode.) and then return
to Default condition for Hardware Reset.

4. Spike Rejection also applies during a valid reset pulse as shown below:

tREST Reset cancel

RESX Pulse Action
Shorter than 5us Reset Rejected
Longer than 9us Reset
Between 5us and 9us Reset starts

- 5 ms
120 ms

5. When Reset applied during Sleep In Mode.

6. When Reset applied during Sleep Out Mode.

7. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent
for 120msec.

V0.2 74 2009-08-05

ST7735R

9.18 Color Depth Conversion Look Up Tables

9.18.1 65536 Color to 262,144 Color

Color

RED

Color
GREEN

Look Up Table Output
Frame Memory Data (6-bits)

R005 R004 R003 R002 R001 R000 1 00000
R015 R014 R013 R012 R011 R010 2 00001
R025 R024 R023 R022 R021 R020 3 00010
R035 R034 R033 R032 R031 R030 4 00011
R045 R044 R043 R042 R041 R040 5 00100
R055 R054 R053 R052 R051 R050 6 00101
R065 R064 R063 R062 R061 R060 7 00110
R075 R074 R073 R072 R071 R070 8 00111
R085 R084 R083 R082 R081 R080 9 01000
R095 R094 R093 R092 R091 R090 10 01001
R105 R104 R103 R102 R101 R100 11 01010
R115 R114 R113 R112 R111 R110 12 01011
R125 R124 R123 R122 R121 R120 13 01100
R135 R134 R133 R132 R131 R130 14 01101
R145 R144 R143 R142 R141 R140 15 01110
R155 R154 R153 R152 R151 R150 16 01111
R165 R164 R163 R162 R161 R160 17 10000
R175 R174 R173 R172 R171 R170 18 10001
R185 R184 R183 R182 R181 R180 19 10010
R195 R194 R193 R192 R191 R190 20 10011
R205 R204 R203 R202 R201 R200 21 10100
R215 R214 R213 R212 R211 R210 22 10101
R225 R224 R223 R222 R221 R220 23 10110
R235 R234 R233 R232 R231 R230 24 10111
R245 R244 R243 R242 R241 R240 25 11000
R255 R254 R253 R252 R251 R250 26 11001
R265 R264 R263 R262 R261 R260 27 11010
R275 R274 R273 R272 R271 R270 28 11011
R285 R284 R283 R282 R281 R280 29 11100
R295 R294 R293 R292 R291 R290 30 11101
R305 R304 R303 R302 R301 R300 31 11110
R315 R314 R313 R312 R311 R310 32 11111

Look Up Table Output
Frame Memory Data (6-bits)

G005 G004 G003 G002 G001 G000 33 000000
G015 G014 G013 G012 G011 G010 34 000001
G025 G024 G023 G022 G021 G020 35 000010
G035 G034 G033 G032 G031 G030 36 000011
G045 G044 G043 G042 G041 G040 37 000100
G055 G054 G053 G052 G051 G050 38 000101
G065 G064 G063 G062 G061 G060 39 000110
G075 G074 G073 G072 G071 G070 40 000111
G085 G084 G083 G082 G081 G080 41 001000
G095 G094 G093 G092 G091 G090 42 001001
G105 G104 G103 G102 G101 G100 43 001010
G115 G114 G113 G112 G111 G110 44 001011
G125 G124 G123 G122 G121 G120 45 001100
G135 G134 G133 G132 G131 G130 46 001101
G145 G144 G143 G142 G141 G140 47 001110
G155 G154 G153 G152 G151 G150 48 001111
G165 G164 G163 G162 G161 G160 49 010000
G175 G174 G173 G172 G171 G170 50 010001
G185 G184 G183 G182 G181 G180 51 010010
G195 G194 G193 G192 G191 G190 52 010011
G205 G204 G203 G202 G201 G200 53 010100

RGBSET
Parameter

RGBSET
Parameter

Look Up Table Input Data
65k Color (5-bits)

Look Up Table Input Data
65k Color (5-bits)

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ST7735R

Color
BLUE

G215 G214 G213 G212 G211 G210 54 010101
G225 G224 G223 G222 G221 G220 55 010110
G235 G234 G233 G232 G231 G230 56 010111
G245 G244 G243 G242 G241 G240 57 011000
G255 G254 G253 G252 G251 G250 58 011001
G265 G264 G263 G262 G261 G260 59 011010
G275 G 274 G273 G272 G271 G270 60 011011
G285 G 284 G283 G282 G281 G280 61 011100
G295 G 294 G293 G292 G291 G290 62 011101
G305 G 304 G303 G302 G301 G300 63 011110
G315 G 314 G313 G312 G311 G310 64 011111
G325 G324 G323 G322 G321 G320 65 100000
G335 G334 G333 G332 G331 G330 66 100001
G345 G344 G343 G342 G341 G340 67 100010
G355 G354 G353 G352 G351 G350 68 100011
G365 G364 G363 G362 G361 G360 69 100100
G375 G374 G373 G372 G371 G370 70 100101
G385 G384 G383 G382 G381 G380 71 100110
G395 G394 G393 G392 G391 G390 72 100111
G405 G404 G403 G402 G401 G400 73 101000
G415 G414 G413 G412 G411 G410 74 101001
G425 G424 G423 G422 G421 G420 75 101010
G435 G434 G433 G432 G431 G430 76 101011
G445 G444 G443 G442 G441 G440 77 101100
G455 G454 G453 G452 G451 G450 78 101101
G465 G464 G463 G462 G461 G460 79 101110
G475 G474 G473 G472 G471 G470 80 101111
G485 G484 G483 G482 G481 G480 81 110000
G495 G494 G493 G492 G491 G490 82 110001
G505 G504 G503 G502 G501 G500 83 110010
G515 G514 G513 G512 G511 G510 84 110011
G525 G524 G523 G522 G521 G520 85 110100
G535 G534 G533 G532 G531 G530 86 110101
G545 G544 G543 G542 G541 G540 87 110110
G555 G554 G553 G552 G551 G550 88 110111
G565 G564 G563 G562 G561 G560 89 111000
G575 G574 G573 G572 G571 G570 90 111001
G585 G584 G583 G582 G581 G580 91 111010
G595 G594 G593 G592 G591 G590 92 111011
G605 G604 G603 G602 G601 G600 93 111100
G615 G614 G613 G612 G611 G610 94 111101
G625 G624 G623 G622 G621 G620 95 111110
G635 G634 G633 G632 G631 G630 96 111111

Look Up Table Output
Frame Memory Data (6-bits)

B005 B004 B003 B002 B001 B000 97 00000
B015 B014 B013 B012 B011 B010 98 00001
B025 B024 B023 B022 B021 B020 99 00010
B035 B034 B033 B032 B031 B030 100 00011
B045 B044 B043 B042 B041 B040 101 00100
B055 B054 B053 B052 B051 B050 102 00101
B065 B064 B063 B062 B061 B060 103 00110
B075 B074 B073 B072 B071 B070 104 00111
B085 B084 B083 B082 B081 B080 105 01000
B095 B094 B093 B092 B091 B090 106 01001
B105 B104 B103 B102 B101 B100 107 01010
B115 B114 B113 B112 B111 B110 108 01011
B125 B124 B123 B122 B121 B120 109 01100
B135 B134 B133 B132 B131 B130 110 01101
B145 B144 B143 B142 B141 B140 111 01110
B155 B154 B153 B152 B151 B150 112 01111
B165 B164 B163 B162 B161 B160 113 10000

RGBSET
Parameter

Look Up Table Input Data
65k Color (5-bits)

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ST7735R

B175 B174 B173 B172 B171 B170 114 10001
B185 B184 B183 B182 B181 B180 115 10010
B195 B194 B193 B192 B191 B190 116 10011
B205 B204 B203 B202 B201 B200 117 10100
B215 B214 B213 B212 B211 B210 118 10101
B225 B224 B223 B222 B221 B220 119 10110
B235 B234 B233 B232 B231 B230 120 10111
B245 B244 B243 B242 B241 B240 121 11000
B255 B254 B253 B252 B251 B250 122 11001
B265 B264 B263 B262 B261 B260 123 11010
B275 B274 B273 B272 B271 B270 124 11011
B285 B284 B283 B282 B281 B280 125 11100
B295 B294 B293 B292 B291 B290 126 11101
B305 B304 B303 B302 B301 B300 127 11110
B315 B314 B313 B312 B311 B310 128 11111

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ST7735R

9.18.2 4096 Color to 262,144 Color

Color

RED

GREEN

BLUE

Look Up Table Output
Frame Memory Data (6-bits)

R005 R004 R003 R002 R001 R000 1 0000
R015 R014 R013 R012 R011 R010 2 0001
R025 R024 R023 R022 R021 R020 3 0010
R035 R034 R033 R032 R031 R030 4 0011
R045 R044 R043 R042 R041 R040 5 0100
R055 R054 R053 R052 R051 R050 6 0101
R065 R064 R063 R062 R061 R060 7 0110
R075 R074 R073 R072 R071 R070 8 0111
R085 R084 R083 R082 R081 R080 9 1000
R095 R094 R093 R092 R091 R090 10 1001
R105 R104 R103 R102 R101 R100 11 1010
R115 R114 R113 R112 R111 R110 12 1011
R125 R124 R123 R122 R121 R120 13 1100
R135 R134 R133 R132 R131 R130 14 1101
R145 R144 R143 R142 R141 R140 15 1110
R155 R154 R153 R152 R151 R150 16 1111
R165 R164 R163 R162 R161 R160 17
| |
R315 R314 R313 R312 R311 R310 32
G005 G004 G003 G002 G001 G000 33 0000
G015 G014 G013 G012 G011 G010 34 0001
G025 G024 G023 G022 G021 G020 35 0010
G035 G034 G033 G032 G031 G030 36 0011
G045 G044 G043 G042 G041 G040 37 0100
G055 G054 G053 G052 G051 G050 38 0101
G065 G064 G063 G062 G061 G060 39 0110
G075 G074 G073 G072 G071 G070 40 0111
G085 G084 G083 G082 G081 G080 41 1000
G095 G094 G093 G092 G091 G090 42 1001
G105 G104 G103 G102 G101 G100 43 1010
G115 G114 G113 G112 G111 G110 44 1011
G125 G124 G123 G122 G121 G120 45 1100
G135 G134 G133 G132 G131 G130 46 1101
G145 G144 G143 G142 G141 G140 47 1110
G155 G154 G153 G152 G151 G150 48 1111
G165 G164 G163 G162 G161 G160 49
| |
G635 G634 G633 G632 G631 G630 96
B005 B004 B003 B002 B001 B000 97 0000
B015 B014 B013 B012 B011 B010 98 0001
B025 B024 B023 B022 B021 B020 99 0010
B035 B034 B033 B032 B031 B030 100 0011
B045 B044 B043 B042 B041 B040 101 0100
B055 B054 B053 B052 B051 B050 102 0101
B065 B064 B063 B062 B061 B060 103 0110
B075 B074 B073 B072 B071 B070 104 0111
B085 B084 B083 B082 B081 B080 105 1000
B095 B094 B093 B092 B091 B090 106 1001
B105 B104 B103 B102 B101 B100 107 1010
B115 B114 B113 B112 B111 B110 108 1011
B125 B124 B123 B122 B121 B120 109 1100
B135 B134 B133 B132 B131 B130 110 1101
B145 B144 B143 B142 B141 B140 111 1110
B155 B154 B153 B152 B151 B150 112 1111
B165 B164 B163 B162 B161 B160 113
| |
B315 B314 B313 B312 B311 B310 128

RGBSET
Parameter

Look Up Table Input Data
4k Color (4-bits)

Not used

Not used

Not used

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ST7735R

0 ↑ 1

No Operation

0 ↑ 1

Software reset

↑ 1

Read Display ID

↑

Dummy read

↑

ID1 read

↑

ID2 read

↑

I

D3 read

↑ 1

Read Display Status

↑

Dummy read

↑

-

↑

-

↑

-

↑

-

↑ 1

↑

Dummy

read

↑

-

↑ 1

Read Display

↑

Dummy read

↑

-

↑ 1

Read Display Pixel

↑

Dummy read

↑

-

↑ 1

Read Display Image

↑

Dummy read

↑

-

↑ 1

Read Display Signal

↑

Dummy read

↑

-

10 Command

10.1 System function Command List and Description

Table 10.1.1 System Function command List (1)

Instruction Refer

NOP 10.1.1

SWRESET 10.1.2

RDDID 10.1.3

RDDST 10.1.4

RDDPM 10.1.5

RDD

MADCTL

RDD

COLMOD

RDDIM 10.1.8

RDDSM 10.1.9

10.1.6

10.1.7

“-“: Don’t care

D/CX WRX RDX D17-8 D7 D6 D5

- 0 0 0 0 0 0 0 0 (00h)

- 0 0 0 0 0 0 0 1 (01h)
0
1 1
1 1
1 1
1 1
0
1 1
1 1
1 1
1 1
1 1

0
1 1

1 1
0
1 1
1 1
0
1 1
1 1
0
1 1
1 1
0
1 1
1 1

- 0 0 0 0 0 1 0 0 (04h)

- - - - - - - - -

- ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10

- 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20

- ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30

- 0 0 0 0 1 0 0 1 (09h)

- - - - - - - - -

- BSTON MY MX MV ML RGB MH ST24

- ST23 IFPF2 IFPF1 IFPF0 IDMON PTLON SLOUT NORON

- VSSON ST14 INVON ST12 ST11 DISON TEON GCS2

- GCS1 GCS0 TEM ST4 ST3 ST2 ST1 ST0

- 0 0 0 0 1 0 1 0 (0Ah)

- - - - - - - - -

- BSTON IDMON PTLON SLPOUT NORON DISON - -

- 0 0 0 0 1 0 1 1 (0Bh)

- - - - - - - - -

- MY MX MV ML RGB MH

- 0 0 0 0 1 1 0 0 (0Ch)

- - - - - - - - -

- 0 0 0 0 - IFPF2 IFPF1 IFPF0

- 0 0 0 0 1 1 0 1 (0Dh)

- - - - - - - - -

- VSSON D6 INVON - - GCS2 GCS1 GCS0

- 0 0 0 0 1 1 1 0 (0Eh)

- - - - - - - - -

- TEON TEM - - - - - -

D4 D3 D2 D1

D0 Hex

- -

Function

Read Display Power

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ST7735R

Sleep in & booster off

Sleep out & booster on

Partial mode on

Partial off (Normal)

Display inversion off

Display inversion on

Gamma curve selec

t

-

Display off

Display on

Column address set

Row address set

Memory write

Write data

LUT for 4k,65k,262k color

Red tone 0

:

Red tone

“a”

Green tone 0

:

Green tone

“b”

Blue tone 0

:

Blue tone

“c”

Memory read

Du

mmy read

Read data

Table 10.1.2 System Function command List (2)

Instructio

SLPIN

SLPOUT 10.1.11

PTLON 10.1.12

NORON 10.1.13

INVOFF 10.1.14

INVON 10.1.15

GAMSET 10.1.16

DISPOFF 10.1.17

DISPON 10.1.18

CASET 10.1.19

RASET 10.1.20

RAMWR 10.1.21

RGBSET 10.1.22

RAMRD 10.1.23

Refer

10.1.10

“-“: Don’t care

D/C WR

0 ↑ 1
0 ↑ 1
0 ↑ 1
0 ↑ 1
0 ↑ 1
0 ↑ 1
0 ↑ 1
1 ↑ 1
0 ↑ 1
0 ↑ 1
0 ↑ 1
1 ↑ 1
1 ↑ 1
1 ↑ 1
1 ↑ 1
0 ↑ 1
1 ↑ 1
1 ↑ 1
1 ↑ 1
1 ↑ 1
0 ↑ 1
1 ↑ 1
0 ↑ 1
1 ↑ 1
1 ↑ 1
1 ↑ 1
1 ↑ 1
1 ↑ 1
1 ↑ 1
1 ↑ 1
1 ↑ 1
1 ↑ 1
0 ↑ 1
1 1 ↑ - - - - - - - - -
1 1 ↑ - D7 D6 D5 D4 D3 D2 D1 D0

RDX

D17-

D7 D6 D5 D4 D3 D2 D1 D0 Hex

- 0 0 0 1 0 0 0 0 (10h)

- 0 0 0 1 0 0 0 1 (11h)

- 0 0 0 1 0 0 1 0 (12h)

- 0 0 0 1 0 0 1 1 (13h)

- 0 0 1 0 0 0 0 0 (20h)

- 0 0 1 0 0 0 0 1 (21h)

- 0 0 1 0 0 1 1 0 (26h)

- - - - - GC3 GC2 GC1 GC0

- 0 0 1 0 1 0 0 0 (28h)

- 0 0 1 0 1 0 0 1 (29h)

- 0 0 1 0 1 0 1 0 (2Ah)

- XS15 XS14 XS13 XS12 XS11 XS10 XS9 XS8

- XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0

- XE15 XE14 XE13 XE12 XE11 XE10 XE9 XE8

- XE7 XE6 XE5 XE4 XE3 XE2 XE1 XE0

- 0 0 1 0 1 0 1 1 (2Bh)

- YS15 YS14 YS13 YS12 YS11 YS10 YS9 YS8

- YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0

- YE15 YE14 YE13 YE12 YE11 YE10 YE9 YE8

- YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0

- 0 0 1 0 1 1 0 0 (2Ch)

- D7 D6 D5 D4 D3 D2 D1 D0

- 0 0 1 0 1 1 0 1 (2Dh)

- - - R005 R004 R003 R002 R001 R000

- - - : : : : : :

- - Ra5 Ra4 Ra3 Ra2 Ra1 Ra0

-

- - - G005 G004 G003 G002 G001 G000

- - - : : : : : :

- - - Gb5 Gb4 Gb3 Gb2 Gb1 Gb0

- - - B005 B004 B003 B002 B001 B000

- - - : : : : : :

- - - Bc5 Bc4 Bc3 Bc2 Bc1 Bc0

- 0 0 1 0 1 1 1 0 (2Eh)

Function

X address start: 0≦XS≦X

X address end: S≦XE≦X

Y address start: 0≦YS≦Y

Y address end:S≦YE≦Y

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ST7735R

WRX

↑ 1

Partial start/end address set

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

Tearing effect line off

↑ 1

Tearing effect mode set & on

↑ 1

↑ 1

Memo

ry data access control

↑ 1

-

↑ 1

Idle mode off

↑ 1

I

dle mode on

↑ 1

Interface pixel format

↑ 1

Interface format

↑ 1

Read ID1

↑

Dummy read

↑

Read parameter

↑ 1

Read ID2

↑

Dummy read

↑

Read parameter

↑ 1

Read ID3

↑

Dummy read

↑

Read parameter

Table 10.1.3 System Function command List (3)

Instruction Refer

PTLAR 10.1.24

TEOFF 10.1.25

TEON 10.1.26

MADCTL 10.1.27

IDMOFF 10.1.28

IDMON 10.1.29

COLMOD 10.1.30

RDID1 10.1.31

RDID2 10.1.32

RDID3 10.1.33

D/CX

0
1
1
1
1
0
0

1

0
1
0
0
0
1
0
1 1
1 1
0
1 1
1 1
0
1 1
1 1

RDXD17-8 D7 D6 D5 D4 D3 D2 D1 D0 Hex

- 0 0 1 1 0 0 0 0 (30h)

- PSL15 PSL14 PSL13PSL12 PSL11 PSL10PSL9 PSL8

- PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0

- PEL15 PEL14 PEL13PEL12 PEL11 PEL10PEL9 PEL8

- PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0

- 0 0 1 1 0 1 0 0 (34h)

- 0 0 1 1 0 1 0 1 (35h)

- - - - - - - - TEM

- 0 0 1 1 0 1 1 0 (36h)

- MY MX MV ML RGB MH - -

- 0 0 1 1 1 0 0 0 (38h)

- 0 0 1 1 1 0 0 1 (39h)

- 0 0 1 1 1 0 1 0 (3Ah)

- - - - - - IFPF2 IFPF1IFPF0

- 1 1 0 1 1 0 1 0 (DAh)

- - - - - - - - -

- ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10

- 1 1 0 1 1 0 1 1 (DBh)

- - - - - - - - -

- 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20

- 1 1 0 1 1 1 0 0 (DCh)

- - - - - - - - -

- ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30

Partial start address (0,1,2, ..P)

Partial end address (0,1,2, .., P)

Mode1: TEM=”0”
Mode2: TEM=”1”

Function

“-“: Don’t care

Note 1: After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer

“RESET TABLE” section)
Note 2: Undefined commands are treated as NOP (00 h) command.
Note 3: B0 to D9 and DA to F are for factory use of driver supplier.
Note 4: Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML parameter only), 37h, 38h and 39h are updated during

V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated

immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTL (0Bh), Read Display Pixel Format

(0Ch), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh).

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ST7735R

10.1.1 NOP (00h)

00H NOP (No Operation)

Inst / Para

NOP

Parameter

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 0 0 0 0 0 0 (00h)

No Parameter

-

Description

“-“ Don’t care

This command is empty command.

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ST7735R

10.1.2 SWRESET (01h): Software Reset

01H SWRESET (Software Reset)

Inst / Para

SWRESET

Parameter

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 0 0 0 0 0 1 (01h)

No Parameter
“-“ Don’t care

-If Software Reset is applied during Sleep In mode, it will be necessary to wait 120msec before sending next command.

-

Description

Flow Chart

-The display module loads all default values to the registers during 120msec.

-If Software Reset is applied during Sleep Out or Display On Mode, it will be necessary to wait 120msec before sending
next command.

Legend

SWRESET

Display whole

blank screen

Set

Commands

to S/W

Default

Value

Command

Parameter

Display

Action

Sleep In Mode

Mode

Sequential

transter

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ST7735R

10.1.3 RDDID (04h): Read Display ID

04H RDDID (Read Display ID)

Inst / Para

RDDID

1st parameter

2nd parameter

3rd parameter
4th parameter

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 0 0 0 1 0 0 (04h)
1 1 ↑ - - - - - - - - - ­1 1 ↑ - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
1 1 ↑ - 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20
1 1 ↑ - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30

-This read byte returns 24-bit display identification information.

-The 1st parameter is dummy data

-The 2nd parameter (ID17 to ID10): LCD module’s manufacturer ID.

Description

Default

-The 3rd parameter (ID26 to ID20): LCD module/driver version ID

-The 4th parameter (ID37 to UD30): LCD module/driver ID.

-Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h,
respectively.
“-“ Don’t care

Status

Power On Sequence

S/W Reset
H/W Reset

Serial I/F Mode

Parallel I/F Mode

ID1 ID2 ID3

- NV Value NV Value

- NV Value NV Value

- NV Value NV Value

Default Value

Legend

Read 04h Read 04h

Command

Parameter

Dummy

Clock

Host

Display

Dummy

Read

Display

Flow Chart

Send 2nd

parameter

Send 3rd

parameter

Send 4th

parameter

Send 2nd

parameter

Send 3rd

parameter

Send 4th

parameter

Action

Mode

Sequential

transter

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ST7735R

ST24 For Future Use

‘0’

ST23 For Future Use

‘0’

IDMON

Idle Mode On/Off

‘1’ = On, “0” = Off

PTLON

Partial Mode On/Off

‘1’ = On, “0” = Off

SLPOUT

Sleep In/Out

‘1’ = Out, “0” =

In

ST15 Vertical Scrolling Status

(Not Used)

‘1’ = Scroll on,“0” = Scroll off

ST14 Horizontal Scroll Status

(Not Used)

‘0’

INVON

Inversion Status

‘1’ = On, “0” = Off

ST12 All Pixels On (Not Used)

‘0’

ST11 All Pixels Off (Not Used)

‘0’

10.1.4 RDDST (09h): Read Display Status

09H RDDST (Read Display Status)

Inst / Para

RDDST

1st parameter
2nd parameter
3rd parameter
4th parameter
5th parameter

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 0 0 1 0 0 1 (09h)
1 1 ↑ - - - - - - - - - ­1 1 ↑ - BSTON MY MX MV ML RGB MH ST24
1 1 ↑ - ST23 IFPF2 IFPF1 IFPF0 IDMON PTLON SLOUT NORON
1 1 ↑ - ST15 ST14 INVON ST12 ST11 DISON TEON GCS2
1 1 ↑ - GCS1 GCS0 TEM ST4 ST3 ST2 ST1 ST0

This command indicates the current status of the display as described in the table below:

Bit Description Value
BSTON Booster Voltage Status ‘1’ =Booster on,

‘0’ =Booster off

MY Row Address Order (MY) ‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7=’1’)

‘0’ =Increment, (Top to Bottom, when MADCTL (36h) D7=’0’)

MX Column Address Order (MX) ‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6=’1’)

‘0’ =Increment, (Left to Right, when MADCTL (36h) D6=’1’)

Description

MV Row/Column Exchange (MV) ‘1’ = Row/column exchange, (when MADCTL (36h) D5=’1’)

‘0’ = Normal, (when MADCTL (36h) D5=’0’

ML Scan Address Order (ML) ‘0’ =Decrement,

(LCD refresh Top to Bottom, when MADCTL (36h) D4=’0’)
‘1’=Increment,
(LCD refresh Bottom to Top, when MADCTL (36h) D4=’1’)

RGB RGB/ BGR Order (RGB) ‘1’ =BGR, (When MADCTL (36h) D3=’1’)

‘0’ =RGB, (When MADCTL (36h) D3=’0’)

MH Horizontal Order

IFPF2

Interface Color Pixel Format

IFPF1

Definition

IFPF0

‘0’ =Decrement,
(LCD refresh Left to Right, when MADCTL (36h) D2=’0’)
‘1’ =Increment,
(LCD refresh Right to Left, when MADCTL (36h) D2=’1’)

“011” = 12-bit / pixel,
“101” = 16-bit / pixel,
“110” = 18-bit / pixel, others are no define

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NORON

Display Normal Mode On/Off

‘1’ = Normal Display,
‘0’ = Partial Display

ST7735R

D

ISON Display On/Off

‘1’ = On, “0” = Off

TEON

Tearing effect line on/off

‘1’ = On, “0” = Off

TEM

Tearing effect line mode

‘0’ =

mode1, ‘1’ = mode2

ST4 For Future Use

‘0’

ST3 For Future Use

‘0’

ST2 For Future Use

‘0’

ST1 For Future Use

‘0’

Default

GCSEL2
GCSEL1

Gamma Curve Selection

GCSEL0

ST0 For Future Use ‘0’

“-“ Don’t care

Status Default Value (ST31 to ST0)
ST[31-24] ST[23-16] ST[15-8] ST[7-0]
Power On Sequence 0000-0000 0110-0001 0000-0000 0000-0000
S/W Reset 0xxx0xx00 0xxx-0001 0000-0000 0000-0000
H/W Reset 0000-0000 0110-0001 0000-0000 0000-0000

“000” = GC0
“001” = GC1
“010” = GC2
“011” = GC3
”100” to “111” = Not defined

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BSTON

IDMON

PTLON

SLPOUT

NORON

DISON

10.1.5 RDDPM (0Ah): Read Display Power Mode

0AH RDDPM (Read Display Power Mode)

Inst / Para

RDDPM

1st parameter
2nd parameter

D/CX WRX RDX D17-8 D7

0 ↑ 1 - 0 0 0 0 1 0 1 0 (0Ah)
1 1 ↑ - - - - - - - - - -

1 1 ↑
This command indicates the current status of the display as described in the table below:
“-“ Don’t care

Bit Description Value

D6

D5

D4

D3

D2

D1

D1

D0 HEX

D0

Description

Default

BSTON Booster Voltage Status

IDMON Idle Mode On/Off

PTLON Partial Mode On/Off

SLPON Sleep In/Out

NORON Display Normal Mode On/Off

DISON Display On/Off

D1 Not Used ‘0’
D0 Not Used ‘0’

Status Default Value (D7 to D0)
Power On Sequence 0000_1000(08h)
S/W Reset 0000_1000(08h)

‘1’ =Booster on,
‘0’ =Booster off
‘1’ = Idle Mode On,
‘0’ = Idle Mode Off
‘1’ = Partial Mode On,
‘0’ = Partial Mode Off
‘1’ = Sleep Out,
‘0’ = Sleep In
‘1’ = Normal Display,
‘0’ = Partial Display
‘1’ = Display On,
‘0’ = Display Off

H/W Reset 0000_1000(08h)

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10.1.6 RDDMADCTL (0Bh): Read Display MADCTL

0BH RDDMADCTL (Read Display MADCTL)

Inst / Para

RDDMADCTL

1st parameter
2nd parameter

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 0 0 1 0 1 1 (0Bh)
1 1 ↑ - - - - - - - - - -

1 1 ↑ MY MX MV ML RGB MH D1 D0
This command indicates the current status of the display as described in the table below:
“-“ Don’t care

Bit Description Value

Description

Default

MX Column Address Order

MY Row Address Order

MV Row/Column Order (MV)

ML Vertical Refresh Order

RGB RGB/BGR Order ‘1’ =BGR, “0”=RGB

MH Horizontal Refresh Order

D1 Not Used ‘0’
D0 Not Used ‘0’

Status Default Value (D7 to D0)
Power On Sequence 0000_0000 (00h)
S/W Reset No change

‘1’ = Right to Left (When MADCTL B6=’1’)
‘0’ = Left to Right (When MADCTL B6=’0’)
‘1’ = Bottom to Top (When MADCTL B7=’1’)
‘0’ = Top to Bottom (When MADCTL B7=’0’)
‘1’ = Row/column exchange (MV=1)
‘0’ = Normal (MV=0)
‘1’ =LCD Refresh Bottom to Top
‘0’ =LCD Refresh Top to Bottom

LCD horizontal refresh direction control
‘0’ = LCD horizontal refresh Left to right
‘1’ = LCD horizontal refresh right to left

H/W Reset 0000_0000 (00h)

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10.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format

0CH RDDCOLMOD (Read Display Pixel Format)

Inst / Para

RDDCOLMOD

1st parameter
2nd parameter

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 0 0 1 1 0 0 (0Ch)

1 1 ↑ - - - - - - - - - -

1 1 ↑ - 0 0 0 0 - IFPF2 IFPF1 IFPF0
This command indicates the current status of the display as described in the table below:

IFPF[2:0] MCU Interface Color Format
011 12-bit/pixel

Description

Default

101 16-bit/pixel
110 18-bit/pixel
111 No used

Others are no define and invalid
“-“ Don’t care

Status Default Value
IFPF[2:0]
Power On Sequence 0110 (18 bits/pixel)
S/W Reset No Change
H/W Reset 0110 (18 bits/pixel)

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10.1.8 RDDIM (0Dh): Read Display Image Mode

0DH RDDIM (0Dh): Read Display Image Mode

Inst / Para

RDDIM

1st parameter

2nd parameter

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 0 0 1 1 0 1 (0Dh)
1 1 ↑ - - - - - - - - - -

1 1 ↑ - VSSON D6 INVON D4 D3 GCS2 GCS1 GCS0
This command indicates the current status of the display as described in the table below:
“-“ Don’t care

Bit Description Value
VSSON Reversed “0”
D6 Reversed “0”

Description

Default

INVON Inversion On/Off

D4 All Pixels On “0” (Not used)
D3 All Pixels Off “0” (Not used)

GCS2
GCS1
GCS0

Status Default Value(D7 to D0)
Power On Sequence 0000_0000 (00h)
S/W Reset 0000_0000 (00h)
H/W Reset 0000_0000 (00h)

Gamma Curve Selection

“1” = Inversion is On,
“0” = Inversion is Off

“000” = GC0,
“001” = GC1,
“010” = GC2,
“011” = GC3, ”100” to “111” = Not defined

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10.1.9 RDDSM (0Eh): Read Display Signal Mode

0EH RDDSM (0Eh): Read Display Signal Mode

Inst / Para

RDDSM

1st parameter

2nd parameter

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 0 0 1 1 1 0 (0Eh)
1 1 ↑ - - - - - - - - - -

1 1 ↑ - TEON TEM D5 D4 D3 D2 D1 D0
This command indicates the current status of the display as described in the table below:
“-“ Don’t care

Bit Description Value
TEON Tearing Effect Line On/Off “1” = On,

TEM Tearing effect line mode “1” = mode2,

D5 Not Used “1” = On,

“0” = Off

“0” = mode1

“0” = Off

Description

Default

D4 Not Used “1” = On,

D3 Not Used “1” = On,

D2 Not Used “1” = On,

D1 Not Used “1” = On,

D0 Not Used “1” = On,

Status Default Value(D7~D0)
Power On Sequence 0000_0000 (00h)
S/W Reset 0000_0000 (00h)
H/W Reset 0000_0000 (00h)

“0” = Off

“0” = Off

“0” = Off

“0” = Off

“0” = Off

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mode. Sleep In Mode can only be exit by the Sleep Out

When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command because of

10.1.10 SLPIN (10h): Sleep In

10H SLPIN (Sleep In)

Inst / Para

SLPIN

Parameter No Parameter -

Description

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 0 1 0 0 0 0 (10h)

-This command causes the LCD module to enter the minimum power consumption mode.

-In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped.

-This command has no effect when module is already in Sleep In

Restriction

Default

Command (11h).

­the stabilization timing for the supply voltages and clock circuits.

Status Default Value
Power On Sequence Sleep in mode
S/W Reset Sleep in mode
H/W Reset Sleep in mode

SLPIN

Stop

DC-DC

Converter

Display whole
blank screen

(Automatic No effect

to DISP ON/OFF

Commands)

Stop

Internal

Oscillator

Legend

Command

Parameter

Display

Flow Chart

Drain

Charge

From LCD

Panel

Sleep In Mode

Action

Mode

Sequential

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fect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In

When IC is in Sleep In mode, it is necessary to wait 120msec before sending next command because of the stabilization

10.1.11 SLPOUT (11h): Sleep Out

11H SLPOUT (Sleep Out)

Inst / Para

SLPOUT

Parameter No Parameter -

Description

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 0 1 0 0 0 1 (11h)

-This command turns off sleep mode.

-In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started.

-This command has no ef
Command (10h).

Restriction

Default

­timing for the supply voltages and clock circuits.

-When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command due to the
download of default value of registers and the execution of self-diagnostic function.

Status Default Value
Power On Sequence Sleep in mode
S/W Reset Sleep in mode
H/W Reset Sleep in mode

Legend

SLPOUT

Start

Internal

Oscillator

Display whole blank
screen for 2 firames

(Automatic No effect

to DISP ON/OFF

Commands)

Command

Parameter

Flow Chart

Start up

DC:DC

Converter

Charge

Offset

voltage for

LCD

Panel

Display Memory

contents In

accordance with

the current

command table

settings

Sleep Out mode

Display

Action

Mode

Sequential

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10.1.12 PTLON (12h): Partial Display Mode On

12H PTLON (12h): Partial Display Mode On

Inst / Para

PTLON

Parameter No Parameter -

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 0 1 0 0 1 0 (12h)

-This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h)

Description

Flow Chart

Default

-To leave Partial mode, the Normal Display Mode On command (13h) should be written.
“-“ Don’t care

Status Default Value

Power On Sequence Normal Mode On

S/W Reset Normal Mode On
H/W Reset Normal Mode On

See Partial Area (30h)

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10.1.13 NORON (13h): Normal Display Mode On

13H NORON (Normal Display Mode On)

Inst / Para

NORON

Parameter No Parameter -

D/CX WRX RDX D17-8

0 ↑ 1 - 0 0 0 1 0 0 1 1 (13h)

-This command returns the display to normal mode.

D7 D6 D5 D4 D3 D2 D1 D0 HEX

Description

Flow Chart

Default

-Normal display mode on means Partial mode off.

-Exit from NORON by the Partial mode On command (12h)
“-“ Don’t care

Status Default Value

Power On Sequence Normal Mode On

S/W Reset Normal Mode On
H/W Reset Normal Mode On

See Partial Area Definition Descriptions for details of when to use this command

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10.1.14 INVOFF (20h): Display Inversion Off

20H IVNOFF (Normal Display Mode Off)

Inst / Para

INVOFF

Parameter No Parameter -

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 1 0 0 0 0 0 (20h)

-This command is used to recover from display inversion mode.

Description

Default

“-“ Don’t care

(Example)

Top-Left
(0,0)

Status Default Value

Power On Sequence Display Inversion off

S/W Reset Display Inversion off
H/W Reset Display Inversion off

Memory Display

Legend

Command

Display

Inversion On

Mode

Parameter

Flow Chart

INVOFF (20h)

Display

Inversion OFF

Mode

Display

Action

Mode

Sequential

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10.1.15 INVON (21h): Display Inversion On

21H IVNOFF (Display Inversion On)

Inst / Para

INVON

Parameter No Parameter -

Description

Default

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 1 0 0 0 0 1 (21h)

-This command is used to enter into display inversion mode

-To exit from Display Inversion On, the Display Inversion Off command (20h) should be written.
“-“ Don’t care

Top-Left (0,0)

Power On Sequence Display Inversion off

S/W Reset Display Inversion off
H/W Reset Display Inversion off

(Example)
Memory

Display

Status Default Value

Flow Chart

Display

Inversion OFF

Mode

INVON (21h)

Display

Inversion ON

Mode

Legend

Command

Parameter

Display

Action

Mode

Sequential

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10.1.16 GAMSET (26h): Gamma Set

26H GAMSET (Gamma Set)

Inst / Para

GAMSET

Parameter

Description

Default

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 1 0 0 1 1 0 (26h)
1 ↑ 1 - - - - - GC3 GC2 GC1 GC0

-This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be
selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table.

GC [7:0] Parameter Curve Selected

GS=1 GS=0
01h GC0 Gamma Curve 1 (G2.2) Gamma Curve 1 (G1.0)
02h GC1 Gamma Curve 2 (G1.8) Gamma Curve 2 (G2.5)
04h GC2 Gamma Curve 3 (G2.5) Gamma Curve 3 (G2.2)
08h GC3 Gamma Curve 4 (G1.0) Gamma Curve 4 (G1.8)

Note: All other values are undefined.

Status Default Value

Power On Sequence 01h

S/W Reset 01h
H/W Reset 01h

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10.1.17 DISPOFF (28h): Display Off

28H DISPOFF (Display Off)

Inst / Para

DISPOFF

Parameter No Parameter -

Description

D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

0 ↑ 1 - 0 0 1 0 1 0 0 0 (28h)

- This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is
disabled and blank page inserted.

- This command makes no change of contents of frame memory.

- This command does not change any other status.

- There will be no abnormal visible effect on the display.

- Exit from this command by Display On (29h)

(Example)

Memory Display

Default

Flow Chart

Status Default Value

Power On Sequence Display off

S/W Reset Display off
H/W Reset Display off

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