Sitronix ST7715 User Manual

ST

This controller datasheet was downloaded from http://www.crystalfontz.com/controllers/

Crystalfontz

Sitronix ST7715

262K Color Single-Chip TFT Controller/Driver

1 Introduction

The ST7715 is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 396 source line and 132
gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial
Peripheral Interface (SPI), 8-bit/9-bit/16-bit/18-bit parallel interface. Display data can be stored in the on-chip display data
RAM of 132 x 132 x 18 bits. It can perform display data RAM read/write operation with no external operation clock to
minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal,
it is possible to make a display system with fewer components.

2 Features

Single chip TFT-LCD Controller/Driver with RAM
On-chip Display Data RAM (i.e. Frame Memory)

- 132 (H) x RGB x 132 (V) bits

LCD Driver Output Circuits:

- Source Outputs: 132 RGB channels

- Gate Outputs: 132 channels

Display Resolution

- 132 (RGB) x 132
(GM[2:0]= ”001”, DDRAM: 132 x 18-bits x 132)

Display Colors (Color Mode)

- Full Color: 262K, RGB=(666) max., Idle Mode OFF

- Color Reduce: 8-color, RGB=(111), Idle Mode ON

Programmable Pixel Color Format (Color Depth) for
Various Display Data input Format

- 12-bit/pixel: RGB=(444) using the 384k-bit frame

memory and LUT

- 16-bit/pixel: RGB=(565) using the 384k-bit frame

memory and LUT

- 18-bit/pixel: RGB=(666) using the 384k-bit frame

memory and LUT

Various Interfaces

- Parallel 8080-series MCU Interface
(8-bit, 9-bit, 16-bit & 18-bit)

- 3-line serial interface

- 4-line serial interface

Display Features

- Programmable partial display duty

- Line inversion, frame inversion

- Support both normal-black & normal-white LC

- Software programmable color depth mode

Built-in Circuits

- DC/DC converter

- Adjustable VCOM

- Non-volatile (NV) memory to store initial register setting

- Oscillator for display clock generation

- Factory default value (module ID, module version, etc)
are stored in NV memory

- Timing controller

Built-in NV Memory for LCD Initial Register Setting

- 7-bits for ID2

- 8-bits for ID3

- 7-bits for VCOM adjustment

Wide Supply Voltage Range

- I/O Voltage (VDDI to DGND): 1.65V~VDD

(VDDI ≤ VDD)

- Analog Voltage (VDD to AGND): 2.6V~3.3V

On-Chip Power System

- Source Voltage (GVDD to AGND): 3.0V~5.0V

- VCOM HIGH level (VCOMH to AGND): 2.5V to 5.0V

- VCOM LOW level (VCOML to AGND): -2.4V to 0.0V

- Gate driver HIGH level (VGH to AGND):
+10.0V to 15V

- Gate driver LOW level (VGL to AGND):

-12.4V to –7.5V

Operating Temperature: -30°C to +85°C

ST7715

Parallel Interface: 8-bit/9-bit/16-bit/18-bit
Serial Interface: 3-line/4-line

Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.

V1.2 1 2009-3-10

ST7715

3 Pad arrangement

3.1 Output Bump Dimension

Boundary (Include scribe Lane)

C K

H

J

Item Symbol Size

Bump pitch A 16 um

Bump width C 16 um

Bump height H 98 um

Bump gap1 (Vertical) J 19 um

Bump gap2 (Horizontal) K 16 um

L

A

Bump area C x H 1568 um2

Chip Boundary (include scribe Lane) L 59 um

V1.2 2 2009-03-10

ST7715

3.2 Input Bump Dimension

C2

H

Bump pitch 1 A1 67 um

Bump pitch 2 A2 50 um
Bump width 1 C1 35 um
Bump width 2 C2 40 um

Bump height H 90 um

Bump gap K 20 um

Bump gap1 K1 15 um

C2

K

Item Symbol Size

A1

K2

L

A2

K1 K1

Boundary (Include scribe Lane)

C1

Bump gap2 K2 32 um
Bump area 1 C1 X H 3150 um2
Bump area 2 C2 X H 3690 um2

Chip Boundary(include scribe Lane) L 59 um

V1.2 3 2009-03-10

ST7715

3.3 Alignment Mark Dimension

10 5

20 1515 1515

3.4 Chip Information

Chip size (um x um): 9900 x 670
PAD coordinate: pad center
Coordinate origin: chip center
Chip thickness (um): 300 (TYP)
Bump height (um): 15 (TYP)
Bump hardness (HV): 75 (TYP)

20 1515 1515
80

105

80

2015 1515 15

80

2015 1515 15
80

V1.2 4 2009-03-10

ST7715

1 DUMMY

-4750 -231 51 VDD -

2250 -

231 101 DGND

550 -

231

2 VDDIO

-4700 -

231 52 VDD -

2200 -

231 102 DGND

600 -

231

3 EXTC

-4650 -

231 53 VDD -

2150 -

231 103 VDDI 650 -

231

4 DGNDO

-4600 -

231 54 VDD -

2100 -

231 104 VDDI 700 -

231

5 IM0 -

4550 -

231 55 VDD -

2050 -

231 105 VDDI 750 -

231

6 VDDIO

-4500 -

231 56 VDD -

2000 -

231 106 VDDI 800 -

231

7 IM1 -

4450 -

231 57 AGND

-1950 -

231 107 VDDI 850 -

231

8 DGNDO

-4400 -

231 58 AGND

-1900 -

231 108 VDDI 900 -

231

9 DUMMY

-4350 -

231 59 AGND

-1850 -

231 109 VCC 950 -

231

10 VDDIO

-4300 -

231 60 AGND

-1800 -

231 110 VCC 1000 -

231

11 TPI[1]

-4250 -

231 61 AGND

-1750 -

231 111 VCCO

1050 -

231

12 DGNDO

-4200 -

231 62 AGND

-1700 -

231 112 VCI1 1100 -

231

13 TPI[2]

-4150 -

231 63 RDX -

1630 -

231 113 VCI1 1150 -

231

14 VDDIO

-4100 -

231 64 D/CX -

1570 -

231 114 VCI1 1200 -

231

15 SRGB

-4050 -

231 65 TESEL

-1510 -

231 115 VREF

1250 -

231

16 DGNDO

-4000 -

231 66

DGNDO

-1450 -

231 116 VREF

1300 -

231

17 SMX -

3950 -

231 67 D17 -

1390 -

231 117 VREF

1350 -

231

18 VDDIO

-3900 -

231 68 D16 -

1330 -

231 118 DUMMY

1400 -

231

19 SMY -

3850 -

231 69 D15 -

1270 -

231 119 DUMMY

1450 -

231

20 DGNDO

-3800 -

231 70 D14 -

1210 -

231 120 AVDD

1500 -

231

21 DUMMY

-3750 -

231 71 D13 -

1150 -

231 121 AVDD

1550 -

231

22 VDDIO

-3700 -

231 72 D12 -

1090 -

231 122 AVDD

1600 -

231

23 DUMMY

-3650 -

231 73 D11 -

1030 -

231 123 AVDD

O 1650 -

231

24 DGNDO

-3600 -

231 74 D10 -

970 -

231 124 AVDD

O 1700 -

231

25 DUMMY

-3550 -

231 75 D9 -

910 -

231 125 GVDD

1750 -

231

26 VDDIO

-3500 -

231 76 D8 -

850 -

231 126 GVDD

1800 -

231

27 DUMMY

-3450 -

231 77 D1 -

790 -

231 127 GVDD

1850 -

231

28 DGNDO

-3400 -

231 78 D3 -

730 -

231 128 DUMMY

1900 -

231

29 DUMMY

-3350 -

231 79 D5 -

670 -

231 129 DUMMY

1950 -

231

30 VDDIO

-3300 -

231 80 D7 -

610 -

231 130 C11P

2000 -

231

31 LCM -

3250 -

231 81 TE -

550 -231 131 C11P

2050 -

231

32 DGNDO

-3200 -

231 82 RESX

-490 -

231 132 C11P

2100 -

231

33 DUMMY

-3150 -

231 83 CSX -

430 -

231 133 C11P

2150 -

231

34 VDDIO

-3100 -

231 84 D6 -

370 -

231 134 C11N

2200 -

231

35 GM2 -

3050 -

231 85 D4 -

310 -

231 135 C11N

2250 -

231

36 DGNDO

-3000 -

231 86 D2 -

250 -

231 136 C11N

2300 -

231

37 GM1 -

2950 -

231 87 IM2 -

190 -

231 137 C11N

2350 -

231

38 VDDIO

-2900 -

231 88 D0 -

130 -

231 138 C12P

2400 -

231

39 GM0 -

2850 -

231 89 WRX -70 -231 139 C12P

2450 -

231

40 DGNDO

-2800 -

231 90 DU

MMY 0 -

231 140 C12P

2500 -

231

41 DUMMY

-2750 -

231 91

DUMMY

50 -231 141 C12P

2550 -

231

42 CS -

2700 -

231 92

DUMMY

100 -

231 142 C12N

2600 -

231

43 SPI4W

-2650 -

231 93

DUMMY

150 -

231 143 C12N

2650 -

231

44 VDDIO

-2600 -

231 94

TPO[3]

200 -

231 144 C12N

2700 -

231

45 TPO[8]

-2550 -

231 95

TPO[2]

250 -

231 145 C12N

2750 -

231

46 TPO[7]

-2500 -

231 96

TPO[1]

300 -

231 146 AGND

2800 -

231

47 TPO[6]

-2450 -

231 97

DGND

350 -

231 147 AGND

2850 -

231

48 TPO[5]

-2400 -

231 98

DGND

400 -

231 148 AGND

2900 -

231

49 TPO[4]

-2350 -

231 99

DGND

450 -

231 149 VCL 2950 -

231

50 OSC -

2300 -

231

100 DGND

500 -

231 150 VCL 3000 -

231

4 Pad Center Coordinates

No. PAD Name

X Y No. PAD Name

X Y

No. PAD Name

X Y

V1.2 5 2009-03-10

ST7715

151

VCL 3050 -

231

201 DUMMYG

4532 227

251 G36 3732 227

152

C41P

3100 -

231 202 DUMMYG

4516 110

252 G34 3716 110

153

C41P

3150 -

231

203 G132 4500 227

253 G32 3700 227

154

C41P

3200 -

231

204 G130 4484 110

254 G30 3684 110

155

C41N

3250 -

231

205 G128 4468 227

255 G28 3668 227

156

C41N

3300 -

231

206 G126 4452 110

256 G26 3

652 110

157

C41N

3350 -

231

207 G124 4436 227

257 G24 3636 227

158

C22P

3400 -

231

208 G122 4420 110

258 G22 3620 110

159

C22P

3450 -

231

209 G120 4404 227

259 G20 3604 227

160 C22P

3500 -

231

210 G118 4388 110

260 G18 3588 110

161 C22N

3550 -

231

211 G116 4372 227

261 G16 3572 227

162 C22N

3600 -

231

212 G114 4356 110

262 G14 3556 110

163

C22N

3650 -

231

213 G112 4340 227

263 G12 3540 227

164

C23P

3700 -

231

214 G110 4324 110

264 G10 3524 110

165 C23P

3750 -

231

215 G108 4308 227

265 G8 3

508 227

166 C23P

3800 -

231

216 G106 4292 110

266 G6 3492 110

167 C23N

3850 -

231

217 G104 4276 227

267 G4 3476 227

168 C23N

3900 -

231

218 G102 4260 110

268 G2 3460 110

169 C23N

3950 -

231

219 G100 4244 227

269 DUMMY

3444 227

170

VGL 4000 -

231 220 G98 4228 110

270 DUMMY

3428 110

171

VGL 4050 -

231

221 G96 4212 227

271 DUMMY

3412 227

172 VGL 4100 -

231

222 G94 4196 110

272 DUMMY

3396 110

173 VGH 4150 -

231

223 G92 4180 227

273 S396 3380 227

174 VGH 4200 -

231

224 G90 4164 110

274 S395 3364

110

175 VGHO

4250 -

231

225 G88 4148 227

275 S394 3348 227

176 VCOMH

4300 -

231

226 G86 4132 110

276 S393 3332 110

177 VCOMH

4350 -

231

227 G84 4116 227

277 S392 3316 227

178 VCOMH

4400 -

231

228 G82 4100 110

278 S391 3300 110

179 VCOML

4450 -231

229 G80 4084 227

279 S390 3284 227

180 VCOML

4500 -

231

230 G78 4068 110

280 S389 3268 110

181 VCOML

4550 -

231

231 G76 4052 227

281 S388 3252 227

182 VCOM

4600 -

231

232 G74 4036 110

282 S387 3236 110

183 VCOM

4650 -

231

233 G72 4020 227

283 S

386 3220 227

184 VCOM

4700 -

231

234 G70 4004 110

284 S385 3204 110

185 DUMMY2

4750 -

231

235 G68 3988 227

285 S384 3188 227

186 DUMMY3

4772 110

236 G66 3972 110

286 S383 3172 110

187 DUMMY4

4756 227

237 G64 3956 227

287 S382 3156 227

188 DUMMYG

4740 110

238 G62 3940 110

288 S381 3140 110

189 DUMMYG

4724 227

239 G60 3924 227

289 S380 3124 227

190 DUMMYG

4708 110

240 G58 3908 110

290 S379 3108 110

191 DUMMYG

4692 227

241 G56 3892 227

291 S378 3092 227

192 DUMMYG

4676 110

242 G54 3876 110

292 S377 3076 110

193 DUMMYG

4660 227

243 G52 3860 227

293 S376 3060 227

194 DUMMYG

4644 110

244 G50 3844 110

294 S375 3044 110

195 DUMMYG

4628 227

245 G48 3828 227

295 S374 3028 227

196 DUMMYG

4612 110

246 G46 3812 110

296 S373 3012 110

197 DUMMYG

4596 227

247 G44 3796 227

297 S372 2996 227

198 DUMMYG

4580 110

248 G42 3780 110

298 S371 2980 110

199 DUMMYG

4564 227

249 G40 3764 227

299 S370 2964 227

200 DUMMYG

4548 110

250 G38 3748 110

300 S369 2948 110

No. PAD Name

X Y

No. PAD Name

X Y

No. PAD Name

X Y

V1.2 6 2009-03-10

ST7715

301

S368 2932 227 351 S318 2132 227

401 S268 1332 227

302

S367 2916 110 352 S317 2116 110

402 S267 1316 110

303

S366 2900 227 353 S316 2100 227

403 S266 1300 227

304

S365 2884 110 354 S315 2084 110

404 S265 1284 110

305

S364 2868 227 355 S314 2068 227

405 S264 1268 227

306

S363 2852 110 356 S313 2052 110

406 S263 1252 110

307

S362 2836 227 357 S312 2036 227

407 S262 1236 227

308

S361 2820 110 358 S311 2020 110

408 S261 1220 110

309

S360 2804 227 359 S310 2004 227

409 S260 1204 227

310

S359 2788 110 360 S309 1988 110

410 S259 1188 110

311

S358 2772 227 361 S308 1972 227

411 S258 1172 227

312

S357 2756 110 362 S307 1956 110

412 S257 1156 110

313

S356 2740 227 363 S306 1940 227

413 S256 1140 227

314

S355 2724 110 364 S305 1924 110

414 S255 1124 110

315

S354 2708 227 365 S304 1908 227

415 S254 1108 227

316

S353 2692 110

366 S303 1892 110

416 S253 1092 110

317

S352 2676 227 367 S302 1876 227

417 S252 1076 227

318

S351 2660 110 368 S301 1860 110

418 S251 1060 110

319

S350 2644 227 369 S300 1844 227

419 S250 1044 227

320

S349 2628 110 370 S299 1828 110

420 S249 1028 110

321

S348 2612 227 371 S298 1812 227

421 S248 1012 227

322

S347 2596 110 372 S297 1796 110

422 S247 996 110

323

S346 2580 227 373 S296 1780 227

423 S246 980 227

324

S345 2564 110 374 S295 1764 110

424 S245 964 110

325

S344 2548 227 375 S294 1748 227

425 S244 948 227

326

S343 2532 110 376 S293 1732 110

426 S243 932 110

327

S342 2516 227 377 S292

1716 227

427 S242 916 227

328

S341 2500 110 378 S291 1700 110

428 S241 900 110

329

S340 2484 227 379 S290 1684 227

429 S240 884 227

330

S339 2468 110 380 S289 1668 110

430 S239 868 110

331

S338 2452 227 381 S288 1652 227

431 S238 852 227

332 S337 2436 110 382 S287 1636 110

432 S237 836 110

333

S336 2420 227 383 S286 1620 227

433 S236 820 227

334

S335 2404 110 384 S285 1604 110

434 S235 804 110

335

S334 2388 227 385 S284 1588 227

435 S234 788 227

336

S333 2372 110 386 S283 1572 110 436 S233 772 110

337

S332 2356 227 387 S282 1556 227

437 S232 756 227

338

S331 2340 110 388 S281 1540 110

438 S231 740 110

339

S330 2324 227 389 S280 1524 227

439 S230 724 227

340

S329 2308 110 390 S279 1508 110

440 S229 708 110

341

S328 2

292 227

391 S278 1492 227

441 S228 692 227

342

S327 2276 110

392 S277 1476 110

442 S227 676 110

343

S326 2260 227

393 S276 1460 227

443 S226 660 227

344

S325 2244 110

394 S275 1444 110

444 S225 644 110

345

S324 2228 227

395 S274 1428 227

445 S224 628 227

346

S323 2212 110

396 S273 1412 110

446 S223 612 110

347

S322 2196 227

397 S272 1396 227

447 S222 596 227

348

S321 2180 110

398 S271 1380 110

448 S221 580 110

349

S320 2164 227

399 S270 1364 227

449 S220 564 227

350

S319 2148 110

400 S269 1348 110

450 S219 548 110

No. PAD Name

X Y No. PAD Name

X Y

No. PAD Name

X Y

V1.2 7 2009-03-10

ST7715

451 S218 532 227

501 S172 -

644 110

551 S122 -

1444 110

452 S217 516 110

502 S171 -

660 227

552 S121 -

1460 227

453 S216 500 227

503 S170 -

676 110

553 S120 -

1476 110

454 S215 484 110

504 S169 -

692 227

554 S119 -

1492 227

455 S214 468 227

505 S168 -

708 110

555 S118 -

1508 110

456 S213 452 110

506 S167 -

724 227

556 S117 -

1524 227

457 S212 436 227

507 S166 -

740 110

557 S116 -

1540 110

458 S211 420 110

508 S165 -

756 227

558 S115 -

1556 227

459 S210 404 227

509 S164 -

772 110

559 S114 -

1572 110

460 S209 388 110

510 S163 -

788 227

560 S113 -

1588 227

461 S208 372 227

511 S162 -

804 110

561 S112 -

1604 110

462 S207 356 110

512 S161 -

820 227

562 S111 -

1620 227

463 S206 340 227

513 S160 -

836 110

563 S110 -

1636 110

464 S205 324 110

514 S159 -

852 227

564 S109 -

1652 227

465 S204 308 227

515 S158 -

868 110

565 S108 -

1668 110

466 S203 292 110

516 S157 -

884 227

566 S107 -

1684 227

467 S202 276 227

517 S156 -

900 110

567 S106 -

1700 110

468 S201 260 110

518 S155 -

916 227

568 S105 -

1716 227

469 S200 244 227

519 S154 -

932 110

569 S104 -

1732 110

470 S199 228 110

520 S153 -

948 227

570 S103 -

1748 227

471 DUMMY

212 227

521 S152 -

964 110

571 S102 -1764 110

472 DUMMY

196 110

522 S151 -

980 227

572 S101 -

1780 227

473 DUMMY

-196 110

523 S150 -

996 110

573 S100 -

1796 110

474 DUMMY

-212 227

524 S149 -

1012 227

574 S99 -

1812 227

475 S198 -

228 110

525 S148 -

1028 110

575 S98 -

1828 110

476 S197 -

244 227

526 S147 -

1044 227

576 S97 -

1844 227

477 S196 -

260 110

527 S146 -

1060 110

577 S96 -

1860 110

478 S195 -

276 227

528 S145 -

1076 227

578 S95 -

1876 227

479 S194 -

292 110

529 S144 -

1092 110

579 S94 -

1892 110

480 S193 -

308 227

530 S143 -

1108 227

580 S93 -

1908 227

481 S192 -

324 110

531 S142 -

1124 110

581 S92 -

1924 110

482 S191 -

340 227

532 S141 -

1140 227

582 S91 -

1940 227

483 S190 -

356 110

533 S140 -

1156 110

583 S90 -

1956 110

484 S189 -

372 227

534 S139 -

1172 227

584 S89 -

1972 227

485 S188 -

388 110

535 S138 -

1188 110

585 S88 -

1988 110

486 S187 -

404 227

536 S137 -

1204 227

586 S87 -

2004 227

487 S186 -

420 110

537 S136 -

1220 110

587 S86 -

2020 110

488 S185 -

436 227

538 S135 -

1236 227

588 S85 -

2036 227

489 S184 -

452 110

539 S134 -

1252 110

589 S84 -

2052 110

490 S183 -

468 227

540 S133 -

1268 227

590 S83 -

2068 227

491 S182 -

484 110

541 S132 -

1284 110

591 S82 -

2084 110

492 S181 -

500 227

542 S131 -

1300 227

592 S81 -

2100 227

493 S180 -

516 110

543 S130 -

1316 110

593 S80 -

2116 110

494 S179 -

532 227

544 S129 -

1332 227

594 S79 -

2132 227

495 S178 -

548 110

545 S128 -

1348 110

595 S78 -

2148 110

496 S177 -

564 227

546 S127 -

1364 227

596 S77 -

2164 227

497 S176 -

580 110

547 S126 -

1380 110

597 S76 -

2180 110

498 S175 -

596 227

548 S125 -

1396 227

598 S75 -

2196 227

499 S174 -

612 110

549 S124 -

1412 110

599 S74 -

2212 110

500 S173 -

628 227

550 S123 -

1428 227

600 S73 -

2228 227

No. PAD Name

X Y No. PAD Name

X Y

No. PAD Name

X Y

V1.2 8 2009-03-10

ST7715

601 S72 -

2244 110

651 S22 -

3044 110

701 G49 -

3844 110

602 S71 -

2260 227

652 S21 -

3060 227

702 G51 -

3860 227

603 S70 -

2276 110

653 S20 -

3076 110

703 G53 -

3876 110

604 S69 -

2292 227

654 S19 -

3092 227

704 G55 -

3892 227

605 S68 -

2308 110

655 S18 -

3108 110

705 G57 -

3908 110

606 S67 -

2324 227

656 S17 -

3124 227

706 G59 -

3924 227

607 S66 -

2340 110

657 S16 -

3140 110

707 G61 -

3940 110

608 S65 -

2356 227

658 S15 -

3156 227

708 G63 -

3956 227

609 S64 -

2372 110

659 S14 -

3172 110

709 G65 -

3972 110

610 S63 -

2388 227

660 S13 -

3188 227

710 G67 -

3988 227

611 S62 -

2404 110

661 S12 -

3204 110

711 G69 -

4004 110

612 S61 -

2420 227

662 S11 -

3220 227

712 G71 -

4020 227

613 S60 -

2436 110

663 S10 -

3236 110

713 G73 -

4036 110

614 S59 -

2452 227

664 S9 -

3252 227

714 G75 -

4052 227

615 S58 -

2468 110

665 S8 -

3268 110

715 G77 -

4068 110

616 S57 -

2484 227

666 S7 -

3284 227

716 G79 -

4084 227

617 S56 -

2500 110

667 S6 -

3300 110

717 G81 -

4100 110

618 S55 -

2516 227

668 S5 -

3316 227

718 G83 -

4116 227

619 S54 -

2532 110

669 S4 -

3332 110

719 G85 -

4132 110

620 S53 -

2548 227

670 S3 -

3348 227

720 G87 -

4148 227

621 S52 -

2564 110

671 S2 -

3364 110

721 G89 -

4164 110

622 S51 -

2580 227

672 S1 -

3380 227

722 G91 -

4180 227

623 S50 -

2596 110

673 DUMMY

-3396 110

723 G93 -

4196 110

624 S49 -

2612 227

674 DUMMY

-3412 227

724 G95 -

4212 227

625 S48 -

2628 110

675 DUMMY

-3428 110

725 G97 -

4228 110

626 S47 -

2644 227

676 DUMMY

-3444 227

726 G99 -

4244 227

627 S46 -

2660 110

677 G1 -

3460 110

727 G101 -

4260 110

628 S45 -

2676 227

678 G3 -

3476 227

728 G103 -

4276 227

629 S44 -

2692 110

679 G5 -

3492 110

729 G105 -

4292 110

630 S43 -

2708 227

680 G7 -

3508 227

730 G107 -

4308 227

631 S42 -

2724 110

681 G9 -

3524 110

731 G109 -

4324 110

632 S41 -

2740 227

682 G11 -

3540 227

732 G111 -

4340 227

633 S40 -2756 110

683 G13 -

3556 110

733 G113 -

4356 110

634 S39 -

2772 227

684 G15 -

3572 227

734 G115 -

4372 227

635 S38 -

2788 110

685 G17 -

3588 110

735 G117 -

4388 110

636 S37 -

2804 227

686 G19 -

3604 227

736 G119 -

4404 227

637 S36 -

2820 110

687 G21 -3620 110

737 G121 -

4420 110

638 S35 -

2836 227

688 G23 -

3636 227

738 G123 -

4436 227

639 S34 -

2852 110

689 G25 -

3652 110

739 G125 -

4452 110

640 S33 -

2868 227

690 G27 -

3668 227

740 G127 -

4468 227

641 S32 -

2884 110

691 G29 -

3684 110

741 G129 -

4484 110

642 S31 -

2900 227

692 G31 -

3700 227

742 G131 -

4500 227

643 S30 -

2916 110

693 G33 -

3716 110

743 DUMMY

G -

4516 110

644 S29 -

2932 227

694 G35 -

3732 227

744 DUMMY

G -

4532 227

645 S28 -

2948 110

695 G37 -

3748 110

745 DUMMY

G -

4548 110

646 S27 -

2964 227

696 G39 -

3764 227

746 DUMMY

G -

4564 227

647 S26 -

2980 110

697 G41 -

3780 110

747 DUMMY

G -

4580 110

648 S25 -

2996 227

698 G43 -

3796 227

748 DUMMY

G -

4596 227

649 S24 -

3012 110

699 G45 -

3812 110

749 DUMMY

G -

4612 110

650 S23 -

3028 227

700 G47 -3828 227

750 DUMMY

G -

4628 227

No. PAD Name

X Y No. PAD Name

X Y

No. PAD Name

X Y

V1.2 9 2009-03-10

ST7715

751

DummyG

-4644 110

752

DummyG

-4660 227

753

DummyG

-4676 110

754

DummyG

-4692 227

755

DummyG

-4708 110

756

DummyG

-4724 227

757

DummyG

-4740 110

758

DUMMY

-4756 227

759

DUMMY

-4772 110

ALK-R 4841 -

220

ALK-L -

4841 -

220

No. PAD Name

X Y

V1.2 10 2009-03-10

ST7715

5 Block diagram

V1.2 11 2009-03-10

ST7715

6 Driver IC Pin Description

6.1 Power Supply Pin

Name

VDD I Power supply for analog, digital system and booster circuit. VDD

VDDI I Power supply for I/O system. VDDI
AGND
DGND

6.2 Interface logic pin

Name I/O Description Connect pin

IM2 I

IM1,IM0

I/O Description Connect pin

I System ground for analog system and booster circuit. GND
I System ground for I/O system and digital system. GND

MCU Parallel interface bus and Serial interface select
IM2=’1’, Parallel interface
IM2=’0’, Serial interface

- MCU parallel interface type selection

-If not used, please fix this pin at VDDI or DGND level.
IM1 IM0 Parallel interface

I

0 0 MCU 8-bit parallel
0 1 MCU 16-bit parallel

DGND/VDDI

DGND/VDDI

SPI4W

RESX I

CSX I

D/CX

(SCL)

RDX I

1 0 MCU 9-bit parallel
1 1 MCU 18-bit parallel

- SPI4W=’0’, 3-line SPI enable.

I

- SPI4W=’1’, 4-line SPI enable.

-If not used, please fix this pin at DGND level.

-This signal will reset the device and it must be applied to properly

initialize the chip.

-Signal is active low.

-Chip selection pin

-Low enable.

-Display data/command selection pin in MCU interface.

-D/CX=’1’: display data or parameter.

I

-D/CX=’0’: command data.

-In serial interface, this is used as SCL.

-If not used, please fix this pin at VDDI or DGND level.

-Read enable in 8080 MCU parallel interface.

-If not used, please fix this pin at VDDI or DGND level.

DGND/VDDI

MCU

MCU

MCU

MCU

WRX

(D/CX)

D[17:0] I/O -D[17:0] are used as MCU parallel interface data bus. MCU

V1.2 12 2009-03-10

-Write enable in MCU parallel interface.

I

-In 4-line SPI, this pin is used as D/CX (data/ command selection).

-If not used, please fix this pin at VDDI or DGND level.

MCU

ST7715

-D0 is the serial input/output signal in serial interface mode.

-In serial interface, D[17:1] are not used and should be fixed at VDDI or

DGND level.

-Tearing effect output pin to synchronies MCU to frame rate, activated

TE O

OSC O

Note1. When in parallel mode, no use data pin must be connected to “1” or “0”.
Note2. When CSX=”1”, there is no influence to the parallel and serial interface.

by S/W command.

-If not used, please open this pin.

-Monitoring pin of internal oscillator clock and is turned ON/OFF by

S/W command.

-When this pin is inactive (function OFF), this pin is DGND level.

-If not used, please open this pin.

MCU

-

V1.2 13 2009-03-10

ST7715

6.3 Mode selection pin

Name

EXTC

GM2,
GM1,
GM0

I/O Description Connect pin

-To use extended command set, please connect this pin to VDDI.

-During normal operation, please open this pin (internal
Rpull-down=2MΩ).

I

EXTC Enable/disable modification of extend command

Open

0 Only use default command set
1 Use EEPROM program set

-Panel resolution selection pins.
G

G

G

Selection of panel resolution

M

M

M

I

2

1

0

VDDI/DGND

0 0 1 132RGB x 132 (S1~S396 & G1~G132 output)

-RGB direction select H/W pin for color filter setting.

SRGB

SMX I

SMY I

SRGB RGB arrangement

I

0
1

S1, S2, S3 filter order = ’R’, ’G’, ’B’
S1, S2, S3 filter order = ‘B’, ‘G’, ‘R’

-Module source output direction H/W selection pin.

SMX Scanning direction of source output
GM= ‘001’
0 S1 -> S396
1 S396 -> S1

-Module Gate output direction H/W selection pin.

SMY Scanning direction of gate output
GM= ‘001’
0 G1 -> G132
1 G132 -> G1

-Liquid crystal (LC) type selection pins.

LCM Selection of LC type

VDDI/DGND

VDDI/DGND

VDDI/DGND

LCM I

0 Normally white LC type
1 Normally black LC type

VDDI/DGND

V1.2 14 2009-03-10

ST7715

GS I

TESEL

-Gamma curve selection pin.

GS Selection of gamma curve
0 GC0=1.0, GC1=2.5, GC2=2.2, GC3=1.8
1 GC0=2.2, GC1=1.8, GC2=2.5, GC3=1.0

Input pin to select horizontal line number in TE signal.

I

Connect this pin to DGND

VDDI/DGND

DGND

V1.2 15 2009-03-10

ST7715

6.4 Driver output pins

Name I/O

S1 to S396 O - Source driver output pins. -

G1 to G132 O - Gate driver output pins. -

VCI1 I/O - A reference voltage for step-up circuit 2. -

AVDD I

AVDDO O

VCL O

VGH I

VGHO O

- Power input pin for analog circuits.

- In normal usage, connect it to AVDDO.

- Output of step-up circuit 1

- Connect a capacitor for stabilization.

- A power supply pin for generating VCOML.

- Connect a capacitor for stabilization.

- Power input pin for gate driver circuit.

- In normal usage, connect it to VGHO.

- Positive output pin of the step-up circuit 2.

- Connect a capacitor for stabilization.

- Power input pin for gate driver circuit.

Description

Connect pin

AVDDO

Capacitor

Capacitor

VGHO

Capacitor

VGL I

VREF O - A reference voltage for power system. -

GVDD O

VCOMH O

VCOML O

VCOM O - A power supply for the TFT-LCD common electrode.

C11P, C11N O - Capacitor connecting pins for step-up circuit 1 (for AVDDO)

- Negative output of the step-up circuit 2 is connected inside the
driver.

- Connect a capacitor for stabilization.

- A power output of grayscale voltage generator.

- When internal GVDD generator is not used, connect an external
power supply (AVDD-0.5V) to this pin.

- Positive voltage output of VCOM.

- Connect a capacitor for stabilization.

- Negative voltage output of VCOM.

- Connect a capacitor for stabilization.

Capacitor

-

Capacitor

Capacitor

Common
electrode

Step-up

Capacitor

C22P, C22N
C23P, C23N
C41P, C41N

VDDIO O -VDDI voltage output level for monitoring. -

V1.2 16 2009-03-10

- Capacitor connecting pins for step-up circuit 2 and 4 (for VGHO,

O

VGL, VCL)

Step-up

Capacitor

ST7715

DGNDO O -DGND voltage output level for monitoring. -

VCC O

VCCO O

6.5 Test pins

Name I/O
TPI[2]

TPI[1]
TPO[8]
TPO[7]
TPO[6]
TPO[5]
TPO[4]
TPO[3]
TPO[2]
TPO[1]

-Power input pin for internal digital reference voltage.

-In normal usage, connect it to VCCO.

-Monitoring pin of internal digital reference voltage.

-Connect a capacitor for stabilization.

Description Connect pin

-These test pins for Driver vender test used.

I

-Please connect these pins to DGND.

-These test pins for Driver vender test used.

O

-Please open these pins.

VCCO

Capacitor

DGND

Open

Dummy -

DummyG - Vendor function Open

-These pins are dummy (have no function inside).
Open

-Can allow signal traces pass through these pads on TFT glass.

V1.2 17 2009-03-10

ST7715

7 Driver electrical characteristics

7.1 Absolute operation range

Item Symbol Rating Unit
Supply voltage VDD -0.3 ~ +4.6 V
Supply voltage (Logic) VDDI -0.3 ~ +4.6 V
Supply voltage (Digital) VCC -0.3 ~ +1.95 V
Driver supply voltage VGH-VGL -0.3 ~ +30.0 V
Logic input voltage range VIN 0.3 ~ VDDI +0.3 V
Logic output voltage range VO 0.3 ~ VDDI +0.3 V
Operating temperature range TOPR -30 ~ +85
Storage temperature range TSTG -40 ~ +125

Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be degraded. Absolute

maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the
product within the recommend range.

7.2 DC characteristic

Parameter Symbol Condition

Power & operation voltage
System voltage VDD Operating voltage
Interface operation

VDDI I/O supply voltage

voltage
Gate driver high

VGH 10 15 V

voltage
Gate driver low

VGL -12.4 -7.5 V

voltage

Specification

Unit

Min Typ Max

2.6 2.75 3.3 V

1.65 1.9 3.3 V

℃
℃

Related

Pins

Gate driver supply
voltage
Input / Output
Logic-high input
voltage
Logic-low input
voltage
Logic-high output
voltage
Logic-low output
voltage
Logic-high input
current

V1.2 18 2009-03-10

| VGH-VGL | 17.5 27.5 V

VIH 0.7VDDI

VIL VSS 0.3VDDI

VOH IOH = -1.0mA 0.8VDDI

VOL IOL = +1.0mA VSS 0.2VDDI

IIH VIN = VDDI 1 uA

VDDI V Note 1

V Note 1

VDDI V Note 1

V Note 1

Note 1

ST7715

Logic-low input
current
Input leakage
current
VCOM voltage
VCOM high voltage VCOMH Ccom=12nF 2.5 5.0 V
VCOM low voltage VCOML Ccom=12nF -2.4 0.0 V
VCOM amplitude VCOMAC |VCOMH-VCOML|
Source driver
Source output range
Gamma reference
voltage
Source output
settling time
Output offset voltage

Notes:

IIL VIN = VSS -1 uA

IIL IOH = -1.0mA -0.1 +0.1 uA

4.0 6.0 V

Vsout 0.1 AVDD-0.1 V

GVDD 3.0 5.0 V

Tr

Voffset 35 mV

Below with 99%

20 us Note 2

precision

Note 1

Note 1

Note 3

1. VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, TA= -30 to 85℃

2. Source channel loading= 2KΩ+12pF/channel, Gate channel loading=5KΩ+40pF/channel.

3. The Max. value is between measured point of source output and gamma setting value.

V1.2 19 2009-03-10

ST7715

7.3 Power consumption

VDD=2.8V, VDDI=1.8V, Ta=25℃, Frame rate = 60Hz, the registers setting are IC default setting.

Current consumption

Operation mode

Inversion

Image

mode

Typical Maximum
IDDI
(mA)

IDD
(mA)

IDDI
(mA)

Note 1 0.01 0.5 0.02 0.7

Normal mode One Line

Note 2 0.01 0.5 0.02 0.7
Note 1 0.01 0.3 0.02 0.5

Partial + Idle mode (40 lines) One Line

Note 2 0.01 0.3 0.02 0.5

Sleep-in mode N/A N/A 0.005 0.015 0.01 0.03

Notes:

1. All pixels black.

2. All pixels white.

3. The Current Consumption is DC characteristics. .

IDD
(mA)

V1.2 20 2009-03-10

ST7715

8 Timing chart

8.1 Parallel interface characteristics: 18, 16, 9 or 8-bit bus (8080 series MCU interface)

Fig. 8.1.1 Parallel interface timing characteristics (8080 series MCU interface)

Signal Symbol Parameter Min Max Unit Description

D/CX

CSX

WRX

RDX (ID)

TAST Address setup time 10 ns
TAHT Address hold time (Write/Read) 10 ns
TCHW Chip select “H” pulse width 0 ns
TCS Chip select setup time (Write) 15 ns
TRCS Chip select setup time (Read ID) 45 ns
TRCSFM Chip select setup time (Read FM) 350 ns
TCSF Chip select wait time (Write/Read) 10 ns
TCSH Chip select hold time 10 ns
TWC Write cycle 100 ns
TWRH Control pulse “H” duration 30 ns
TWRL Control pulse “L” duration 30 ns
TRC Read cycle (ID) 160 ns
TRDH Control pulse “H” duration (ID) 90 ns

-

-

When read ID data

TRDL Control pulse “L” duration (ID) 45 ns

RDX
(FM)

V1.2 21 2009-03-10

TRCFM Read cycle (FM) 450 ns

When read from frame

TRDHFM Control pulse “H” duration (FM) 150 ns

memory

TRDLFM Control pulse “L” duration (FM) 150 ns

ST7715

TDST Data setup time 10 ns
TDHT Data hold time 10 ns

D[17:0]

TRAT Read access time (ID) 40 ns
TRATFM Read access time (FM) 40 ns
TODH Output disable time 80 ns

Table 8.1.1 Parallel Interface Characteristics

Note: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 ℃

T

R

T

F

VIH=0.7 x VDDI

VIL=0.3 x VDDI

TR=TF<=15ns

Fig. 8.1.2 Rising and falling timing for input and output signal

T

R

VOL=0.2 x VDDI

TR=TF<=15ns

For CL=30pF

VOH=0.8 x VDDI

T

F

Fig. 8.1.3 Chip selection (CSX) timing

Fig. 8.1.4 Write-to-read and read-to-write timing

Note: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%

and 70% of VDDI for Input signals.

V1.2 22 2009-03-10

ST7715

8.2 Serial interface characteristics (3-line serial)

V

CSX

SCL

IH

V

IL

T

T

CSS

SCYCW/TSCYCR

T

T

SHW/TSHR

SLW/TSLR

T

CHW

T

CSH

T

V

SCC

IH

V

IL

SDA

SDA

(DOUT)

T

SDS

V

IH

V

IL

T

SDH

V

T

ACC

T

OH

V

IH

V

IL

IH

V

IL

Fig. 8.2.1 3-line serial interface timing

Signal Symbol Parameter Min Max Unit Description

TCSS Chip select setup time (write) 15 ns
TCSH Chip select hold time (write) 15 ns

CSX

TCSS Chip select setup time (read) 60 ns
TSCC Chip select hold time (read) 65 ns
TCHW Chip select “H” pulse width 40 ns
TSCYCW Serial clock cycle (Write) 66 ns
TSHW SCL “H” pulse width (Write) 30 ns
TSLW SCL “L” pulse width (Write) 30 ns

SCL

TSCYCR Serial clock cycle (Read) 150 ns
TSHR SCL “H” pulse width (Read) 60 ns
TSLR SCL “L” pulse width (Read) 60 ns
TSDS Data setup time 10 ns

SDA

TSDH Data hold time 10 ns

For maximum CL=30pF

(DIN)
(DOUT)

TACC Access time 10 50 ns

For minimum CL=8pF

TOH Output disable time 50 ns

Table 8.2.1 3-line Serial Interface Characteristics

Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 ℃
Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%

and 70% of VDDI for Input signals.

V1.2 23 2009-03-10

ST7715

8.3 Serial interface characteristics (4-line serial)

Fig. 8.3.1 4-line serial interface timing

Signal Symbol Parameter MIN MAX Unit Description

TCSS Chip select setup time (write) 15 ns
TCSH Chip select hold time (write) 15 ns

CSX

TCSS Chip select setup time (read) 60 ns
TSCC Chip select hold time (read) 65 ns
TCHW Chip select “H” pulse width 40 ns
TSCYCW Serial clock cycle (Write) 66 ns

-write command & data

TSHW SCL “H” pulse width (Write) 30 ns

ram

TSLW SCL “L” pulse width (Write) 30 ns

SCL

TSCYCR Serial clock cycle (Read) 150 ns

-read command & data

TSHR SCL “H” pulse width (Read) 60 ns

ram

TSLR SCL “L” pulse width (Read) 60 ns
TDCS D/CX setup time 0 ns

D/CX

TDCH D/CX hold time 10 ns
TSDS Data setup time 10 ns

SDA

TSDH Data hold time 10 ns

(DIN)

TACC Access time 10 50 ns

For maximum CL=30pF

(DOUT)

TOH Output disable time 50 ns

For minimum CL=8pF

Table 8.3.1 4-line Serial Interface Characteristics

Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 ℃
Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%

and 70% of VDDI for Input signals.

V1.2 24 2009-03-10

ST7715

9 Function description

9.1 Interface type selection

The selection of given interfaces are done by setting IM2, IM1, and IM0 pins as shown in following table.

IM2 IM1 IM0 Interface Read back selection
0 - - 3-line serial interface Via the read instruction
1 0 0 8080 MCU 8-bit parallel RDX strobe (8-bit read data and 8-bit read parameter)
1 0 1 8080 MCU 16-bit parallel RDX strobe (16-bit read data and 8-bit read parameter)
1 1 0 8080 MCU 9-bit parallel RDX strobe (9-bit read data and 8-bit read parameter)
1 1 1 8080 MCU 18-bit parallel RDX strobe (18-bit read data and 8-bit read parameter)

Table 9.1.1 Selection of MCU interface

IM2 IM1 IM0 Interface RDX WRX D/CX Read back selection
0 - - 3-line serial Note1 Note1 SCL D[17:1]: unused, D0: SDA
1 0 0 8080 8-bit parallel RDX WRX D/CX D[17:8]: unused, D7-D0: 8-bit data
1 0 1 8080 16-bit parallel RDX WRX D/CX D[17:16]: unused, D15-D0: 16-bit data
1 1 0 8080 9-bit parallel RDX WRX D/CX D[17:9]: unused, D8-D0: 9-bit data
1 1 1 8080 18-bit parallel RDX WRX D/CX D17-D0: 18-bit data

Table 9.1.2 Pin connection according to various MCU interface

Note1 Unused pins can be open, or connected to DGND or VDDI.

V1.2 25 2009-03-10

ST7715

9.2 8080-series MCU parallel interface

The MCU can use one of following interfaces: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface,
19-line with 16-data parallel interface or 21-lines with 18-data parallel interface. The chip-select CSX (active low)
enables/disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write enable,
RDX is the parallel data read enable and D[17:0] is parallel data bus.
The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX=’1’,
D[17:0] bits is either display data or command parameter. When D/C=’0’, D[17:0] bits is command.
The interface functions of 8080-series parallel interface are given in following table.

IM2 IM1 IM0 Interface D/CX RDX WRX

0 1 ↑ Write 8-bit command (D7 to D0)

1 0 0

1 0 1

1 1 0

1 1 1

8-bit

parallel

16-bit

parallel

9-bit

parallel

18-bit

parallel

1 1 ↑ Write 8-bit display data or 8-bit parameter (D7 to D0)
1 ↑ 1 Read 8-bit display data (D7 to D0)
1 ↑ 1 Read 8-bit parameter or status (D7 to D0)
0 1 ↑ Write 8-bit command (D7 to D0)
1 1 ↑ Write 16-bit display data or 8-bit parameter (D15 to D0)
1 ↑ 1 Read 16-bit display data (D15 to D0)
1 ↑ 1 Read 8-bit parameter or status (D7 to D0)
0 1 ↑ Write 8-bit command (D7 to D0)
1 1 ↑ Write 9-bit display data or 8-bit parameter (D8 to D0)
1 ↑ 1 Read 9-bit display data (D8 to D0)
1 ↑ 1 Read 8-bit parameter or status (D7 to D0)
0 1 ↑ Write 8-bit command (D7 to D0)
1 1 ↑ Write 18-bit display data or 8-bit parameter (D17 to D0)
1 ↑ 1 Read 18-bit display data (D17 to D0)
1 ↑ 1 Read 8-bit parameter or status (D7 to D0)

Read back selection

Table 9.2.1 the function of 8080-series parallel interface

Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh

V1.2 26 2009-03-10

ST7715

9.2.1 Write cycle sequence

The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write
cycle (WRX high-low-high sequence) consists of 3 control signals (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit
is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is
low (=’0’) and vice versa it is data (=’1’).

WRX

D[17:0]

The host starts to control D[17:0]
lines when there is a falling edge
of the WRX.

Fig. 9.2.1 8080-series WRX protocol

Note: WRX is an unsynchronized signal (It can be stopped).

D[17:0]

RESX

CSX

D/CX

RDX

WRX

1-byte

command

CMD CMD PA1 CMD PA

S P

“1”

“1”

2-byte

command

The display writes D[17:0] lines
when there is a rising edge of
WRX.

N-byte

command

1

The host stops to
control D[17:0] lines.

PA

PA

N-2

N-1

D[17:0]

Host D[17:0]
Host to LCD

Driver D[17:0]

CMD CMD PA1 CMD PA

S P

CMD CMD PA1 CMD PA

S P

Hi-Z

1

1

PA

PA

PA

N-2

N-2

PA

N-1

N-1

LCD to Host

CMD: write command code
PA: parameter or display data

Signals on D[17:0], D/CX, R/WX, E
pins during CSX=1 are ignored.

Fig. 9.2.2 8080-series parallel bus protocol, write to register or display RAM

9.2.2 Read cycle sequence

The read cycle (RDX high-low-high sequence) means that the host reads information from LCD driver via interface. The
driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising
edge of RDX.

V1.2 27 2009-03-10

ST7715

Fig. 9.2.3 8080-series RDX protocol

Note: RDX is an unsynchronized signal (It can be stopped).

Read parameter Read display data

D[17:0]

RESX

CSX

D/CX

RDX

WRX

D[17:0]

Host D[17:0]
Host to LCD

Driver D[17:0]

LCD to Host

CMD DM PA CMD DM & data Data DataS P

“1”

CMD DM PA CMD DM & data Data DataS P

CMD CMDS P

Hi-Z

CMD: write command code
PA: parameter or display data

Hi-Z Hi-Z

DM PA1 DM & data PA

Hi-Z

Signals on D[17:0], D/CX, R/WX, E
pins during CSX=1 are ignored.

PA

N-2

PS

N-1

Fig. 9.2.4 8080-series parallel bus protocol, read data from register or display RAM

V1.2 28 2009-03-10

ST7715

9.3 Serial interface

The selection of this interface is done by IM2. See the Table 9.3.1.

IM2 SPI4W Interface Read back selection
0 0 3-line serial interface Via the read instruction (8-bit, 24-bit and 32-bit read parameter)
0 1 4-line serial interface Via the read instruction (8-bit, 24-bit and 32-bit read parameter)

Table 9.3.1 Selection of serial interface
The serial interface is either 3-line/9-bit or 4-line/8-bit bi-directional interface for communication between the micro

controller and the LCD driver. The 3-line serial interface use: CSX (chip enable), SCL (serial clock) and SDA (serial data
input/output), and the 4-line serial interface use: CSX (chip enable), D/CX (data/ command flag), SCL (serial clock) and
SDA (serial data input/output). Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no
communication is necessary.

9.3.1 Command Write Mode

The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-line serial data
packet contains a control bit D/CX and a transmission byte. In 4-line serial interface, data packet contains just transmission
byte and control bit D/CX is transferred by the D/CX pin. If D/CX is “low”, the transmission byte is interpreted as a
command byte. If D/CX is “high”, the transmission byte is stored in the display data RAM (memory write command), or
command register as parameter.
Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is initialized when
CSX is high. In this state, SCL clock pulse or SDA data have no effect.
A falling edge on CSX enables the serial interface and indicates the start of data transmission.

Fig. 9.3.1 Serial interface data stream format
When CSX is “high”, SCL clock is ignored. During the high period of CSX the serial interface is initialized. At the falling

edge of CSX, SCL can be high or low (see Fig 9.3.2). SDA is sampled at the rising edge of SCL. D/CX indicates whether
the byte is command (D/CX=’0’) or parameter/RAM data (D/CX=’1’). D/CX is sampled when first rising edge of SCL (3-line
serial interface) or 8th rising edge of SCL (4-line serial interface). If CSX stays low after the last bit of command/data byte,
the serial interface expects the D/CX bit (3-line serial interface) or D7 (4-line serial interface) of the next byte at the next
rising edge of SCL.

V1.2 29 2009-03-10

ST7715

Fig. 9.3.2 3-line serial interface write protocol (write to register with control bit in transmission)

Fig. 9.3.3 4-line serial interface write protocol (write to register with control bit in transmission)

V1.2 30 2009-03-10

ST7715

9.3.2 Read Functions

The read mode of the interface means that the micro controller reads register value from the driver. To achieve read
function, the micro controller first has to send a command (read ID or register command) and then the following byte is
transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below
figure). The driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of
SCL. Thus the micro controller is supported to read at the rising edge of SCL.
After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL
of the last bit.

9.3.3 3-line serial protocol

3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):

3-line serial protocol (for RDDID command: 24-bit read)

3-line Serial Protocol (for RDDST command: 32-bit read)

Fig. 9.3.4 3-line serial interface read protocol

V1.2 31 2009-03-10

ST7715

9.3.4 4-line serial protocol

4-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):

4-line serial protocol (for RDDID command: 24-bit read)

4-line Serial Protocol (for RDDST command: 32-bit read)

Host Driver

Fig. 9.3.5 4-line serial interface read protocol

V1.2 32 2009-03-10

ST7715

9.4 Data Transfer Break and Recovery

If there is a break in data transmission by RESX pulse, while transferring a command or frame memory data or multiple
parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have
reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next
activated after RESX have been HIGH state. See the following example

(MCU to driver)

Host

Fig. 9.4.1 Serial bus protocol, write mode – interrupted by RESX

If there is a break in data transmission by CSX pulse, while transferring a command or frame memory data or multiple
parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have
reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next
activated. See the following example

Fig. 9.4.2 Serial bus protocol, write mode – interrupted by CSX

If 1, 2 or more parameter commands are being sent and a break occurs while sending any parameter before the last one
and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the
parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is
ready to receive next byte as shown below.

V1.2 33 2009-03-10

ST7715

Fig. 9.4.3 Write interrupts recovery (serial interface)

If a 2 or more parameter commands are being sent and a break occurs by the other command before the last one is sent,
then the parameters that were successfully sent are stored and the other parameter of that command remains previous
value.

Fig. 9.4.4 Write interrupts recovery (both serial and parallel Interface)

V1.2 34 2009-03-10

ST7715

9.5 Data transfer pause

It will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the
data transmission. If the chip select line is released after a whole byte of a frame memory data or multiple parameter data
has been completed, then driver will wait and continue the frame memory data or parameter data transmission from the
point where it was paused. If the chip select Line is released after a whole byte of a command has been completed, then
the display module will receive either the command‘s parameters (if appropriate) or a new command when the chip select
line is next enabled as shown below.
This applies to the following 4 conditions:

1) Command-Pause-Command

2) Command-Pause-Parameter

3) Parameter-Pause-Command

4) Parameter-Pause-Parameter

9.5.1 Serial interface pause

Fig. 9.5.1 Serial interface pause protocol (pause by CSX)

9.5.2 Parallel interface pause

Fig. 9.5.2 Parallel bus pause protocol (paused by CSX)

V1.2 35 2009-03-10

ST7715

9.6 Data Transfer Modes

The module has three kinds color modes for transferring data to the display RAM. These are 12-bit color per pixel, 16-bit
color per pixel and 18-bit color per pixel. The data format is described for each interface. Data can be downloaded to the
frame memory by 2 methods.

9.6.1 Method 1

The image data is sent to the frame memory in successive frame writes, each time the frame memory is filled, the frame
memory pointer is reset to the start point and the next frame is written.

9.6.2 Method 2

The image data is sent and at the end of each frame memory download, a command is sent to stop frame memory write.
Then start memory write command is sent, and a new frame is downloaded.

Note 1: These apply to all data transfer Color modes on both serial and parallel interfaces.
Note 2: The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in

the frame memory.

V1.2 36 2009-03-10

ST7715

9.7 Data Color Coding

9.7.1 8-bit Parallel Interface (IM2, IM1, IM0= “100”)

Different display data formats are available for three Colors depth supported by listed below.

- 4k colors, RGB 4,4,4-bit input.

- 65k colors, RGB 5,6,5-bit input.

- 262k colors, RGB 6,6,6-bit input.

9.7.2 8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= “03h”

“1 ”

“1 ”

“1 ”“1 ”

RESX

“

“100”

”

““

“

“1”

”

““

””

””

8080-series control pins

R1, Bit 3 B1, Bit 3 G2, Bit 3 R3, Bit 30

IM[2:0]

CSX

D/CX

WRX

RDX

D7

D6

D5

D4

D3

D2

D1

D0

Look-up table for 4096 color data mapping (12 bits to 18 bits)

Frame memory

R1, Bit 2 B1, Bit 2 G2, Bit 2 R3, Bit 20

R1, Bit 1 B1, Bit 1 G2, Bit 1 R3, Bit 11

R1, Bit 0 B1, Bit 0 G2, Bit 0 R3, Bit 00

G1, Bit 3 R2, Bit 3 B2, Bit 3 G3, Bit 31

G1, Bit 2 R2, Bit 2 B2, Bit 2 G3, Bit 21

G1, Bit 1 R2, Bit 1 B2, Bit 1 G3, Bit 10

G1, Bit 0 R2, Bit 0 B2, Bit 0 G3, Bit 00

Pixel n Pixel n+1

12 bits 12 bits

18 bits

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-time transfer is used to transmit 1 pixel data with the 12-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

V1.2 37 2009-03-10

ST7715

9.7.3 8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= “05h”

There is 1 pixel (3 sub-pixels) per 2-byte

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“100”

““

“

“1”

”

““

””

”

””

8080-series control pins

D7
D6
D5
D4
D3
D2
D1
D0

Look-up table for 65k color data mapping (16 bits to 18 bits)

Frame memory

R1, Bit 4 G1, Bit 20

R1, Bit 3 G1, Bit 10

R1, Bit 2 G1, Bit 01

R1, Bit 1 B1, Bit 40

R1, Bit 0 B1, Bit 31

G1, Bit 5 B1, Bit 21

G1, Bit 4 B1, Bit 10

G1, Bit 3 B1, Bit 00

Pixel n Pixel n+1

16 bits 16 bits

18 bits

R1 G1 B1 R2 G2 B2 R3 G3 B3

R2, Bit 4 G2, Bit 2

R2, Bit 3 G2, Bit 1

R2, Bit 2 G2, Bit 0

R2, Bit 1 B2, Bit 4

R2, Bit 0 B2, Bit 3

G2, Bit 5 B2, Bit 2

G2, Bit 4 B2, Bit 1

G2, Bit 3 B2, Bit 0

Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for

Red and Blue data.
Note 2:2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

V1.2 38 2009-03-10

ST7715

9.7.4 8-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= “06h”

There is 1 pixel (3 sub-pixels) per 3-bytes.

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“100”

““

“

“1”

”

““

””

”

””

8080-series control pins

D7
D6
D5
D4
D3
D2
D1
D0

0

0

1

0

1

1

R1, Bit 5

R1, Bit 4

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

- -0

- -0

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

Pixel n Pixel n+1

18 bits 18 bits

B1, Bit 5

B1, Bit 4

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0

- -

- -

R2, Bit 5

R2, Bit 4

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2:3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

V1.2 39 2009-03-10

ST7715

9.7.5 16-Bit Parallel Interface (IM2,IM1, IM0= “101”)

Different display data formats are available for three colors depth supported by listed below.

- 4k colors, RGB 4,4,4-bit input

- 65k colors, RGB 5,6,5-bit input

- 262k colors, RGB 6,6,6-bit input

9.7.6 16-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= “03h”

There is 1 pixel (3 sub-pixels) per 1 byte

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“101”

““

“

“1”

”

““

””

”

””

8080-series control pins

D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

-

-

-

-

-

-

-

-

0

0

1

0

1

1

0

0

-

-

-

-

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0

Pixel n Pixel n+1

-

-

-

-

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 3

B2, Bit 2

B2, Bit 1

B2, Bit 0

-

-

-

-

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

B3, Bit 3

B3, Bit 2

B3, Bit 1

B3, Bit 0

Pixel n+2 Pixel n+3

-

-

-

-

R4, Bit 3

R4, Bit 2

R4, Bit 1

R4, Bit 0

G4, Bit 3

G4, Bit 2

G4, Bit 1

G4, Bit 0

B4, Bit 3

B4, Bit 2

B4, Bit 1

B4, Bit 0

12 bits 12 bits

Look-up table for 4096 color data mapping (12 bits to 18 bits)

18 bits

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note1. The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2:1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information.

V1.2 40 2009-03-10

ST7715

9.7.7 16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= “05h”

There is 1 pixel (3 sub-pixels) per 1 byte

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“101”

““

“

“1”

”

““

””

”

””

8080-series control pins

D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4

-

-

-

-

-

-

-

0

0

1

0

1

1

0

0

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 5

G2, Bit 4

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 3

B2, Bit 2

B2, Bit 1

B2, Bit 0

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 5

G3, Bit 4

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

B3, Bit 3

B3, Bit 2

B3, Bit 1

B3, Bit 0

R4, Bit 3

R4, Bit 2

R4, Bit 1

R4, Bit 0

G4, Bit 5

G4, Bit 4

G4, Bit 3

G4, Bit 2

G4, Bit 1

G4, Bit 0

B4, Bit 3

B4, Bit 2

B4, Bit 1

B4, Bit 0

Pixel n Pixel n+1

16 bits 16 bits

Pixel n+2 Pixel n+3

Look-up table for 65k color data mapping (16 bits to 18 bits)

18 bits

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0

for Red and Blue data.
Note 2:1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

V1.2 41 2009-03-10

ST7715

9.7.8 16-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= “06h”

There are 2 pixels (6 sub-pixels) per 3 bytes

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“101”

““

“

“1”

”

““

””

”

””

8080-series control pins

D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

-

-

-

-

-

-

-

-

0

0

1

0

1

1

0

0

R1, Bit 5

R1, Bit 4

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

- - - -

- - - -

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

- - - -

- - - -

B1, Bit 5

B1, Bit 4

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0

R2, Bit 5

R2, Bit 4

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 5

G2, Bit 4

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 5

B2, Bit 4

B2, Bit 3

B2, Bit 2

B2, Bit 1

B2, Bit 0

R3, Bit 5

R3, Bit 4

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 5

G3, Bit 4

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

Pixel n Pixel n+1

18 bits

18 bits

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2:3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

V1.2 42 2009-03-10

ST7715

9.7.9 9-Bit Parallel Interface (IM2, IM1, IM0=“110”)

Different display data formats are available for three colors depth supported by listed below.

-262k colors, RGB 6,6,6-bit input

9.7.10 Write 9-bit data for RGB 6-6-6-bit input (262k-color)

There is 1 pixel (6 sub-pixels) per 3 bytes

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“110”

““

“

“1”

”

““

””

”

””

8080-series control

pins

D8
D7
D6
D5
D4
D3
D2
D1
D0

1

0

0

R1, Bit 5

R1, Bit 40

R1, Bit 30

R1, Bit 21

R1, Bit 10

R1, Bit 01

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 5

B1, Bit 4

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0

Pixel n Pixel n+1

18 bits 18 bits

R2, Bit 5-

R2, Bit 4

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 5

G2, Bit 4

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 5

B2, Bit 4

B2, Bit 3

B2, Bit 2

B2, Bit 1

B2, Bit 0

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note1. The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2:3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don't care - Can be set to '0' or '1'

V1.2 43 2009-03-10

ST7715

9.7.11 18-Bit Parallel Interface (IM2, IM1, IM0=“111”)

Different display data formats are available for three colors depth supported by listed below.

- 4k colors, RGB 4,4,4-bit input

- 65k colors, RGB 5,6,5-bit input

- 262k colors, RGB 6,6,6-bit input.

9.7.12 18-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h”

There is 1 pixel (3 sub-pixels) per 1 byte

““““ 1””””

RESX

““““ 111””””

IM[2:0]

CSX

D/CX

WRX

““““ 1””””

RDX

8080-series control pins

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

-

-

-

-

-

-

-

-

-

-

0

0

1

0

1

1

0

0

-

-

-

-

-

-

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 3

B1, Bit 2

B1, Bit 1

B1, Bit 0
Pixel n Pixel n+1

-

-

-

-

-

-

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 3

B2, Bit 2

B2, Bit 1

B2, Bit 0

-

-

-

-

-

-

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

B3, Bit 3

B3, Bit 2

B3, Bit 1

B3, Bit 0

Pixel n+2 Pixel n+3

-

-

-

-

-

-

R4, Bit 3

R4, Bit 2

R4, Bit 1

R4, Bit 0

G4, Bit 3

G4, Bit 2

G4, Bit 1

G4, Bit 0

B4, Bit 3

B4, Bit 2

B4, Bit 1

B4, Bit 0

12 bits 12 bits

Look-Up Table for 4096 Color data mapping (12 bits to 18 bits)

18 bits

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note1. The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2:1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information.

V1.2 44 2009-03-10

ST7715

9.7.13 18-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h”

There is 1 pixel (3 sub-pixels) per 1 byte

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“111”

““

“

“1”

”

““

””

”

””

8080-series control pins

D17
D16
D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1

-

-

-

-

-

-

-

-

-

-

0

0

1

0

1

1

0

-

-

R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4

B1, Bit 3

B1, Bit 2

B1, Bit 1

-

-

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 5

G2, Bit 4

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 3

B2, Bit 2

B2, Bit 1

-

-

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 5

G3, Bit 4

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

B3, Bit 3

B3, Bit 2

B3, Bit 1

-

-

R4, Bit 3

R4, Bit 2

R4, Bit 1

R4, Bit 0

G4, Bit 5

G4, Bit 4

G4, Bit 3

G4, Bit 2

G4, Bit 1

G4, Bit 0

B4, Bit 3

B4, Bit 2

B4, Bit 1

D0

0

B1, Bit 0

Pixel n Pixel n+1

16 bits 16 bits

B2, Bit 0

B3, Bit 0

Pixel n+2 Pixel n+3

B4, Bit 0

Look-up table for 65k color data mapping (16 bits to 18 bits)

18 bits

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0

for Red and Blue data.
Note 2:1-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.

V1.2 45 2009-03-10

ST7715

9.7.14 18-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h”

There is 1 pixel (3 sub-pixels) per 1 byte

“

“1”

”

““

RESX

IM[2:0]

CSX

D/CX

WRX

RDX

””

“

“111”

““

“

“1”

”

““

””

”

””

8080-series control pins

D17
D16
D15
D14
D13
D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2

-

-

-

-

-

-

-

-

-

-

0

0

1

0

1

1

R1, Bit 5 R2, Bit 5 R3, Bit 5 R4, Bit 5

R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4

R1, Bit 3

R1, Bit 2

R1, Bit 1

R1, Bit 0

G1, Bit 5

G1, Bit 4

G1, Bit 3

G1, Bit 2

G1, Bit 1

G1, Bit 0

B1, Bit 5 B2, Bit 5 B3, Bit 5 B4, Bit 5

B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4

B1, Bit 3

B1, Bit 2

R2, Bit 3

R2, Bit 2

R2, Bit 1

R2, Bit 0

G2, Bit 5

G2, Bit 4

G2, Bit 3

G2, Bit 2

G2, Bit 1

G2, Bit 0

B2, Bit 3

B2, Bit 2

R3, Bit 3

R3, Bit 2

R3, Bit 1

R3, Bit 0

G3, Bit 5

G3, Bit 4

G3, Bit 3

G3, Bit 2

G3, Bit 1

G3, Bit 0

B3, Bit 3

B3, Bit 2

R4, Bit 3

R4, Bit 2

R4, Bit 1

R4, Bit 0

G4, Bit 5

G4, Bit 4

G4, Bit 3

G4, Bit 2

G4, Bit 1

G4, Bit 0

B4, Bit 3

B4, Bit 2

D1
D0

0

0

B1, Bit 1

B1, Bit 0

Pixel n Pixel n+1

18 bits 18 bits

B2, Bit 1

B2, Bit 0

B3, Bit 1

B3, Bit 0

Pixel n+2 Pixel n+3

B4, Bit 1

B4, Bit 0

Frame memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Note1. The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data.
Note 2:1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.

V1.2 46 2009-03-10

ST7715

9.7.15 3-line serial Interface

Different display data formats are available for three colors depth supported by the LCM listed below.
4k colors, RGB 4-4-4-bit input
65k colors, RGB 5-6-5-bit input
262k colors, RGB 6-6-6-bit input

9.7.16 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h”

Note 1: pixel data with the 12-bit color depth information
Note 2: The most significant bits are: Rx3, Gx3 and Bx3
Note 3: The least significant bits are: Rx0, Gx0 and Bx0

V1.2 47 2009-03-10

ST7715

9.7.17 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h”

Note 1: pixel data with the 16-bit color depth information
Note 2: The most significant bits are: Rx4, Gx5 and Bx4
Note 3: The least significant bits are: Rx0, Gx0 and Bx0

V1.2 48 2009-03-10

ST7715

9.7.18 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h”

Note 1: pixel data with the 18-bit color depth information
Note 2: The most significant bits are: Rx5, Gx5 and Bx5
Note 3: The least significant bits are: Rx0, Gx0 and Bx0

V1.2 49 2009-03-10

ST7715

9.7.19 4-line serial Interface

Different display data formats are available for three colors depth supported by the LCM listed below.
4k colors, RGB 4-4-4-bit input
65k colors, RGB 5-6-5-bit input
262k colors, RGB 6-6-6-bit input

9.7.20 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH=“03h”

Note 1: pixel data with the 12-bit color depth information
Note 2: The most significant bits are: Rx3, Gx3 and Bx3
Note 3: The least significant bits are: Rx0, Gx0 and Bx0

V1.2 50 2009-03-10

ST7715

9.7.21 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH=“05h”

Note 1: pixel data with the 16-bit color depth information
Note 2: The most significant bits are: Rx4, Gx5 and Bx4
Note 3: The least significant bits are: Rx0, Gx0 and Bx0

V1.2 51 2009-03-10

ST7715

9.7.22 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH=“06h”

Note 1: pixel data with the 18-bit color depth information
Note 2: The most significant bits are: Rx5, Gx5 and Bx5
Note 3: The least significant bits are: Rx0, Gx0 and Bx0

V1.2 52 2009-03-10

ST7715

9.8 Display Data RAM

9.8.1 Configuration (GM[2:0] = “001”)

The display module has an integrated 132x132x18-bit graphic type static RAM. This 313,632-bit memory allows storing
on-chip a 132xRGBx132 image with an 18-bpp resolution (262K-color). There will be no abnormal visible effect on the
display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory.

Fig. 9.8.1 Display data RAM organization

V1.2 53 2009-03-10

ST7715

Gate Out

10131R0G0B0R1G1B1

--------

R130

G130

B130

R131

G131

B1310131

21130

--------

1

130

32129

--------

2

129

43128

--------

3

128

54127

--------

4

127

65126

--------

5

126

76125

--------

6

125

87124

--------

7

124

125

1247--------

124

7

126

1256--------

125

6

127

1265--------

126

5

128

1274--------

127

4

129

1283--------

128

3

130

1292--------

129

2

131

1301--------

130

1

MX='0'

--------

9.8.2 Memory to Display Address Mapping

9.8.3 When using 132RGB x 132 resolution (GM[2:0] = “001”, SMX=SMY=SRGB= ‘0’)

Pixel 1 Pixel 2 Pixel 131 Pixel 132

Source Out

RA SA

MY=' 0 ' MY=' 1 ' ML=' 0 ' ML=' 1 '

|
|
|
|

|
|
|
|

S1 S2 S3 S4 S5 S6 -------- S391 S392 S393 S394 S395 S396

RGB=0

|

|

|

|

|

|

|

|

RGB=1

RGB=0

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|

|
|
|
|

RGB=1

--------

RGB

Order

|
|
|
|

RGB=0

|
|
|
|

RGB=1

RGB=0

|

|

|

|

|

|

|

|

|

|

|

|

RGB=1

|

|

|

|

|

|

|

|

|

|

|

|

|
|
|
|

132 131 0 -------- 131 0

CA

MX='1' --------

0 1 130

131 130 1 0

Note
RA = Row Address,
CA = Column Address
SA = Scan Address
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command
ML =Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command

131

V1.2 54 2009-03-10

ST7715

G130

G131

G132

9.8.4 Normal Display On or Partial Mode On

9.8.5 When using 132RGB x 132 resolution (GM[2:0] = “001”)

In this mode, contents of the frame memory within an area where column pointer is 00h to 83h and page pointer is 00h to
83h is displayed.
To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0)

1). Example for Normal Display On (MX=MY=ML=’0’, SMX=SMY=’0’)

132 Columns

Scan
Order

132 Columns

00h 01h ---- ---- ---- ---- ---- 82h 83h
00h 00 01 02 03 0W 0X 0Y 0Z 1
01h 10 11 12 13 1W 1X 1Y 1Z 2
02h 20 21 22 2X 2Y 2Z 3

| 30 31 32 3X 3Y 3Z |
| 40 41 42 4X 4Y 4Z |

132 Lines

| 50 51 5Y 5Z |
| 60 6Z |
| |
| |
| |
| |
| S0 SZ |
| U0 U1 UY UZ |
| V0 V1 V2 VX VY VZ |

| W0 W1 W2 WX WY WZ |
81h X0 X1 X2 XX XY XZ 130
82h Y0 Y1 Y2 Y3 YW YX YY YZ 131
83h Z0 Z1 Z2 Z3 ZW ZX ZY ZZ 132

132 x 132 x18 bit

Frame RAM

00h 01h ---- ---- ---- ---- ---- 82h 83h
00h 00 01 02 03 0W 0X 0Y 0Z G1
01h 10 11 12 13 1W 1X 1Y 1Z G2
02h 20 21 22 2X 2Y 2Z G3

| 30 31 32 3X 3Y 3Z |
| 40 41 42 4X 4Y 4Z |
| 50 51 5Y 5Z |
| 60 6Z |
| |
| |
| |
| |
| S0 SZ |
| U0 U1 UY UZ |
| V0 V1 V2 VX VY VZ |

| W0 W1 W2 WX WY WZ |
81h X0 X1 X2 XX XY XZ
82h Y0 Y1 Y2 Y3 YW YX YY YZ
83h Z0 Z1 Z2 Z3 ZW ZX ZY ZZ

132RGB x 132

LCD Panel

2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=7Ch, MX=MV=ML=’0’ ,SMX=SMY=’0’)

132 Columns 132 Columns

Scan
Order

Display area =132 lines

00h 01h ------------ -------- 82h 83h

00 01 02 03 0W 0X 0Y 0Z G1

00h

10 11 12 13 1W 1X 1Y 1Z G2

01h

20 21 22 2X 2Y 2Z G3

02h

30 31 32 3X 3Y 3Z |

|

40 41 42 4X 4Y 4Z |

|

50 51 5Y 5Z |

|

60 6Z |

|

132 Lines

|
|
|
|

S0 SZ |

|

U0 U1 UY UZ |

|

V0 V1 V2 VX VY VZ |

|

W0 W1 W2 WX WY WZ |

|

X0 X1 X2 XX XY XZ G130

81h

Y0 Y1 Y2 Y3 YW YX YY YZ G131

82h

Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G132

83h

132RGB x 132

LCD Panel

|
|
|
|

00h 01h ---------------- ---- 82h 83h

00 01 02 03 0W 0X 0Y 0Z G1

00h

10 11 12 13 1W 1X 1Y 1Z G2

01h

20 21 22 2X 2Y 2Z G3

02h

30 31 32 3X 3Y 3Z |

|

40 41 42 4X 4Y 4Z |

|

50 51 5Y 5Z |

|

60 6Z |

|
|
|
|
|

S0 SZ |

|

U0 U1 UY UZ |

|

V0 V1 V2 VX VY VZ |

|

W0 W1 W2 WX WY WZ |

|

X0 X1 X2 XX XY XZ G130

81h

Y0 Y1 Y2 Y3 YW YX YY YZ G131

82h

Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G132

83h

132RGB x 132

LCD Panel

|
|
|
|

Non-Displa
y area =4
lines

Display
area
=124
lines

Non-Displa
y area
=4lines

V1.2 55 2009-03-10

ST7715

9.9 Address Counter

The address counter sets the addresses of the display data RAM for writing and reading.
Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit),
according to the data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM.
The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=131 (83h) and Y=0 to
Y=131 (83h). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined that
will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE
designating the end address.

For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h)
and XE=127 (83h), YE=131 (83h).

In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps
around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address
increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next
row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS).

For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET and MADCTL” (see
section 10 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All
combinations of flags are allowed. Section 9.10 show the available combinations of writing to the display RAM. When MX,
MY and MV will be changed the data bust be rewritten to the display RAM.

For each image condition, the controls for the column and row counters apply as section 9.10 below

Condition Column Counter Row Counter

When RAMWR/RAMRD command is accepted

Complete Pixel Read / Write action Increment by 1 No change

The Column counter value is larger than “End Column (XE)”

The Column counter value is larger than “End Column (XE)” and the Row

counter value is larger than “End Row (YE)”

Return to

“Start Column (XS)”

Return to

“Start Column (XS)”

Return to

“Start Column (XS)”

Return to

“Start Row (YS)”

Increment by 1

Return to

“Start Row (YS)”

V1.2 56 2009-03-10

ST7715

9.10 Memory Data Write/ Read Direction

The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be
written is controlled by “Memory Data Access Control” Command, bits B5 (MV), B6 (MX), B7 (MY) as described below.

Panel

Fig. 9.10.1 Data streaming order

9.10.1 When 132RGBx132 (GM= “001”)

MV MX MY

0 0 0 Direct to Physical Column Pointer Direct to Physical Row Pointer
0 0 1 Direct to Physical Column Pointer Direct to (131-Physical Row Pointer)
0 1 0 Direct to (131-Physical Column Pointer) Direct to Physical Row Pointer
0 1 1 Direct to (131-Physical Column Pointer) Direct to (131-Physical Row Pointer)
1 0 0 Direct to Physical Row Pointer Direct to Physical Column Pointer
1 0 1 Direct to (131-Physical Row Pointer) Direct to Physical Column Pointer
1 1 0 Direct to Physical Row Pointer Direct to (131-Physical Column Pointer)
1 1 1 Direct to (131-Physical Row Pointer) Direct to (131-Physical Column Pointer)

Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7

(MY), B6 (MX), B5 (MV). The write order for each pixel unit is

CASET RASET

One pixel unit represents 1 column and 1page counter value on the Frame Memory.

V1.2 57 2009-03-10

ST7715

9.10.2 Frame Data Write Direction According to the MADCTL parameters (MV, MX and MY)

Display Data
Direction

Normal 0 0 0

Y-Mirror 0 0 1

X-Mirror 0 1 0

MADCTL
Parameter

MV MX MY

Image in the Host
(MPU)

Image in the Driver
(DDRAM)

X-Mirror
Y-Mirror

X-Y Exchange 1 0 0

X-Y Exchange
Y-Mirror

X-Y Exchange
X-Mirror

0 1 1

1 0 1

1 1 0

X-Y Exchange
X-Mirror
Y-Mirror

1 1 1

V1.2 58 2009-03-10

ST7715

9.11 Tearing Effect Output Line

The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled
by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the
Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when
displaying video images.

9.11.1 Tearing Effect Line Modes

Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:

tvdh= The LCD display is not updated from the Frame Memory
tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)

Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 132
H-sync pulses per field.

thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)

Note: During Sleep In Mode, the Tearing Output Pin is active Low.

V1.2 59 2009-03-10

ST7715

9.11.2 Tearing Effect Line Timings

The Tearing Effect signal is described below:

Table 9.11.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 60 Hz, Ta=25°C)

Symbol Parameter min max unit description

tvdl Vertical Timing Low Duration 13 - ms

tvdh Vertical Timing High Duration 1000 - µs

thdl Horizontal Timing Low Duration 33 - µs

thdh Horizontal Timing Low Duration 25 500 µs

NOTE: The timings in Table 9.11.1 apply when MADCTL ML=0 and ML=1

The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.

The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect:

V1.2 60 2009-03-10

ST7715

9.11.3 Example 1: MPU Write is faster than panel read

MCU to memory

st

TE output signal

Memory to LCD

Image on LCD

Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of
the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame
refresh has a complete new image:

132

nd

time1

time

st

1

132

nd

time

V1.2 61 2009-03-10

ST7715

9.11.4 Example 2: MPU write is slower than panel read

MCU to memory

st

TE output signal

Memory to LCD

st

1

132

nd

Image on LCD

The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the
Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing
download during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position.

132

nd

time1

time

time

V1.2 62 2009-03-10

ST7715

9.12 Power ON/OFF Sequence

VDDI and VDD can be applied in any order.
VDDI and VDD can be powered down in any order.
During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 120msec after RESX
has been released.
During power off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum 0msec after RESX has
been released.
CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX.

Note 1: There will be no damage to the display module if the power sequences are not met.
Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out

command. Also between receiving Sleep In command and Power Off Sequence.

Note 4: If RESX line is not held stable by host during Power On Sequence as defined in the sequence below, then it will be necessary to

apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not
guaranteed.

The power on/off sequence is illustrated below

TrPW≧ 0ns TfPW≧ 0ns

VDD

VDDI

CSX

RESX

(Power down in
sleep-out mode)

RESX

(Power down in

sleep-in mode)

H or L

Timing when the latter signal rises up to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross point of
90% of 2.75V, not 90% of 2.6V.

Timing when the latter signal falls up to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross point of
90% of 2.75V, not 90% of 2.6V.

Tf

Tr

30%

PW-CSX

= +/- no limit

Tr

Tr

PW-RESX

PW-RESX

= + no limit

Tf

PW-RESX1

= + no limit

PW-CSX

= min 120ms

30%

Tf
Tf

is applied to RESX falling in the Sleep Out Mode.

PW-RESx1

is applied to RESX falling in the Sleep In Mode.

PW-RESx2

= +/- no limit

Tf

PW-RESX2

= min 0ms

V1.2 63 2009-03-10

ST7715

9.12.1 Uncontrolled Power Off

The uncontrolled power-off means a situation which removed a battery without the controlled power off sequence. It will
neither damage the module or the host interface.

If uncontrolled power-off happened, the display will go blank and there will not any visible effect on the display (blank
display) and remains blank until “Power On Sequence” powers it up.

9.13 Power Level Definition

9.13.1 Power Level

6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption

1. Normal Mode On (full display), Idle Mode Off, Sleep Out.
In this mode, the display is able to show maximum 262,144 colors.

2. Partial Mode On, Idle Mode Off, Sleep Out.
In this mode part of the display is used with maximum 262,144 colors.

3. Normal Mode On (full display), Idle Mode On, Sleep Out.
In this mode, the full display area is used but with 8 colors.

4. Partial Mode On, Idle Mode On, Sleep Out.
In this mode, part of the display is used but with 8 colors.

5. Sleep In Mode
In this mode, the DC: DC converter, internal oscillator and panel driver circuit are stopped. Only the MCU interface and
memory works with VDDI power supply. Contents of the memory are safe.

6. Power Off Mode
In this mode, both VDD and VDDI are removed.

Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.

V1.2 64 2009-03-10

ST7715

9.13.2 Power Flow Chart

Normal display mode on = NOR ON
Partial display mode on = PTL ON
Idle mode off = IDM OFF
Idle mode on = IDM ON
Sleep out = SLP OUT
Sleep in = SLP IN

NOR ON

PTL ON

IDM ON IDM OFF

IDM ON IDM OFF

Sleep out

Normal display mode on

Idle mode off

Sleep out

Normal display mode on

Idle mode on

Sleep out

Partial display mode on

Idle mode off

SLP IN

SLP OUT

SLP IN

SLP OUT

SLP IN

SLP OUT

Power on sequence

HW reset

SW reset

Sleep in

Normal display mode on

Idle mode off

IDM ON IDM OFF

Sleep in

Normal display mode on

Idle mode on

Sleep in

Partial display mode on

Idle mode off

IDM ON IDM OFF

NOR ON

PTL ON

PTL ON

NOR ON

Sleep out

Partial display mode on

Idle mode on

SLP IN

SLP OUT

Sleep in

Partial display mode on

Idle mode on

PTL ON

NOR ON

V1.2 65 2009-03-10

ST7715

9.14 Reset Table

9.14.1 Reset Table (GM[2:0]= “001”, 132RGB x 132)

Item After Power On After H/W Reset After S/W Reset
Frame memory Random No Change No Change
Sleep In/Out In In In
Display On/Off Off Off Off
Display mode (normal/partial) Normal Normal Normal
Display Inversion On/Off Off Off Off
Display Idle Mode On/Off Off Off Off
Column: Start Address (XS) 0000h 0000h 0000h

0083h (131d) (when

Column: End Address (XE) 0083h 0083h

Row: Start Address (YS) 0000h 0000h 0000h

Row: End Address (YE) 0083h 0083h

Gamma setting GC0 GC0 GC0
RGB for 4k and 65k Color Mode See Section 9.17 See Section 9.17 No Change
Partial: Start Address (PSL) 0000h 0000h 0000h
Partial: End Address (PEL) 0083h 0083h 0083h
Tearing: On/Off Off Off Off
Tearing Effect Mode (*1) 0 (Mode1) 0 (Mode1) 0 (Mode1)
Memory Data Access Control
(MY/MX/MV/ML/RGB)
Interface Pixel Color Format 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) No Change
RDDPM 08h 08h 08h
RDDMADCTL 00h 00h No Change
RDDCOLMOD 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) No Change
RDDIM 00h 00h 00h
RDDSM 00h 00h 00h
ID2 NV value NV value NV value
ID3 NV value NV value NV value

Note 1: TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.

0/0/0/0/0 0/0/0/0/0 No Change

MV=0)
0083h (131d) (when
MV=1)

0083h (131d) (when
MV=0)
0083h (131d) (when
MV=1)

V1.2 66 2009-03-10

ST7715

9.15 Module Input/Output Pins

9.15.1 Output or Bi-directional (I/O) Pins

Output or Bi-directional pins After Power On After Hardware Reset After Software Reset
TE Low Low Low
D7 to D0 (Output driver) High-Z (Inactive) High-Z (Inactive) High-Z (Inactive)

Input pins
RESX See 9.15 Input valid Input valid Input valid See 9.15

CSX Input invalid Input valid Input valid Input valid Input invalid
D/CX Input invalid Input valid Input valid Input valid Input invalid
WRX Input invalid Input valid Input valid Input valid Input invalid
RDX Input invalid Input valid Input valid Input valid Input invalid
D7 to D0 Input invalid Input valid Input valid Input valid Input invalid

Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset.

During Power
On Process

After Power On

After Hardware
Reset

After Software
Reset

During Power
Off Process

V1.2 67 2009-03-10

ST7715

9.16 Reset Timing

Table 9.16.1 Reset timing

Related
Pins

RESX

Notes:

1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from EEPROM (or
similar device) to registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a
rising edge of RESX.

2. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below:

-

3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum
time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In -mode.) and then
return to Default condition for Hardware Reset.

4. Spike Rejection also applies during a valid reset pulse as shown below:

Symbol Parameter MIN MAX
tRESW Reset pulse duration 10 - us
tREST Reset cancel

RESX Pulse Action
Shorter than 5us Reset Rejected
Longer than 9us Reset
Between 5us and 9us Reset starts

- 5 ms
120 ms

Unit

5. When Reset applied during Sleep In Mode.

6. When Reset applied during Sleep Out Mode.

7. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent
for 120msec.

V1.2 68 2009-03-10

ST7715

9.17 Color Depth Conversion Look Up Tables

9.17.1 65536 Color to 262,144 Color

Color

RED

Color
GREEN

Look Up Table Output
Frame Memory Data (6-bits)

R005 R004 R003 R002 R001 R000
R015 R014 R013 R012 R011 R010
R025 R024 R023 R022 R021 R020
R035 R034 R033 R032 R031 R030
R045 R044 R043 R042 R041 R040
R055 R054 R053 R052 R051 R050
R065 R064 R063 R062 R061 R060
R075 R074 R073 R072 R071 R070
R085 R084 R083 R082 R081 R080
R095 R094 R093 R092 R091 R090
R105 R104 R103 R102 R101 R100
R115 R114 R113 R112 R111 R110
R125 R124 R123 R122 R121 R120
R135 R134 R133 R132 R131 R130
R145 R144 R143 R142 R141 R140
R155 R154 R153 R152 R151 R150
R165 R164 R163 R162 R161 R160
R175 R174 R173 R172 R171 R170
R185 R184 R183 R182 R181 R180
R195 R194 R193 R192 R191 R190
R205 R204 R203 R202 R201 R200
R215 R214 R213 R212 R211 R210
R225 R224 R223 R222 R221 R220
R235 R234 R233 R232 R231 R230
R245 R244 R243 R242 R241 R240
R255 R254 R253 R252 R251 R250
R265 R264 R263 R262 R261 R260
R275 R274 R273 R272 R271 R270
R285 R284 R283 R282 R281 R280
R295 R294 R293 R292 R291 R290
R305 R304 R303 R302 R301 R300
R315 R314 R313 R312 R311 R310

Look Up Table Output
Frame Memory Data (6-bits)

G005 G004 G003 G002 G001 G000 000000 33 000000
G015 G014 G013 G012 G011 G010 000001 34 000001
G025 G024 G023 G022 G021 G020 000010 35 000010
G035 G034 G033 G032 G031 G030 000011 36 000011
G045 G044 G043 G042 G041 G040 000100 37 000100
G055 G054 G053 G052 G051 G050 000101 38 000101
G065 G064 G063 G062 G061 G060 000110 39 000110
G075 G074 G073 G072 G071 G070 000111 40 000111
G085 G084 G083 G082 G081 G080 001000 41 001000
G095 G094 G093 G092 G091 G090 001001 42 001001
G105 G104 G103 G102 G101 G100 001010 43 001010
G115 G114 G113 G112 G111 G110 001011 44 001011
G125 G124 G123 G122 G121 G120 001100 45 001100
G135 G134 G133 G132 G131 G130 001101 46 001101
G145 G144 G143 G142 G141 G140 001110 47 001110
G155 G154 G153 G152 G151 G150 001111 48 001111
G165 G164 G163 G162 G161 G160 010000 49 010000
G175 G174 G173 G172 G171 G170 010001 50 010001
G185 G184 G183 G182 G181 G180 010010 51 010010
G195 G194 G193 G192 G191 G190 010011 52 010011
G205 G204 G203 G202 G201 G200 010100 53 010100

Default value
after H/W Reset

000000 1 00000
000010 2 00001
000100 3 00010
000110 4 00011
001000 5 00100
001010 6 00101
001100 7 00110
001110 8 00111
010000 9 01000
010010 10 01001
010100 11 01010
010110 12 01011
011000 13 01100
011010 14 01101
011100 15 01110
011110 16 01111
100001 17 10000
100011 18 10001
100101 19 10010
100111 20 10011
101001 21 10100
101011 22 10101
101101 23 10110
101111 24 10111
110001 25 11000
110011 26 11001
110101 27 11010
110111 28 11011
111001 29 11100
111011 30 11101
111101 31 11110
111111 32 11111

Default value
after H/W Reset

RGBSET
Parameter

RGBSET
Parameter

Look Up Table Input Data
65k Color (5-bits)

Look Up Table Input Data
65k Color (5-bits)

V1.2 69 2009-03-10

ST7715

Color
BLUE

G215 G214 G213 G212 G211 G210 010101 54 010101
G225 G224 G223 G222 G221 G220 010110 55 010110
G235 G234 G233 G232 G231 G230 010111 56 010111
G245 G244 G243 G242 G241 G240 011000 57 011000
G255 G254 G253 G252 G251 G250 011001 58 011001
G265 G264 G263 G262 G261 G260 011010 59 011010
G275 G 274 G273 G272 G271 G270 011011 60 011011
G285 G 284 G283 G282 G281 G280 011100 61 011100
G295 G 294 G293 G292 G291 G290 011101 62 011101
G305 G 304 G303 G302 G301 G300 011110 63 011110
G315 G 314 G313 G312 G311 G310 011111 64 011111
G325 G324 G323 G322 G321 G320 100000 65 100000
G335 G334 G333 G332 G331 G330 100001 66 100001
G345 G344 G343 G342 G341 G340 100010 67 100010
G355 G354 G353 G352 G351 G350 100011 68 100011
G365 G364 G363 G362 G361 G360 100100 69 100100
G375 G374 G373 G372 G371 G370 100101 70 100101
G385 G384 G383 G382 G381 G380 100110 71 100110
G395 G394 G393 G392 G391 G390 100111 72 100111
G405 G404 G403 G402 G401 G400 101000 73 101000
G415 G414 G413 G412 G411 G410 101001 74 101001
G425 G424 G423 G422 G421 G420 101010 75 101010
G435 G434 G433 G432 G431 G430 101011 76 101011
G445 G444 G443 G442 G441 G440 101100 77 101100
G455 G454 G453 G452 G451 G450 101101 78 101101
G465 G464 G463 G462 G461 G460 101110 79 101110
G475 G474 G473 G472 G471 G470 101111 80 101111
G485 G484 G483 G482 G481 G480 110000 81 110000
G495 G494 G493 G492 G491 G490 110001 82 110001
G505 G504 G503 G502 G501 G500 110010 83 110010
G515 G514 G513 G512 G511 G510 110011 84 110011
G525 G524 G523 G522 G521 G520 110100 85 110100
G535 G534 G533 G532 G531 G530 110101 86 110101
G545 G544 G543 G542 G541 G540 110110 87 110110
G555 G554 G553 G552 G551 G550 110111 88 110111
G565 G564 G563 G562 G561 G560 111000 89 111000
G575 G574 G573 G572 G571 G570 111001 90 111001
G585 G584 G583 G582 G581 G580 111010 91 111010
G595 G594 G593 G592 G591 G590 111011 92 111011
G605 G604 G603 G602 G601 G600 111100 93 111100
G615 G614 G613 G612 G611 G610 111101 94 111101
G625 G624 G623 G622 G621 G620 111110 95 111110
G635 G634 G633 G632 G631 G630 111111 96 111111

Look Up Table Output
Frame Memory Data (6-bits)

B005 B004 B003 B002 B001 B000
B015 B014 B013 B012 B011 B010
B025 B024 B023 B022 B021 B020
B035 B034 B033 B032 B031 B030
B045 B044 B043 B042 B041 B040
B055 B054 B053 B052 B051 B050
B065 B064 B063 B062 B061 B060
B075 B074 B073 B072 B071 B070
B085 B084 B083 B082 B081 B080
B095 B094 B093 B092 B091 B090
B105 B104 B103 B102 B101 B100
B115 B114 B113 B112 B111 B110
B125 B124 B123 B122 B121 B120
B135 B134 B133 B132 B131 B130
B145 B144 B143 B142 B141 B140
B155 B154 B153 B152 B151 B150
B165 B164 B163 B162 B161 B160

Default value
after H/W Reset

000000
000010
000100
000110
001000
001010
001100
001110
010000
010010
010100
010110
011000
011010
011100
011110
100001

RGBSET
Parameter

97 00000
98 00001
99 00010
100 00011
101 00100
102 00101
103 00110
104 00111
105 01000
106 01001
107 01010
108 01011
109 01100
110 01101
111 01110
112 01111
113 10000

Look Up Table Input Data
65k Color (5-bits)

V1.2 70 2009-03-10

ST7715

B175 B174 B173 B172 B171 B170
B185 B184 B183 B182 B181 B180
B195 B194 B193 B192 B191 B190
B205 B204 B203 B202 B201 B200
B215 B214 B213 B212 B211 B210
B225 B224 B223 B222 B221 B220
B235 B234 B233 B232 B231 B230
B245 B244 B243 B242 B241 B240
B255 B254 B253 B252 B251 B250
B265 B264 B263 B262 B261 B260
B275 B274 B273 B272 B271 B270
B285 B284 B283 B282 B281 B280
B295 B294 B293 B292 B291 B290
B305 B304 B303 B302 B301 B300
B315 B314 B313 B312 B311 B310

100011
100101
100111
101001
101011
101101
101111
110001
110011
110101
110111
111001
111011
111101
111111

114 10001
115 10010
116 10011
117 10100
118 10101
119 10110
120 10111
121 11000
122 11001
123 11010
124 11011
125 11100
126 11101
127 11110
128 11111

V1.2 71 2009-03-10

ST7715

9.17.2 4096 Color to 262,144 Color

Color

RED

GREEN

BLUE

Look Up Table Output
Frame Memory Data (6-bits)

R005 R004 R003 R002 R001 R000
R015 R014 R013 R012 R011 R010
R025 R024 R023 R022 R021 R020
R035 R034 R033 R032 R031 R030
R045 R044 R043 R042 R041 R040
R055 R054 R053 R052 R051 R050
R065 R064 R063 R062 R061 R060
R075 R074 R073 R072 R071 R070
R085 R084 R083 R082 R081 R080
R095 R094 R093 R092 R091 R090
R105 R104 R103 R102 R101 R100
R115 R114 R113 R112 R111 R110
R125 R124 R123 R122 R121 R120
R135 R134 R133 R132 R131 R130
R145 R144 R143 R142 R141 R140
R155 R154 R153 R152 R151 R150
R165 R164 R163 R162 R161 R160
|
R315 R314 R313 R312 R311 R310 ------ 32
G005 G004 G003 G002 G001 G000 000000 33 0000
G015 G014 G013 G012 G011 G010 000100 34 0001
G025 G024 G023 G022 G021 G020 001000 35 0010
G035 G034 G033 G032 G031 G030 001100 36 0011
G045 G044 G043 G042 G041 G040 010001 37 0100
G055 G054 G053 G052 G051 G050 010101 38 0101
G065 G064 G063 G062 G061 G060 011001 39 0110
G075 G074 G073 G072 G071 G070 011101 40 0111
G085 G084 G083 G082 G081 G080 100010 41 1000
G095 G094 G093 G092 G091 G090 100110 42 1001
G105 G104 G103 G102 G101 G100 101010 43 1010
G115 G114 G113 G112 G111 G110 101110 44 1011
G125 G124 G123 G122 G121 G120 110011 45 1100
G135 G134 G133 G132 G131 G130 110111 46 1101
G145 G144 G143 G142 G141 G140 111011 47 1110
G155 G154 G153 G152 G151 G150 111111 48 1111
G165 G164 G163 G162 G161 G160 ------ 49
|
G635 G634 G633 G632 G631 G630 ------ 96
B005 B004 B003 B002 B001 B000
B015 B014 B013 B012 B011 B010
B025 B024 B023 B022 B021 B020
B035 B034 B033 B032 B031 B030
B045 B044 B043 B042 B041 B040
B055 B054 B053 B052 B051 B050
B065 B064 B063 B062 B061 B060
B075 B074 B073 B072 B071 B070
B085 B084 B083 B082 B081 B080
B095 B094 B093 B092 B091 B090
B105 B104 B103 B102 B101 B100
B115 B114 B113 B112 B111 B110
B125 B124 B123 B122 B121 B120
B135 B134 B133 B132 B131 B130
B145 B144 B143 B142 B141 B140
B155 B154 B153 B152 B151 B150
B165 B164 B163 B162 B161 B160
|
B315 B314 B313 B312 B311 B310 ------ 128

Default value
after H/W Reset

000000 1 0000
000100 2 0001
001000 3 0010
001100 4 0011
010001 5 0100
010101 6 0101
011001 7 0110
011101 8 0111
100010 9 1000
100110 10 1001
101010 11 1010
101110 12 1011
110011 13 1100
110111 14 1101
111011 15 1110
111111 16 1111

------ 17
| |

| |

000000 97 0000
000100 98 0001
001000 99 0010
001100 100 0011
010001 101 0100
010101 102 0101
011001 103 0110
011101 104 0111
100010 105 1000
100110 106 1001
101010 107 1010
101110 108 1011
110011 109 1100
110111 110 1101
111011 111 1110
111111 112 1111

------ 113
| |

RGBSET
Parameter

Look Up Table Input Data
4k Color (4-bits)

Not used

Not used

Not used

V1.2 72 2009-03-10

ST7715

ion

Refer

D/CX

↑ 1

SWRESET

↑ 1

↑ 1

↑

↑

↑

↑

↑ 1

↑

↑

↑

↑

↑

↑ 1

↑

↑

↑ 1

↑

MADCTL

↑

↑ 1

↑

COLMOD

↑

↑ 1

↑

↑

↑ 1

↑

↑

10 Command

10.1 System function Command List and Description

Table 10.1.1 System Function command List (1)

Instruct

NOP 10.1.1 0

10.1.2 0

RDDID 10.1.3

RDDST 10.1.4

RDDPM 10.1.5

RDD

10.1.6

RDD

10.1.7

RDDIM 10.1.8

RDDSM 10.1.9

“-“: Don’t care

WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 Hex

- 0 0 0 0 0 0 0 0 (00h) No Operation

- 0 0 0 0 0 0 0 1 (01h) Software reset
0
1 1
1 1
1 1
1 1
0
1 1
1 1
1 1
1 1
1 1

0
1 1

1 1
0
1 1
1 1

0
1 1

1 1
0
1 1

1 1
0
1 1

1 1

- 0 0 0 0 0 1 0 0 (04h) Read Display ID

- - - - - - - - - Dummy read

- ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID1 read

- 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID2 read

- ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 ID3 read

- 0 0 0 0 1 0 0

- - - - - - - - - Dummy read

- BSTON MY MX MV ML RGB 0 ST24 -

- ST23 IFPF2 IFPF1 IFPF0 IDMON PTLON SLOUT NORON -

- VSSON ST14 INVON ST12 ST11 DISON TEON GCS2 -

- GCS1 GCS0 TELON ST4 ST3 ST2 ST1 ST0

- 0 0 0 0 1 0 1 0 (0Ah)

- - - - - - - - - Dummy read

- BSTON IDMON PTLON SLPOUT NORON DISON - - -

- 0 0 0 0 1 0 1 1 (0Bh) Read Display MADCTL

- - - - - - - - - Dummy read

- MY MX MV ML RGB 0 - - -

- 0 0 0 0 1 1 0 0 (0Ch)

- - - - - - - - - Dummy read

- 0 0 0 0 - IFPF2 IFPF1 IFPF0 -

- 0 0 0 0 1 1 0 1 (0Dh)

- - - - - - - - - Dummy read

- VSSON D6 INVON - - GCS2 GCS1 GCS0 -

- 0 0 0 0 1 1 1 0 (0Eh)

- - - - - - - - - Dummy read

- TEON TELON - - - - - - -

1 (09h) Read Display Status

Function

­Read Display Power

Mode

Read Display Pixel

Format

Read Display Image

Mode

Read Display Signal

Mode

V1.2 73 2009-03-10

ST7715

Table 10.1.2 System Function command List (2)

D/C

Instruction Refer

SLPIN 10.1.10 0 ↑ 1 - 0 0 0 1 0 0 0 0 (10h) Sleep in & booster off

SLPOUT 10.1.11 0 ↑ 1 - 0 0 0 1 0 0 0 1 (11h) Sleep out & booster on

PTLON 10.1.12 0 ↑ 1 - 0 0 0 1 0 0 1 0 (12h)

NORON 10.1.13 0 ↑ 1 - 0 0 0 1 0 0 1 1 (13h) Partial off (Normal)
INVOFF 10.1.14 0 ↑ 1 - 0 0 1 0 0 0 0 0 (20h)

INVON 10.1.15 0 ↑ 1 - 0 0 1 0 0 0 0 1 (21h) Display inversion on

GAMSET 10.1.16

DISPOFF 10.1.17 0 ↑ 1 - 0 0 1 0 1 0 0 0 (28h)

DISPON 10.1.18 0 ↑ 1 - 0 0 1 0 1 0 0 1 (29h)

CASET 10.1.19

RASET 10.1.20

RAMWR 10.1.21

RAMRD 10.1.22

WR

X

X

0 ↑ 1 - 0 0 1 0 0 1 1 0 (26h) Gamma curve select
1 ↑ 1 - - - - - GC3 GC2 GC1 GC0 -

0 ↑ 1 - 0 0 1 0 1 0 1 0 (2Ah) Column address set
1 ↑ 1 - - - - - - - - -
1 ↑ 1 - XS7 XS XS5 XS4 XS3 XS2 XS1 XS0
1 ↑ 1 - - - - - - - - -
1 ↑ 1 - XE7 XE6 XE5 XE4 XE3 XE2 XE1 XE0
0 ↑ 1 - 0 0 1 0 1 0 1 1 (2Bh)
1 ↑ 1 - - - - - - - - -

1 ↑ 1 - YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0

1 ↑ 1 - - - - - - - - -

1 ↑ 1 - YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0
0 ↑ 1 - 0 0 1 0 1 1 0 0 (2Ch)

1 ↑ 1 - D7 D6 D5 D4 D3 D2 D1 D0 Write data
0 ↑ 1 - 0 0 1 0 1 1 1 0 (2Eh)
1 1 ↑ - - - - - - - - - Dummy read
1 1 ↑ - D7 D6 D5 D4 D3 D2 D1 D0 Read data

“-“: Don’t care

RDX

D17-

D7 D6 D5 D4 D3 D2 D1 D0 Hex

8

Function

Partial mode on

Display inversion off

(normal)

Display off
Display on

X address start: 0≦S≦X

X address end: XS≦XE≦

X

Row address set

Y address start: 0≦YS≦Y

Y address end:S≦YE≦Y

Memory write

Memory read

V1.2 74 2009-03-10

ST7715

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

↑ 1

↑

↑

↑ 1

↑

↑

↑ 1

↑

↑

Table 10.1.3 System Function command List (3)

Instruction Refer D/CX WRXRDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 Hex

PTLAR 10.1.23

TEOFF 10.1.24 0

TEON 10.1.25

MADCTL 10.1.26

IDMOFF 10.1.27 0

IDMON 10.1.28 0

COLMOD 10.1.29

RDID1 10.1.30

RDID2 10.1.31

RDID3 10.1.32

0
1
1
1
1

0
1
0

1

0
1
0
1 1
1 1
0
1 1
1 1
0
1 1
1 1

- 0 0 1 1 0 0 0

- - - - - - - - -

- PSL7PSL6 PSL5 PSL4PSL3 PSL2 PSL1 PSL0

- - - - - - - - -

- PEL7PEL6 PEL5 PEL4PEL3 PEL2 PEL1 PEL0

- 0 0 1 1 0 1 0

- 0 0 1 1 0 1 0

- - - - - - - - TELOM

- 0 0 1 1 0 1 1

- MY MX MV ML RGB 0 - - -

- 0 0 1 1 1 0 0

- 0 0 1 1 1 0 0

- 0 0 1 1 1 0 1

- - - - - - IFPF2IFPF1 IFPF0 Interface format

- 1 1 0 1 1 0 1

- - - - - - - - - Dummy read

- ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 Read parameter

- 1 1 0 1 1 0 1

- - - - - - - - - Dummy read

- 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 Read parameter

- 1 1 0 1 1 1 0

- - - - - - - - - Dummy read

- ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 Read parameter

0 (30h) Partial start/end address set

0 (34h)
1 (35h) Tearing effect mode set & on

0 (36h) Memory data access control

0 (38h)
1 (39h)
0 (3Ah)

0 (DAh)

1 (DBh)

0 (DCh)

Partial start address (0,1,2, ..P)

Partial end address (0,1,2, .., P)

Function

Tearing effect line off

Mode1: TELOM=”0”
Mode2: TELOM=”1”

Idle mode off
Idle mode on

Interface pixel format

Read ID1

Read ID2

Read ID3

“-“: Don’t care

Note 1: After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer

“RESET TABLE” section)
Note 2: Undefined commands are treated as NOP (00 h) command.
Note 3: B0 to D9 and DA to F are for factory use of driver supplier.
Note 4: Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 36h (ML parameter only), 38h and 39h are updated during V-sync when

Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately.

Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTL (0Bh), Read Display Pixel Format (0Ch), Read

Display Image Mode (0Dh), Read Display Signal Mode (0Eh) and Read Display Self Diagnostic Result (0Fh) of these commands

are updated immediately both in Sleep In mode and Sleep Out mode.

V1.2 75 2009-03-10

ST7715

10.1.1 NOP (00h)

00H NOP (No Operation)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

NOP 0 ↑ 1 - 0 0 0 0 0 0 0 0 (00h)

Parameter

No Parameter

-

Description

“-“ Don’t care

This command is empty command.

V1.2 76 2009-03-10

ST7715

0msec before sending next

10.1.2 SWRESET (01h): Software Reset

01H SWRESET (Software Reset)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

SWRESET

Parameter

Description

0 ↑ 1 - 0 0 0 0 0 0 0 1 (01h)

No Parameter
“-“ Don’t care

-If Software Reset is applied during Sleep In mode, it will be necessary to wait 12
command.

-The display module loads all default values to the registers during 120msec.

-If Software Reset is applied during Sleep Out or Display On Mode, it will be necessary to wait 120msec before sending
next command.

Legend

-

Flow Chart

SWRESET

Display whole

blank screen

Set

Commands

to S/W
Default

Value

Sleep In Mode

Command

Parameter

Display

Action

Mode

Sequential

transter

V1.2 77 2009-03-10

ST7715

10.1.3 RDDID (04h): Read Display ID

04H RDDID (Read Display ID)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

RDDID 0 ↑ 1 - 0 0 0 0 0 1 0 0 (04h)

1st parameter 1 1 ↑ - - - - - - - - - -

2nd parameter 1 1 ↑ - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10

3rd parameter 1 1 ↑ - 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20
4th parameter 1 1 ↑ - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30

-This read byte returns 24-bit display identification information.

-The 1st parameter is dummy data

-The 2nd parameter (ID17 to ID10): LCD module’s manufacturer ID.

Description

Default

-The 3rd parameter (ID26 to ID20): LCD module/driver version ID

-The 4th parameter (ID37 to UD30): LCD module/driver ID.

- Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h,
respectively.
“-“ Don’t care

Status

Power On Sequence - 8xh 00h

S/W Reset - 8xh 00h

H/W Reset - 8xh 00h

ID1 ID2 ID3

Default Value

Flow Chart

V1.2 78 2009-03-10

ST7715

10.1.4 RDDST (09h): Read Display Status

09H RDDST (Read Display Status)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

RDDST 0 ↑ 1 - 0 0 0 0 1 0 0 1 (09h)

1st parameter 1 1 ↑ - - - - - - - - - -

2nd parameter 1 1 ↑ - BSTON MY MX MV ML RGB

3rd parameter 1 1 ↑ - ST23 IFPF2 IFPF1 IFPF0 IDMON PTLON SLOUT NORON
4th parameter 1 1 ↑ - VSSON ST14 INVON ST12 ST11 DISON TEON GCS2
5th parameter 1 1 ↑ - GCS1 GCS0 TELOM ST4 ST3 ST2 ST1 ST0

This command indicates the current status of the display as described in the table below:

Bit Description Value
BSTON Booster Voltage Status ‘1’ =Booster on,

‘0’ =Booster off

MY Row Address Order (MY) ‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7=’1’)

‘0’ =Increment, (Top to Bottom, when MADCTL (36h) D7=’0’)

MX Column Address Order (MX) ‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6=’1’)

‘0’ =Increment, (Left to Right, when MADCTL (36h) D6=’1’)

0 ST24

Description

MV Row/Column Exchange (MV) ‘1’ = Row/column exchange, (when MADCTL (36h) D5=’1’)

‘0’ = Normal, (when MADCTL (36h) D5=’0’)

ML Scan Address Order (ML) ‘1’=Increment,

(LCD refresh Bottom to Top, when MADCTL (36h) D4=’1’)
‘0’ =Decrement,
(LCD refresh Top to Bottom, when MADCTL (36h) D4=’0’)

RGB RGB/ BGR Order (RGB) ‘1’ =BGR, (When MADCTL (36h) D3=’1’)

‘0’ =RGB, (When MADCTL (36h) D3=’0’)
ST24 For Future Use ‘0’
ST23 For Future Use ‘0’
IFPF2

Interface Color Pixel Format

IFPF1

Definition

IFPF0
IDMON Idle Mode On/Off ‘1’ = On, “0” = Off
PTLON Partial Mode On/Off ‘1’ = On, “0” = Off
SLPOUT Sleep In/Out ‘1’ = Out, “0” = In

“011” = 12-bit / pixel,

“101” = 16-bit / pixel,

“110” = 18-bit / pixel, others are no define

NORON

Display Normal Mode On/Off

VSSON Reversed “0”
ST14 Reversed ‘0’
INVON Inversion Status ‘1’ = On, “0” = Off
ST12 All Pixels On (Not Used) ‘0’
ST11 All Pixels Off (Not Used) ‘0’
DISON Display On/Off ‘1’ = On, “0” = Off

‘1’ = Normal Display,

‘0’ = Partial Display

V1.2 79 2009-03-10

ST7715

TEON Tearing effect line on/off ‘1’ = On, “0” = Off

Default

GCSEL2
GCSEL1

Gamma Curve Selection

GCSEL0

TELOM Tearing effect line mode ‘0’ = mode1, ‘1’ = mode2
ST4 For Future Use ‘0’
ST3 For Future Use ‘0’
ST2 For Future Use ‘0’
ST1 For Future Use ‘0’
ST0 For Future Use ‘0’

“-“ Don’t care

Status Default Value (ST31 to ST0)
ST[31-24] ST[23-16] ST[15-8] ST[7-0]
Power On Sequence 0000-0000 0110-0001 0000-0000 0000-0000
S/W Reset 0xxx0xx00 0xxx-0001 0000-0000 0000-0000

“000” = GC0

“001” = GC1

“010” = GC2

“011” = GC3

”100” to “111” = Not defined

H/W Reset 0000-0000 0110-0001 0000-0000 0000-0000

V1.2 80 2009-03-10

ST7715

Serial I/F Mode Parallel I/F Mode

Flow Chart

RDDST 09h RDDST 09h

Dummy

Clock

Send 2nd
parameter

Send 3rd

parameter

Send 4th

parameter

Dummy

Read

Send 2nd

parameter

Send 3rd

parameter

Send 4th

parameter

Legend

Command

Parameter

Display

Action

Mode

Sequential

transter

Send 5th

parameter

Sendth

parameter

V1.2 81 2009-03-10

ST7715

BSTON

IDMON

PTLON

SLPOUT

NORON

DISON

10.1.5 RDDPM (0Ah): Read Display Power Mode

0AH RDDPM (Read Display Power Mode)

Inst / Para D/CX WRX RDX D17-8 D7

RDDPM 0 ↑ 1 - 0 0 0 0 1 0 1 0 (0Ah)

1st parameter 1 1 ↑ - - - - - - - - - -

2nd parameter 1 1 ↑

This command indicates the current status of the display as described in the table below:
“-“ Don’t care

Bit Description Value

D6

D5

D4

D3

D2 D1

D1

D0 HEX

D0

Description

Default

BSTON Booster Voltage Status

IDMON Idle Mode On/Off

PTLON Partial Mode On/Off

SLPON Sleep In/Out

NORON Display Normal ModemOn/Off

DISON Display On/Off

D1 Not Used ‘0’
D0 Not Used ‘0’

Status Default Value (D7 to D0)
Power On Sequence 0000_1000(08h)
S/W Reset 0000_1000(08h)

‘1’ =Booster on,
‘0’ =Booster off
‘1’ = Idle Mode On,
‘0’ = Idle Mode Off
‘1’ = Partial Mode On,
‘0’ = Partial Mode Off
‘1’ = Sleep Out,
‘0’ = Sleep In
‘1’ = Normal Display,
‘0’ = Partial Display
‘1’ = Display On,
‘0’ = Display Off

H/W Reset 0000_1000(08h)

V1.2 82 2009-03-10

ST7715

Serial I/F Mode

RDDPM 0Ah RDDPM 0Ah

Parallel I/F Mode

Legend

Command

Parameter

Flow Chart

Send 2nd

parameter

Dummy

Read

Send 2nd

parameter

Display

Action

Mode

Sequential

transter

V1.2 83 2009-03-10

ST7715

10.1.6 RDDMADCTL (0Bh): Read Display MADCTL

0BH RDDMADCTL (Read Display MADCTL)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

RDDMADCTL

1st parameter 1 1 ↑ - - - - - - - - - ­2nd parameter 1 1 ↑ MY MX MV ML RGB

0 ↑ 1 - 0 0 0 0 1 0 1 1 (0Bh)

0 D1 D0

This command indicates the current status of the display as described in the table below:
“-“ Don’t care

Bit Description Value

Description

Default

MX Column Address Order

MY Row Address Order

MV Row/Column Order (MV)

ML Vertical Refresh Order

RGB RGB/BGR Order ‘1’ =BGR, “0”=RGB
D1 Not Used ‘0’
D0 Not Used ‘0’

Status Default Value (D7 to D0)
Power On Sequence 0000_0000 (00h)
S/W Reset No change
H/W Reset 0000_0000 (00h)

‘1’ = Right to Left (When MADCTL B6=’1’)
‘0’ = Left to Right (When MADCTL B6=’0’)
‘1’ = Bottom to Top (When MADCTL B7=’1’)
‘0’ = Top to Bottom (When MADCTL B7=’0’)
‘1’ = Row/column exchange (MV=1)
‘0’ = Normal (MV=0)
‘1’ =LCD Refresh Bottom to Top
‘0’ =LCD Refresh Top to Bottom

Flow Chart

V1.2 84 2009-03-10

ST7715

10.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format

0CH RDDCOLMOD (Read Display Pixel Format)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

RDDCOLMOD

1st parameter 1 1 ↑ - - - - - - - - - ­2nd parameter 1 1 ↑ - 0 0 0 0 - IFPF2 IFPF1 IFPF0

0 ↑ 1 - 0 0 0 0 1 1 0 0 (0Ch)

This command indicates the current status of the display as described in the table below:

IFPF[2:0] MCU Interface Color Format
011 12-bit/pixel

Description

Default

101 16-bit/pixel
110 18-bit/pixel
111 No used

Others are no define and invalid
“-“ Don’t care

Status Default Value
IFPF[2:0]
Power On Sequence 0110 (18 bits/pixel)
S/W Reset No Change
H/W Reset 0110 (18 bits/pixel)

Flow Chart

V1.2 85 2009-03-10

ST7715

10.1.8 RDDIM (0Dh): Read Display Image Mode

0DH RDDIM (0Dh): Read Display Image Mode

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

RDDIM 0 ↑ 1 - 0 0 0 0 1 1 0 1 (0Dh)

1st parameter 1 1 ↑ - - - - - - - - - -

2nd parameter 1 1 ↑ - VSSON D6 INVON D4 D3 GCS2 GCS1 GCS0

This command indicates the current status of the display as described in the table below:
“-“ Don’t care

Bit Description Value
VSSON Reversed “0”
D6 Reversed “0”

Description

Default

INVON Inversion On/Off

D4 All Pixels On “0” (Not used)
D3 All Pixels Off “0” (Not used)

GCS2
GCS1
GCS0

Status Default Value(D7 to D0)
Power On Sequence 0000_0000 (00h)
S/W Reset 0000_0000 (00h)
H/W Reset 0000_0000 (00h)

Gamma Curve Selection

“1” = Inversion is On,
“0” = Inversion is Off

“000” = GC0,
“001” = GC1,
“010” = GC2,
“011” = GC3, ”100” to “111” = Not defined

Flow Chart

V1.2 86 2009-03-10

ST7715

10.1.9 RDDSM (0Eh): Read Display Signal Mode

0EH RDDSM (0Eh): Read Display Signal Mode

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

RDDSM 0 ↑ 1 - 0 0 0 0 1 1 1 0 (0Eh)

1st parameter 1 1 ↑ - - - - - - - - - -

2nd parameter 1 1 ↑ - TEON TELOM D5 D4 D3 D2 D1 D0

This command indicates the current status of the display as described in the table below:
“-“ Don’t care

Bit Description Value
TEON Tearing Effect Line On/Off “1” = On,

“0” = Off

TELOM Tearing effect line mode “1” = mode2,

“0” = mode1

D5 Not Used “1” = On,

“0” = Off

Description

Default

D4 Not Used “1” = On,

“0” = Off

D3 Not Used “1” = On,

“0” = Off

D2 Not Used “1” = On,

“0” = Off

D1 Not Used “1” = On,

“0” = Off

D0 Not Used “1” = On,

Status Default Value(D7~D0)
Power On Sequence 0000_0000 (00h)
S/W Reset 0000_0000 (00h)
H/W Reset 0000_0000 (00h)

“0” = Off

V1.2 87 2009-03-10

ST7715

Flow Chart

Serial I/F Mode

Read RDDSM Read RDDSM

Send 2nd

parameter

Parallel I/F Mode

Dummy

Read

Send 2nd

parameter

Host

Display

Legend

Command

Parameter

Display

Action

Mode

Sequential

transter

V1.2 88 2009-03-10

ST7715

mode. Sleep In Mode can only be exit by the Sleep Out

When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command because of

10.1.10 SLPIN (10h): Sleep In

10H SLPIN (Sleep In)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

SLPIN 0 ↑ 1 - 0 0 0 1 0 0 0 0 (10h)

Parameter No Parameter -

Description

-This command causes the LCD module to enter the minimum power consumption mode.

-In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped.

-This command has no effect when module is already in Sleep In

Restriction

Default

Flow Chart

Command (11h).

­the stabilization timing for the supply voltages and clock circuits.

Status Default Value
Power On Sequence Sleep in mode
S/W Reset Sleep in mode
H/W Reset Sleep in mode

SLPIN

Display whole blank

screen (Automatic

No effect to DISP

ON/OFF

Commands)

Drain

Charge

From LCD

Panel

Stop

DC-DC

Converte

r

Stop

Internal

Oscillator

Sleep In Mode

Legend

Command

Parameter

Display

Action

Mode

Sequential

transter

V1.2 89 2009-03-10

ST7715

fect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In

When IC is in Sleep In mode, it is necessary to wait 120msec before sending next command because of the stabilization

10.1.11 SLPOUT (11h): Sleep Out

11H SLPOUT (Sleep Out)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

SLPOUT 0 ↑ 1 - 0 0 0 1 0 0 0 1 (11h)

Parameter No Parameter -

Description

Restriction

Default

-This command turns off sleep mode.

-In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started.

-This command has no ef
Command (10h).

­timing for the supply voltages and clock circuits.

-When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command due to the
download of default value of registers and the execution of self-diagnostic function.

Status Default Value
Power On Sequence Sleep in mode
S/W Reset Sleep in mode
H/W Reset Sleep in mode

Legend

SLPOUT

Start

Internal

Oscillator

Display whole blank
screen for 2 firames

(Automatic No effect

to DISP ON/OFF

Commands)

Command

Parameter

Flow Chart

Start up
DC:DC

Converter

Charge

Offset

voltage for

LCD

Panel

Display Memory

contents In

accordance with

the current

command table

settings

Sleep Out mode

Display

Action

Mode

Sequential

transter

V1.2 90 2009-03-10

ST7715

10.1.12 PTLON (12h): Partial Display Mode On

12H PTLON (12h): Partial Display Mode On

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

PTLON 0 ↑ 1 - 0 0 0 1 0 0 1 0 (12h)

Parameter No Parameter -

-This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h)

Description

Flow Chart

Default

-To leave Partial mode, the Normal Display Mode On command (13h) should be written.
“-“ Don’t care

Status Default Value

Power On Sequence Normal Mode On

S/W Reset Normal Mode On

H/W Reset Normal Mode On

See Partial Area (30h)

V1.2 91 2009-03-10

ST7715

10.1.13 NORON (13h): Normal Display Mode On

13H NORON (Normal Display Mode On)

Inst / Para D/CX WRX RDX D17-8

NORON 0 ↑ 1 - 0 0 0 1 0 0 1 1 (13h)

Parameter No Parameter -

-This command returns the display to normal mode.

D7 D6 D5 D4 D3 D2 D1 D0 HEX

Description

Flow Chart

Default

-Normal display mode on means Partial mode off.

-Exit from NORON by the Partial mode On command (12h)
“-“ Don’t care

Status Default Value

Power On Sequence Normal Mode On

S/W Reset Normal Mode On

H/W Reset Normal Mode On

See Partial Area Definition Descriptions for details of when to use this command

V1.2 92 2009-03-10

ST7715

10.1.14 INVOFF (20h): Display Inversion Off

20H IVNOFF (Normal Display Mode Off)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

INVOFF 0 ↑ 1 - 0 0 1 0 0 0 0 0 (20h)

Parameter No Parameter -

-This command is used to recover from display inversion mode.

Description

Default

“-“ Don’t care

(Example)

Top-Left
(0,0)

Status Default Value

Power On Sequence Display Inversion off

S/W Reset Display Inversion off

H/W Reset Display Inversion off

Memory Display

Legend

Command

Display

Inversion On

Mode

Parameter

Display

Flow Chart

INVOFF (20h)

Display

Inversion OFF

Mode

Action

Mode

Sequential

transter

V1.2 93 2009-03-10

ST7715

10.1.15 INVON (21h): Display Inversion On

21H IVNOFF (Display Inversion On)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

INVON 0 ↑ 1 - 0 0 1 0 0 0 0 1 (21h)

Parameter No Parameter -

-This command is used to enter into display inversion mode

-To exit from Display Inversion On, the Display Inversion Off command (20h) should be written.

(Example)
Memory

Display

Description

Default

“-“ Don’t care

Top-Left (0,0)

Status Default Value

Power On Sequence Display Inversion off

S/W Reset Display Inversion off

H/W Reset Display Inversion off

Flow Chart

Display

Inversion OFF

Mode

INVON (21h)

Display

Inversion ON

Mode

Legend

Command

Parameter

Display

Action

Mode

Sequential

transter

V1.2 94 2009-03-10

ST7715

10.1.16 GAMSET (26h): Gamma Set

26H GAMSET (Gamma Set)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

GAMSET 0 ↑ 1 - 0 0 1 0 0 1 1 0 (26h)

Parameter 1 ↑ 1 - - - - - GC3 GC2 GC1 GC0

-This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be
selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table.

GC [7:0] Parameter Curve Selected

Description

Default

GS=1 GS=0
01h GC0 Gamma Curve 1 (G2.2) Gamma Curve 1 (G1.0)
02h GC1 Gamma Curve 2 (G1.8) Gamma Curve 2 (G2.5)
04h GC2 Gamma Curve 3 (G2.5) Gamma Curve 3 (G2.2)
08h GC3 Gamma Curve 4 (G1.0) Gamma Curve 4 (G1.8)

Note: All other values are undefined.

Status Default Value

Power On Sequence 01h

S/W Reset 01h

H/W Reset 01h

Flow Chart

V1.2 95 2009-03-10

ST7715

10.1.17 DISPOFF (28h): Display Off

28H DISPOFF (Display Off)
Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
DISPOFF 0 ↑ 1 - 0 0 1 0 1 0 0 0 (28h)

Parameter No Parameter -

- This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is
disabled and blank page inserted.

- This command makes no change of contents of frame memory.

- This command does not change any other status.

- There will be no abnormal visible effect on the display.

- Exit from this command by Display On (29h)

- The delay time between DISPON and DISPOFF needs 120ms at least.

Description

Default

(Example)

Memory Display

Note1: Complete 1 frame display (ex: continue 2-falling edges of VS)
Note2: Please use command 28h (display off) combined with command 10h (sleep in) to make module into display
off status. Please check the application note of ST7715 when using display off function.

Status Default Value

Power On Sequence Display off

S/W Reset Display off

H/W Reset Display off

Legend

Command

Flow Chart

Display On

Mode

DISPOFF

Display Off

Mode

Parameter

Display

Action

Mode

Sequential

transter

V1.2 96 2009-03-10

ST7715

10.1.18 DISPON (29h): Display On

29H DISPON (Display On)

DISPON 0 ↑ 1 - 0 0 1 0 1 0 0 1 (29h)

Parameter No Parameter -

- This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled.

- This command makes no change of contents of frame memory.

- This command does not change any other status.

- The delay time between DISPON and DISPOFF needs 120ms at least.

Description

Default

(Example)

Memory Display

Status Default Value

Power On Sequence Display off

S/W Reset Display off
H/W Reset Display off

Legend

Command

Display Off

Mode

Parameter

Display

Flow Chart

DISPON

Display On

Mode

Action

Mode

Sequential

transter

V1.2 97 2009-03-10

ST7715

10.1.19 CASET (2Ah): Column Address Set

2AH CASET(Colume Address Set)_

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX

CASET(2Ah)
1st parameter
2nd parameter
3rd parameter
4th parameter

Description

0 ↑ 1 - 0 0 1 0 1 0 1 0 (2Ah)
1 ↑ 1 - - - - - - - - - ­1 ↑ 1 - XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0
1 ↑ 1 - - - - - - - - -
1 ↑ 1 - XE7 XE6 XE5 XE4 XE3 XE2 XE1 XE0

-The value of XS [7:0] and XE [7:0] are referred when RAMWR command comes.

-Each value represents one column line in the Frame Memory.

XS[7:0] XE[7:0]

Restriction

Default

XS [15:0] always must be equal to or less than XE [15:0]
When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored.

1. 132X132 memory base (GM = ’001’)
(Parameter range: 0 < XS [15:0] < XE [15:0] < 131 (0083h)): MV=”0”)
(Parameter range: 0 < XS [15:0] < XE [15:0] < 131 (0083h)): MV=”1”)

GM Status Status

GM=’001’

(132x132

memory base)

Power On

Sequence
S/W Reset 0000h 0083h (131)
H/W Reset 0000h 0083h (131)

Default Value

XS [7:0] XE [7:0] (MV=’0 ’) XE [7:0] (MV=’1’)

0000h 0083h (131)

V1.2 98 2009-03-10

ST7715

CASET

1st parameter XS[15:0]
2nd parameter XE[15:0]

PASET

Legend

Command

Parameter

Display

Flow Chart

1st parameter YS[15:0]
2nd parameter YE[15:0]

RAMWR

Image Data

D1[7:0],D2[7:0]

… … .Dn[7:0]

Any Command

Action

Mode

Sequential

transter

V1.2 99 2009-03-10

ST7715

10.1.20 RASET (2Bh): Row Address Set

2BH RASET (Row Address Set)

Inst / Para D/CX WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
RASET (2Bh)
1st parameter
2nd parameter
3rd parameter
4th parameter

Description

0 ↑ 1 - 0 0 1 0 1 0 1 1 (2Bh)
1 ↑ 1 - - - - - - - - -
1 ↑ 1 - YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0
1 ↑ 1 - - - - - - - - -
1 ↑ 1 - YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0

The value of YS [7:0] and YE [7:0] are referred when RAMWR command comes.
Each value represents one column line in the Frame Memory.

YS[7:0]

Restriction

Default

YE[7:0]

YS [15:0] always must be equal to or less than YE [15:0]
When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range will be ignored.

1. 132X132 memory base (GM = ’001’)
(Parameter range: 0 < YS [15:0] < YE [15:0] < 131 (0083h)): MV=”0”
(Parameter range: 0 < YS [15:0] < YE [15:0] < 131 (0083h)): MV=”1”

GM status Status

GM=’001’
(132x132

memory base)

Power On

Sequence
S/W Reset 0000h 0083h (131)
H/W Reset 0000h 0083h (131)

Default Value

YS [15:0] YE [15:0] (MV=’0 ’) YE [15:0] (MV=’1’)

0000h 0083h (131)

V1.2 100 2009-03-10