impressive and desirable for accurate power supply design.
1) Powering Up the SP7651EB Circuit
Connect the SP7651 Evaluation Board with an external +12V power supply. Connect
with short leads and large diameter wire directly to the “VIN” and “GND” posts. Connect
a Load between the VOUT and GND2 posts, again using short leads with large
diameter wire to minimize inductance and voltage drops.
2) Measuring Output Load Characteristics
V
OUT
ripple can best be seen touching the probe tip to the pad for C3 and the scope
GND collar touching the GND side of C3 using short wrapped wire around the collar –
avoid a GND lead on the scope which will increase noise pickup.
3)Using the Evaluation Board with Different Output Voltages
While the SP7651 Evaluation Board has been tested and delivered with the output set
to 3.30V, by simply changing one resistor, R2, the SP7651 can be set to other output
voltages. The relationship in the following formula is based on a voltage divider from the
output to the feedback pin VFB, which is set to an internal reference voltage of 0.80V.
Standard 1% metal film resistors of surface mount size 0603 are recommended.
Furthermore, one could select the value of the R1 & R2 combination to meet the exact
output voltage setting by restricting R1 resistance range such that 50KΩ≤ R1 ≤ 100KΩ
for overall system loop stability.
Note that since the SP7651 Evaluation Board design was optimized for 12V down
conversion to 3.30V, changes of output voltage and/or input voltage will alter
performance from the data given in the Power Supply Data section. In addition, the
SP7651ER provides short circuit protection by sensing V
OUT
at GND.
POWER SUPPLY DATA
The SP7651ER is designed with a very accurate 1.0% reference over line, load and
temperature. Figure 1 data shows a typical SP7655 Evaluation Board Efficiency plot,
with efficiencies to 87% (including generation of 5V Vcc) and output currents to 3A.
SP7651ER Load Regulation is shown in Figure 2 to have only 0.5% change in output
voltage from 0.5A load to 3A load. Figures 3 and 4 illustrate a 1.5A to 3A and 0A to 3A
Load Step. Start-up Responses in Figures 5, 6 and 7 show a controlled start-up with
different output load behavior when power is applied where the input current rises
smoothly as the Softstart ramp increases. In Figure 8 the SP7651ER is configured for
hiccup mode in response to an output dead short circuit condition and will Soft-start until
the over-load is removed. Figure 9 and 10 show output voltage ripple less than 25mV at
no load to 3A load.
While data on individual power supply boards may vary, the capability of the SP7651ER
of achieving high accuracy over a range of load conditions shown here is quite
Resr := Output Capacitor Equivalent Series Resitance
Definition
Rdc := Output
Inductor DC Resistance
Vramp_pp := SP7651 Internal RAMP Amplitude Peak to Peak Voltage
Output Load Resistance >> Resr and Rdc
Cz2 >> Cp1 and R1 >> Rz3
Condition
The open loop gain of the SP7651EB can be divided into the gain of the error amplifier
Gamp(s), PWM modulator Gpwm, buck converter output stage Gout(s), and feedback
resistor divider Gfbk. In order to cross over at the selecting frequency fco, the gain of
the error amplifier must compensate for the attenuation caused by the rest of the loop at
this frequency. The goal of loop compensation is to manipulate the open loop frequency
response such that its gain crosses over 0dB at a slope of –20dB/dec. The open loop
crossover frequency should be higher than the ESR zero of the output capacitors but
less than 1/5 to 1/10 of the switching frequency fs to insure proper operation. Since the
SP7651EB is designed with Ceramic Type output capacitors, a Type III compensation
circuit is required to give a phase boost of 180° in order to counteract the effects of the
output LC underdamped resonance double pole frequency.
PWM Stage
(Volts
(Volts
(Volts
Figure 11. Voltage Mode Control Loop with Loop Dynamic for Type III Compensation
The simple guidelines for positioning the poles and zeros and for calculating the
component values for Type III compensation are as follows:
a. Choose fco = fs / 5
b. Calculate fp_LC
fp_LC = 1 / [2π (L ●C) ^ 1/2 ]
c. Calculate fz_ESR
fz_ESR = 1 / 2π (R
ESR
) ● (C
OUT
)
d. Select R1 component value such that 50kΩ≤ R1 ≤ 100kΩ
e. Calculate R2 base on the desired V
R2 = R1 / [(V
OUT
/ 0.80V) – 1]
OUT
f. Select the ratio of Rz2 / R1 gain for the desired gain bandwidth
Rz2 = R1 (V
RAMP_PP
/ VIN_
MAX
) (fco / fp_LC)
g. Calculate Cz2 by placing the zero at ½ of the output filter pole frequency
Cz2 = 1 / [π (Rz2) ● (fp_LC) ]
h. Calculate Cp1 by placing the first pole at ESR zero frequency
Cp1 = 1 / [2π (Rz2) ● (fz_ESR) ]
i. Calculate Rz3 by setting the second pole at ½ of the switching frequency and the
second zero at the output filter double pole frequency
Rz3 = 2 (R1) (fp_LC) / fs
j. Calculate Cz3 from Rz3 component value above
Cz3 = 1 / π (Rz3) ● (fs)
k. Choose 100pF ≤Cf1 ≤ 220pF to stabilize the SP7651ER internal Error Amplifier
Note: Loop Compensation component calculations discussed in this section are
further elaborated in the application note #ANP16, “Loop Compensation of Voltage-Mode Buck Converters”.
These calculations shown here can be quickly iterated with the Type III Loop
Compensation Calculator on the web at: