SIMTEK UL635H256 Technical data
Obsolete - Not Recommended for New Designs
Features Description
UL635H256
Low Voltage PowerStore 32K x 8 nvSRAM
• High-performance CMOS non-
volatile static RAM 32768 x 8 bits
• 35 and 45 ns Access Times
• 15 and 20 ns Output Enable
Access Times
• I
= 8 mA typ. at 200 ns Cycle
CC
Time
• Automatic STORE to EEPROM
on Power Down using system
capacitance
• Software initiated STORE
• Automatic STORE Timing
6
• 10
STORE cycles to EEPROM
• 100 years data retention in
EEPROM
• Automatic RECALL on Power Up
• Software RECALL Initiation
• Unlimited RECALL cycles from
EEPROM
• Wide voltage range: 2.7 ... 3.6 V
(3.0 ... 3.6 V for 35 ns type)
• Operating temperature range:
0 to 70 °C
-40 to 85 °C
• QS 9000 Quality Standard
• ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
• RoHS compliance and Pb- free
• Package:SOP28 (330 mil)
The UL635H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disabled.
The UL635H256 is a fast static
RAM (35 and 45 ns), with a nonvolatile electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resides in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in system
capacitance. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on powerup.
The UL635H256 combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
STORE cycles also may be initiated under user control via a software sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initiated by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
A14
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
A1
A0
DQ0
DQ1
DQ2
VSS
SOP
8
9
10
11
12
13
14
Top View
March 31, 2006
VCC
28
W
27
A13
26
A8
25
A9
24
A11
23
G
22
A10
21
E
20
DQ7
19
DQ6
18
DQ5
17
DQ4
16
DQ3
15
STK Control #ML0059
n. c.
VCC
n. c.
A11
A9
A8
A13
W
A14
A12
A7
A6
A5
A4
A3
Pin Description
G
1
2
3
4
5
6
7
8
TSOP
9
10
11
12
13
14
15
16
Top View
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
n.c.
1
Signal Name Signal Description
A0 - A14 Address Inputs
DQ0 - DQ7 Data In/Out
E
G
W
Chip Enable
Output Enable
Write Enable
VCC Power Supply Voltage
VSS Ground
Rev 1.0
UL635H256
Block Diagram
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Tr uth Table for SRAM Operations
SRAM
Array
512 Rows x
Row Decoder
Input Buffers
64 x 8 Columns
Column I/O
Column Decoder
A0 A1 A2 A3 A4 A10
EEPROM Array
512 x (64 x 8)
STORE
RECALL
Power
Control
Store/
Recall
Control
Software
Detect
V
CC
V
SS
V
CC
A0 - A13
G
E
W
Operating Mode E W G DQ0 - DQ7
Standby/not selected H
**
Internal Read L H H High-Z
Read L H L Data Outputs Low-Z
Write L L
*
Data Inputs High-Z
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V
input levels of V
with the exception of the t
Absolute Maximum Ratings
Power Supply Voltage V
Input Voltage V
Output Voltage V
Power Dissipation P
= 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
IL
-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
dis
a
Symbol Min. Max. Unit
CC
I
O
D
-0.5 4.6 V
-0.3 VCC+0.5 V
-0.3 VCC+0.5 V
, as well as
I
High-Z
1W
Operating Temperature C-Type
K-Type
Storage Temperature T
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
STK Control #ML0059
T
a
stg
2
0
-40
70
85
°C
°C
-65 150 °C
Rev 1.0
March 31, 2006
UL635H256
Recommended
Operating Conditions
Power Supply Voltage V
Input Low Voltage V
Input High Voltage V
Symbol Conditions Min. Max. Unit
t
CC
= 35 ns
c
t
= 45 ns
c
-2 V at Pulse Width
IL
IH
10 ns permitted
DC Characteristics Symbol Conditions
Operating Supply Current
Average Supply Current during
STORE
Operating Supply Current
at tcR = 200 ns
(Cycling CMOS Input Levels)
Average Supply Current during
PowerStore Cycle
Standby Supply Current
(Cycling TTL Input Levels)
b
c
b
c
d
I
CC1
I
CC2
I
CC3
I
CC4
I
CC(SB)1
V
V
V
t
t
V
E
W
V
V
V
W
V
V
V
V
V
V
E
CC
IL
IH
c
c
CC
= 3.6 V
= 0.8 V
= 2.2 V
= 35 ns
= 45 ns
= 3.6 V
≤ 0.2 V
≥ V
-0.2 V
CC
IL
IH
CC
IL
IH
CC
IL
IH
CC
≤ 0.2 V
≥ V
CC
= 3.6 V
≥ V
CC
≤ 0.2 V
≥ V
CC
= V
CCmin
= 0.2 V
≥ V
CC
= 3.6 V
= V
IH
-0.2 V
-0.2 V
-0.2 V
-0.2 V
3.0
2.7
3.6
3.6
-0.3 0.8 V
2.2 VCC+0.3 V
C-Type K-Type
Min. Max. Min. Max.
45
35
47
37
34mA
10 11 mA
22mA
V
V
Unit
mA
mA
Standby Supply Curent
d
(Stable CMOS Input Levels)
b: I
and I
CC1
The current I
and I
c: I
CC2
d: Bringing E
table. The current I
March 31, 2006
are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC3
is measured for WRITE/READ - ratio of 1/2.
CC1
are the average currents required for the duration of the respective STORE cycles.
CC4
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
CC(SB)1
STK Control #ML0059
t
c
t
c
I
CC(SB)
V
CC
E
V
IL
V
IH
is measured for WRITE/READ - ratio of 1/2.
3
= 35 ns
= 45 ns
= 3.6 V
≥ V
CC
≤ 0.2 V
≥ V
CC
-0.2 V
-0.2 V
Rev 1.0
11
9
12
10
mA
mA
11mA
UL635H256
DC Characteristics Symbol Conditions
C-Type K-Type
Unit
Min. Max. Min. Max.
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
SRAM Memory Operations
Switching Characteristics
No.
Read Cycle
High
Low
V
V
I
OH
I
OL
I
I
I
OHZ
I
OLZ
OH
OL
IH
IL
V
I
I
V
V
V
V
V
V
V
V
V
CC
OH
OL
CC
OH
OL
CC
IH
IL
CC
OH
OL
= V
CC
min
=-2 mA
2.4
= 2 mA
= V
CC
min
= 2.4 V
= 0.4 V 2
= 3.6 V
= 3.6 V
= 0 V -1
= 3.6 V
= 3.6 V
= 0 V -1
2.4
0.4
-2
2
1
-1
1
-1
Symbol 35 45
Alt. IEC Min.Max.Min.Max.
0.4
-2 mA
mA
1 μA
μA
1 μA
μA
Unit
V
V
1 Read Cycle Time
2 Address Access Time to Data Valid
f
g
3 Chip Enable Access Time to Data Valid t
4 Output Enable Access Time to Data
Valid
HIGH to Output in High-Z
5E
6G
HIGH to Output in High-Z
h
h
7E LOW to Output in Low-Z t
LOW to Output in Low-Z t
8G
9 Output Hold Time after Address Change t
10 Chip Enable to Power Active
11 Chip Disable to Power Standby
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E
g: Address valid prior to or coincident with E
h: Measured ± 200 mV from steady state output voltage.
e
d, e
and G both Low.
transition LOW.
t
AVAV
t
AVQ V
ELQV
t
GLQV
t
EHQZ
t
GHQZ
ELQX
GLQX
AXQX
t
ELICCH
t
EHICCL
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
t
PU
t
PD
35 45 ns
35 45 ns
35 45 ns
15 20 ns
13 15 ns
13 15 ns
55ns
00ns
33ns
00ns
35 45 ns
STK Control #ML0059
4
Rev 1.0
March 31, 2006
UL635H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)
t
(1)
cR
Ai
DQi
Output
Previous Data Valid
t
v(A)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)
Ai
E
t
t
en(G)
t
PU
en(E)
(10)
G
DQi
DQi
Output
Output
I
CC
High Impedance
ACTIVE
STANDBY
Address Valid
t
(2)
a(A)
(9)
t
(1)
cR
Address Valid
t
(2)
a(A)
t
(3)
a(E)
(7)
t
a(G)
(8)
g
(4)
Output Data Valid
f
Output Data Valid
t
(11)
PD
t
dis(E)
(5)
t
(6)
dis(G)
Switching Characteristics
No.
Write Cycle
12 Write Cycle Time t
13 Write Pulse Width t
Alt. #1 Alt. #2 IEC
AVAV
WLWH
14 Write Pulse Width Setup Time t
15 Address Setup Time t
16 Address Valid to End of Write t
17 Chip Enable Setup Time t
AVW L
AVW H
ELWH
18 Chip Enable to End of Write t
19 Data Setup Time to End of Write t
20 Data Hold Time after End of Write t
21 Address Hold after End of Write t
22 W
LOW to Output in High-Z
h, i
23 W HIGH to Output in Low-Z t
DVWHtDVEH
WHDXtEHDX
WHAXtEHAX
t
WLQZ
WHQX
Symbol 35 45
t
AVAV
WLEH
t
AVEL
t
AVEH
ELEH
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(A-WH)
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
en(W)
Min. Max.
35 45 ns
25 30 ns
25 30 ns
00ns
25 30 ns
25 30 ns
25 30 ns
12 15 ns
00ns
00ns
13 15 ns
55ns
Min. Max.
Unit
March 31, 2006
STK Control #ML0059
5
Rev 1.0
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