SIMTEK STK25C48-W45I, STK25C48-W45, STK25C48-W35I, STK25C48-W35, STK25C48-W25I Datasheet

STK25C48

2K x 8 AutoStore™ nvSRAM

QuantumTrap™ CMOS

Nonvolatile Static RAM

FEATURES

• Nonvolatile Storage without Battery Problems

• Directly Replaces 2K x 8 Static RAM, Battery-

Backed RAM or EEPROM

• 20ns, 25ns, 35ns and 45ns Access Times

• STORE to EEPROM Initiated by AutoStore™

on Power Down

• RECALL to SRAM Initiated by Software or
Power Restore

• 10mA Typical I

at 200ns Cycle Time

CC

• Unlimited READ, WRITE and RECALL Cycles

• 1,000,000 STORE Cycles to EEPROM

• 100-Y ear Data Retention over Full Industrial

Temperature Range

• Commercial and Industrial Temperatures

• 24-Pin 600 PDIP Package

BLOCK DIAGRAM

EEPROM ARRAY

32 x 51 2

A

5

A

6

A

7

A

8

A

9

STA TIC RAM

ARRAY

32 x 512

ROW DECO DE R

STORE

RECALL

STORE/

RECALL

CONTROL

DESCRIPTION

The STK25C48 is a fast SRAM with a nonvolatile

EEPROM element incorporated in each static memory

cell. The
number of times, while independent nonvolatile data
resides in the EEPROM. Data transfers from the SRAM to
the
matically on power down using charge stored in system
capacitance. Transfers from the EEPROM to the SRAM
(the RECALL opera tion) take place auto maticall y on res­toration of power. The nv
existing 2K x 8
2K x 8 battery-backed
allowing direct substitution while enhancing performance.
There i s no limit on t h e number o f r ead or wr i t e cyc les that
can be executed, and no support circuitry is required for
microprocessor interfacing.

SRAM can be read and written an unlimited

EEPROM (the STORE operation) can take place auto-

SRAM can be used in place of

SRAMs and also matches the pinout of

SRAMs, EPROMs and EEPROMs,

PIN CONFIGURATIONS

A

V

CC

POWER

CONTROL

DQ
DQ
DQ

V

6

1

A

5

2

A

4

3

A

3

4

A

2

5

A

1

6

A

0

7

0

8

1

9

2

10

SS

11
12

V

24

CC

23

A

8

22

A

9

21

W
G

20

A

19

10

18

E

17

DQ
DQ

DQ
DQ
DQ

7
6
5
4

3

24 - 600 PDIP

16
15
14
13

DQ
DQ
DQ
DQ

DQ
DQ

DQ
DQ

0
1
2
3

4
5

6
7

INPUT BUFFERS

COLUMN I/O

COLUMN DEC

A0A

2

1

A

A3A

A

10

4

July 1999 3-31

PIN NAM ES

A0 - A

10

W Write E nable
DQ0 - DQ

G

E
W

E Chip Enable
G Output Enable
V

CC

V

SS

7

Address I nputs

Data In/Out

Power (+ 5V)
Ground

STK25C48

ABSOLUT E MAXIMUM RATINGS

Voltage on Input Relative to VSS. . . . . . . . . . –0.6V to (VCC + 0.5V)

Voltage on DQ

Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W

DC Output Current (1 output at a time, 1s duration). . . . . . . .15mA

. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)

0-7

a

Note a: Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi­tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat­ing conditions for extended periods may affect reliability.

DC CHARACTERISTICS (VCC = 5.0V ± 10%)

SYMBOL PARAMETER

c

I

CC

I

CC

I

CC

I

CC

I

SB

I

SB

I

ILK

I

OLK

V
V
V
V
T

IH
IL
OH
OL

A

Average VCC Current 95

1

d

Average VCC Current during STORE 33mAAll Inputs Don’t Car e, VCC = max

2

c

Average VCC Current at t

3

5V, 25°C, Typical

d

Average V

4

AutoStore™ Cycle

e

Average VCC Current

1

(Standby, Cyclin g TT L Input Levels)

e

VCC Sta ndby Current

2

(Standby, Stable CMOS Input Levels)
Input Leakage Current

Off-State Output Leakage Cu r r ent

Input Logic “1” Voltage 2.2 V
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 –40 85 °C

Current during

CAP

AVAV

= 200ns

Note b: The STK25C48-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
Note d: I
Note e: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.

CC
CC

and I

1

and I

2

are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

CC

3

are the average currents required for the duration of the respective STORE cycles (t

CC

4

COMMERCIAL INDUSTRIAL

MIN MAX MIN MAX

N/A
85
75
65

10 10 mA

22mA

30
25
21
18

1.5 1.5 mA

±1 ±1 µA

±5 ±5 µA

+ .5 2.2 VCC + .5 V All Inputs

CC

90
75
65

N/A

26
22
19

UNITS NOTES

mA
mA
mA
mA

mA
mA
mA
mA

t

= 20ns

AVAV

t

= 25ns

AVAV

t

= 35ns

AVAV

t

= 45ns

AVAV

W

≥ (V

– 0.2V)

CC

All Others Cycling, CMOS Levels
All Inputs Don’t Car e

t

= 20ns, E ≥ V

AVAV

t

AVAV

t

AVAV

t

AVAV

E

≥ (VCC – 0.2V)

All Others V
V

CC

V

= VSS to V

IN

V

CC

V

= V

IN

OUT
OUT

).

STORE

= 25ns, E ≥ V

= 35ns, E ≥ V
= 45ns, E ≥ V

= max

= max

SS

= – 4mA
= 8mA

IH
IH
IH
IH

≤ 0.2V or ≥ (VCC – 0.2V)

IN

CC

to VCC, E or G ≥ VIH

b

AC TEST CO NDITIONS

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V

Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V

Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1

CAPACITANCE

SYMBOL PARAMETER MAX UNITS CONDITIONS

C

IN

C

OUT

Note f: These parameters are guaranteed but not tested.

Input Capacitance
Output Capacitance

f

(TA = 25°C, f = 1.0MHz)

8pF∆V = 0 to 3V
7pF∆V = 0 to 3V

July 1999 3-32

OUTPUT

5.0V

480 Ohms

30 pF

255 Ohms

INCLUDING
SCOPE AN D
FIXTURE

Figure 1: AC Output Loading

STK25C48

SRAM READ CYCLES #1 & #2 (V

NO.

10 t
11 t

#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX

1t

ELQV

2t

AVAV

3t

AVQV

4t

GLQV

5t

AXQX

6t

ELQX

7t

EHQZ

8t

GLQX

9t

GHQZ
ELICCH
EHICCL

SYMBOLS

g

h

h

i

i

f

e, f

t

ACS

t

RC

t

AA

t

OE

t

OH

t

LZ

t

HZ

t

OLZ

t

OHZ

t

PA

t

PS

Chip Enable Ac c es s Time 20 25 35 45 ns
Read Cycle Time 20 25 35 45 ns
Address Access Time 22 25 35 45 ns
Output Enable to Data Valid 8 10 15 20 ns
Output Hold after Address Change 5 5 5 5 ns
Chip Enable to Output Active 5 5 5 5 ns
Chip Disable to Output Inac tive 7 10 13 15 ns
Output Enable to Output Active 0 0 0 0 ns
Outpu t Disable to Output Inactive 7 10 13 15 ns
Chip Enable to Power Active 0 0 0 0 ns
Chip Disable to Power S tandby 25 25 35 45 ns

PARAMETER

Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note i: Measured + 200mV from steady state output voltage.

SRAM READ CYCLE #1: Address Cont rolled

ADDRESS

t

AVQV

DQ (DATA OUT)

t

AXQX

5

STK25C48-20 STK25C48-25 STK25C48-35 STK25C48-45

g, h

2

t

AVAV

3

DATA VALID

= 5.0V ± 10%)

CC

b

UNITS

SRAM READ CYCLE #2: E Controlled

ADDRESS

t

ELQX

t

ELICCH

6

t

GLQX

10

4

t

GLQV

8

DQ (DAT A OUT)

I

CC

E

G

STANDBY

g

t

AVAV

2

1

t

ELQV

ACTIVE

DATA VALID

t

GHQZ

9

t

EHQZ

t

EHICCL

7

11

July 1999 3-33