SIMTEK STK25C48-W45I, STK25C48-W45, STK25C48-W35I, STK25C48-W35, STK25C48-W25I Datasheet
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STK25C48
2K x 8 AutoStore™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• Nonvolatile Storage without Battery Problems
• Directly Replaces 2K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 20ns, 25ns, 35ns and 45ns Access Times
• STORE to EEPROM Initiated by AutoStore™
on Power Down
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
at 200ns Cycle Time
CC
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Y ear Data Retention over Full Industrial
Temperature Range
• Commercial and Industrial Temperatures
• 24-Pin 600 PDIP Package
BLOCK DIAGRAM
EEPROM ARRAY
32 x 51 2
A
5
A
6
A
7
A
8
A
9
STA TIC RAM
ARRAY
32 x 512
ROW DECO DE R
STORE
RECALL
STORE/
RECALL
CONTROL
DESCRIPTION
The STK25C48 is a fast SRAM with a nonvolatile
EEPROM element incorporated in each static memory
cell. The
number of times, while independent nonvolatile data
resides in the EEPROM. Data transfers from the SRAM to
the
matically on power down using charge stored in system
capacitance. Transfers from the EEPROM to the SRAM
(the RECALL opera tion) take place auto maticall y on restoration of power. The nv
existing 2K x 8
2K x 8 battery-backed
allowing direct substitution while enhancing performance.
There i s no limit on t h e number o f r ead or wr i t e cyc les that
can be executed, and no support circuitry is required for
microprocessor interfacing.
SRAM can be read and written an unlimited
EEPROM (the STORE operation) can take place auto-
SRAM can be used in place of
SRAMs and also matches the pinout of
SRAMs, EPROMs and EEPROMs,
PIN CONFIGURATIONS
A
V
CC
POWER
CONTROL
DQ
DQ
DQ
V
6
1
A
5
2
A
4
3
A
3
4
A
2
5
A
1
6
A
0
7
0
8
1
9
2
10
SS
11
12
V
24
CC
23
A
8
22
A
9
21
W
G
20
A
19
10
18
E
17
DQ
DQ
DQ
DQ
DQ
7
6
5
4
3
24 - 600 PDIP
16
15
14
13
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
1
2
3
4
5
6
7
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A0A
2
1
A
A3A
A
10
4
July 1999 3-31
PIN NAM ES
A0 - A
10
W Write E nable
DQ0 - DQ
G
E
W
E Chip Enable
G Output Enable
V
CC
V
SS
7
Address I nputs
Data In/Out
Power (+ 5V)
Ground
STK25C48
ABSOLUT E MAXIMUM RATINGS
Voltage on Input Relative to VSS. . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC Output Current (1 output at a time, 1s duration). . . . . . . .15mA
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
0-7
a
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
SYMBOL PARAMETER
c
I
CC
I
CC
I
CC
I
CC
I
SB
I
SB
I
ILK
I
OLK
V
V
V
V
T
IH
IL
OH
OL
A
Average VCC Current 95
1
d
Average VCC Current during STORE 33mAAll Inputs Don’t Car e, VCC = max
2
c
Average VCC Current at t
3
5V, 25°C, Typical
d
Average V
4
AutoStore™ Cycle
e
Average VCC Current
1
(Standby, Cyclin g TT L Input Levels)
e
VCC Sta ndby Current
2
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Cu r r ent
Input Logic “1” Voltage 2.2 V
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 –40 85 °C
Current during
CAP
AVAV
= 200ns
Note b: The STK25C48-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
Note d: I
Note e: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
CC
CC
and I
1
and I
2
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
are the average currents required for the duration of the respective STORE cycles (t
CC
4
COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX
N/A
85
75
65
10 10 mA
22mA
30
25
21
18
1.5 1.5 mA
±1 ±1 µA
±5 ±5 µA
+ .5 2.2 VCC + .5 V All Inputs
CC
90
75
65
N/A
26
22
19
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
t
= 20ns
AVAV
t
= 25ns
AVAV
t
= 35ns
AVAV
t
= 45ns
AVAV
W
≥ (V
– 0.2V)
CC
All Others Cycling, CMOS Levels
All Inputs Don’t Car e
t
= 20ns, E ≥ V
AVAV
t
AVAV
t
AVAV
t
AVAV
E
≥ (VCC – 0.2V)
All Others V
V
CC
V
= VSS to V
IN
V
CC
V
= V
IN
OUT
OUT
).
STORE
= 25ns, E ≥ V
= 35ns, E ≥ V
= 45ns, E ≥ V
= max
= max
SS
= – 4mA
= 8mA
IH
IH
IH
IH
≤ 0.2V or ≥ (VCC – 0.2V)
IN
CC
to VCC, E or G ≥ VIH
b
AC TEST CO NDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
CAPACITANCE
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
Note f: These parameters are guaranteed but not tested.
Input Capacitance
Output Capacitance
f
(TA = 25°C, f = 1.0MHz)
8pF∆V = 0 to 3V
7pF∆V = 0 to 3V
July 1999 3-32
OUTPUT
5.0V
480 Ohms
30 pF
255 Ohms
INCLUDING
SCOPE AN D
FIXTURE
Figure 1: AC Output Loading
STK25C48
SRAM READ CYCLES #1 & #2 (V
NO.
10 t
11 t
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1t
ELQV
2t
AVAV
3t
AVQV
4t
GLQV
5t
AXQX
6t
ELQX
7t
EHQZ
8t
GLQX
9t
GHQZ
ELICCH
EHICCL
SYMBOLS
g
h
h
i
i
f
e, f
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Ac c es s Time 20 25 35 45 ns
Read Cycle Time 20 25 35 45 ns
Address Access Time 22 25 35 45 ns
Output Enable to Data Valid 8 10 15 20 ns
Output Hold after Address Change 5 5 5 5 ns
Chip Enable to Output Active 5 5 5 5 ns
Chip Disable to Output Inac tive 7 10 13 15 ns
Output Enable to Output Active 0 0 0 0 ns
Outpu t Disable to Output Inactive 7 10 13 15 ns
Chip Enable to Power Active 0 0 0 0 ns
Chip Disable to Power S tandby 25 25 35 45 ns
PARAMETER
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note i: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Cont rolled
ADDRESS
t
AVQV
DQ (DATA OUT)
t
AXQX
5
STK25C48-20 STK25C48-25 STK25C48-35 STK25C48-45
g, h
2
t
AVAV
3
DATA VALID
= 5.0V ± 10%)
CC
b
UNITS
SRAM READ CYCLE #2: E Controlled
ADDRESS
t
ELQX
t
ELICCH
6
t
GLQX
10
4
t
GLQV
8
DQ (DAT A OUT)
I
CC
E
G
STANDBY
g
t
AVAV
2
1
t
ELQV
ACTIVE
DATA VALID
t
GHQZ
9
t
EHQZ
t
EHICCL
7
11
July 1999 3-33
STK25C48
SRAM WRITE CYCLES #1 & #2 (V
NO.
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
WLWH
DVWH
WHDX
AVWH
WHAX
WLQZ
WHQX
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
AVAV
ELWH
AVWL
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
i, j
t
Write Cycle Time 20 25 35 45 ns
WC
t
Write Pul s e Width 15 20 25 30 ns
WP
t
Chip Enable t o E nd of Write 15 20 25 30 ns
CW
t
Data Set-up to End of Write 8 10 12 15 ns
DW
t
Data Ho ld afte r En d of Write 0 0 0 0 ns
DH
t
Address Set -up to End of Write 15 20 25 30 ns
AW
t
Addr es s S et-up t o Star t of Write 0 0 0 0 ns
AS
t
Addr es s Hold af ter End of Write 0 0 0 0 ns
WR
t
Write Ena ble to Output Disable 7 1 0 13 15 ns
WZ
t
Output Active after End of Write 5 5 5 5 ns
OW
PARAMETER
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E
or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlled
ADDRESS
t
E
ELWH
STK25C48-20 STK25C48-25 STK25C48-35 STK25C48-45
k
12
t
AVAV
14
19
t
WHAX
= 5.0V ± 10%)
CC
b
UNITS
17
t
20
t
WLQZ
AVWH
13
t
WLWH
W
DATA IN
DAT A OUT
t
AVWL
18
PREVIOUS DAT A
SRAM WRITE CYCLE #2: E Controlled
ADDRESS
18
t
E
W
DATA IN
AVEL
1 7
t
AVEH
15
t
DVWH
DATA VALI D
HIGH IMPEDANCE
16
t
WHDX
21
t
WHQX
k
12
t
AVAV
t
ELEH
14
13
t
WLEH
15
t
DVEH
DATA VALI D
t
EHAX
16
t
EHDX
19
DAT A OUT
HIGH IMPEDANCE
July 1999 3-34
STK25C48
AutoStore™/POWER-UP RECALL (V
NO.
22 t
23 t
24 t
25 V
26 V
Note l: t
SYMBOLS
Standard MIN MAX
RESTORE
STORE
DELAY
SWITCH
RESET
starts from the time VCC rises above V
RESTORE
Power-up RECALL Dur ation 550 µsl
STORE Cycle Duration 10 ms h
Time Al lowed to Complete SRAM Cycle 1 µsh
Low Voltage Trigger Level 4.0 4.5 V
Low Voltage Re s et Level 3.6 V f
SWITCH
PARAMETER
.
AutoStore™/POWER-UP RECALL
V
CC
5V
25
V
SWITCH
26
V
RESET
= 5.0V ± 10%)
CC
STK25C48
UNITS NOTES
b
AutoStore™
OWER-UP RECALL
W
DQ (DATA OUT)
22
t
RESTORE
POWER-UP
RECALL
BROWN OUT
NO STORE DUE TO
NO SRAM WRITES
NO RECALL
(V
DID NOT GO
CC
BELOW V
RESET
)
t
DELAY
BROWN OUT
AutoStore™
NO RECALL
(V
DID NOT GO
CC
BELOW V
24
RESET
23
t
STORE
BROWN OUT
AutoStore™
RECALL WHEN
V
RETURNS
CC
)
ABOVE V
SWITCH
July 1999 3-35
STK25C48
DEVICE OPERATION
The STK25C48 is a versatile memory chip that provides several modes of operation. The STK25C48
can operate as a standard 8K x 8
8K x 8
EEPROM shadow to which the SRAM infor ma-
tion can be copied, or from which the
SRAM. It has an
SRAM can be
updated in nonvolatile mode.
NOISE CO NSIDERATIONS
Note that the STK25C48 is a high-speed memory
and so must have a high-frequency bypass capacitor of approximately 0.1µF connected between V
CC
and VSS, using leads and traces that are as short as
possible. As with all high-speed
CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK25C48 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A
bytes will be accessed. When the
by an address transition, the outputs will be valid
after a delay of t
initiated by E
at t
, whichever is later (READ cycle #2). The data
GLQV
outputs will rep eatedly respond to addr ess chan ges
within the t
sitions on any control input pins, and will remain valid
until another address change or until E
brought high or W
determines which of the 2,048 data
0-10
READ is initiated
(READ cycle #1). If the READ is
AVQV
or G, the outputs will be valid at t
access time without the need for tran-
AVQV
or G is
is brought low.
ELQV
or
AutoStore™ OPERATION
The STK25C48 uses the intrinsic system capacitance to perform an automatic store on power down.
As long as the system power supply takes at least
t
to decay from V
STORE
down to 3.6V, the
SWITCH
STK25C48 will safely and automatically store the
SRAM data in EEPROM on power down.
In order to prevent unneeded
automatic
WRITE operation has taken place since the most
recent
STORE will be ignored unless at least one
STORE or RECALL cycle .
STORE operations,
POWER-UP RECALL
During power up, or after any low-power condition
(V
< V
CC
latched. When V
voltage of V
be initiated and will take t
If the STK25C48 is in a
power-up
), an internal RECALL request will be
RESET
once again exceeds the sense
CC
, a RECALL cycle will automatically
SWITCH
RESTORE
RECALL, the SRAM data will be corrupted.
to compl e te .
WRITE state at the end of
To help avoid this situation, a 10K Ohm resistor
should be connected either between W
V
or between E and system VCC.
CC
and system
HARDWARE PROTECT
The STK25C48 offers hardware protection against
inadvertent
during low-voltage conditions. When V
STORE operations and SRAM WRITEs are inhibited.
STORE operation and SRAM WRITEs
< V
CC
SWITCH
,
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the
until either E
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W
E
controlled WRITE or t
controlled WRITE.
It is recommended that G
entire
WRITE cycle to avoid data bus contention on
the common I/O lin es. If G
will turn off t he out put buffers t
WRITE cycle and must remain stable
or W goes high at the end of the cycle.
will be writ-
0-7
before the end
DVWH
before the end of an
DVEH
be kept high during the
is left low, internal circuitry
after W goes low.
WLQZ
July 1999 3-36
LOW AVERAGE ACTIVE PO WER
The STK25C48 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
perature range, V
= 5.5V, 100% duty cycle on chip
CC
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK25C48 depends on the following items:
1)
CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of
temperature; 6) the V
READs to WRITEs; 5) the operating
level; and 7) I/O loading.
CC
and READ cycle
CC
STK25C48
100
Average Active Current (mA)
80
60
40
20
0
50 100 150 200
Cycle Time (ns)
Figure 2: ICC (max) Reads
TTL
CMOS
100
Average Active Current (mA)
80
60
40
20
0
50 100 150 200
Cycle Time (ns)
Figure 3: ICC (max) Writes
TTL
CMOS
July 1999 3-37
STK25C48
ORDERING INFORMA TION
STK25C48
- W 25 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C
Access Time
20 = 20ns (Commercial only)
25 = 25ns
35 = 35ns
45 = 45ns
Package
W = Plastic 24-pin 600 mil DIP
)
July 1999 3-38
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