SIMTEK STK22C48-N25I, STK22C48-N25, STK22C48-N20, STK22C48-P45, STK22C48-P35I Datasheet

July 1999 3-21

PIN CONFIGURATIONS

V

CAP

NC

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

DQ

0

DQ

1

DQ

2

V

SS

V

CCX

HSB
A

8

A

9

NC
G

W

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

A

10

E
DQ

7

DQ

6

DQ

5

DQ

4

DQ

3

28 - 300 PDIP
28 - 600 PDIP
28 - 300 SOIC
28 - 350 SOIC

PIN NAMES

A0 - A

10

Address In puts

DQ

0

-DQ7Data In/Out

E

Chip Enable

W

Write Ena ble

G

Output Enable

HSB

Hardware Store Busy (I/O)

V

CCX

Power (+ 5V)

V

CAP

Capacitor

V

SS

Ground

STK22C48

2K x 8 AutoStore™ nvSRAM

QuantumTrap™ CMOS

Nonvolatile Static RAM

FEATURES

• 20ns, 25ns, 35ns and 45ns Access Times

•“Hands-off” Automatic STORE with External

68µF Capacitor on Power Down

• STORE to EEPROM Initiated by Hardware or
AutoStore™ on Power Down

• Automatic RECALL on Power Up

• 10mA Typical I

CC

at 200ns Cycle Time

• Unlimited READ, WRITE and RECALL Cycles

• 1,000,000 STORE Cycles to EEPROM

• 100-Y ear Data Retention in EEPROM

• Single 5 V +

10% Operation

• Not Sensitive to Power On/Off Ramp Rates

• No Data Loss from Under s hoot

• Commercial and Industrial Temperatures

• 28-Pin DIP and SOIC Packages

DESCRIPTION

The Simtek STK22C48 is a fast static RAM with a
nonvolatile, electrically erasable

PROM element

incorporated in each static memory cell. The

SRAM

can be read and written an unlimited number of
times, while independent, nonvolatile data resides in

EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation) can take place

automatically on power down. A 68µF or larger
capacitor tied from V

CAP

to ground guarantees the

STORE operation, regardless of power-down slew

rate or loss of power from “hot swapping”. Transfers
from the

EEPROM to the SRAM (the RECALL opera-

tion) take place automatically on restoration of
power. A hardware

STORE may be initiated with the

HSB

pin.

BLOCK DIAGRAM

COLUMN I/O

COLUMN DEC

STATIC RAM

ARRAY

32 x 512

ROW DECO DE R

INPUT BUFFERS

EEPROM ARRAY

32 x 512

STORE/

RECALL

CONTROL

STORE

RECALL

POWER

CONTROL

A

5

A

6

A

9

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

G

E
W

A

8

A

7

A

10

A3A

2

A0A

1

A

4

V

CCXVCAP

HSB

STK22C48

July 1999 3-22

ABSOLUT E MAXIMUM RATINGS

a

Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V)

Voltage on DQ

0-7

or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)

Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA

Note a: Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con­ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat­ing conditions for extended periods may affect reliability.

DC CHARAC TERISTICS (VCC = 5.0V ± 10%)

b, f

Note b: The STK22C48-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I

CC

1

and I

CC

3

are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

Note d: I

CC

2

and I

CC

4

are the average currents required for the duration of the respective STORE cycles (t

STORE

).
Note e: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Note f: VCC reference levels throughout this datasheet refer to V

CCX

if that is where the power supply connection is made, or V

CAP

if V

CCX

is con-

nected to ground.

SYMBOL PARAMETER

COMMERCIAL INDUSTRIAL

UNITS NOTES

MIN MAX MIN MAX

I

CC

1

c

Average VCC Curre nt 95

85
75
65

N/A

90
75
65

mA
mA
mA
mA

t

AVAV

= 20ns

t

AVAV

= 25ns

t

AVAV

= 35ns

t

AVAV

= 45ns

I

CC

2

d

Average VCC Current during STORE 3 3 mA All Inpu ts Do n’t Car e , VCC = max

I

CC

3

c

Average V

CC

Current at t

AVAV

= 200ns

5V, 25°C, Typical

10 10 mA

W

≥ (V

CC

– 0.2V)

All Others Cycling, CMOS Levels

I

CC

4

d

Average V

CAP

Current during

AutoStore™ Cycle

22mA

All Inputs Don’t Car e

I

SB

1

e

Average V

CC

Current

(Standby, Cycling TTL I nput Levels)

30
25
21
18

N/A

26
22
19

mA
mA
mA
mA

t

AVAV

= 20ns, E ≥ V

IH

t

AVAV

= 25ns, E ≥ V

IH

t

AVAV

= 35ns, E ≥ V

IH

t

AVAV

= 45ns, E ≥ V

IH

I

SB

2

e

V

CC

St andby Current

(Standby, Stable CMOS Input Levels)

1.5 1.5 mA

E

≥ (VCC – 0.2V)

All Others V

IN

≤ 0.2V or ≥ (VCC – 0.2V)

I

ILK

Input Leakage Current

±1 ±1 µA

V

CC

= max

V

IN

= VSS to V

CC

I

OLK

Off-State Outp ut Leakage Current

±5 ±5 µA

V

CC

= max

V

IN

= VSS to VCC, E or G ≥ VIH

V

IH

Input Logic “1” V o ltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs

V

IL

Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs

V

OH

Output Logic “1” Voltage 2.4 2.4 V I

OUT

= –4mA exc ept HSB

V

OL

Output Logic “0” Voltage 0.4 0.4 V I

OUT

= 8mA except HS B

V

BL

Logic “0” V oltage on HSB Output 0.4 0.4 V I

OUT

= 3mA

T

A

Operating Temperature 0 70 –40 85 °C

AC TEST CO NDITIONS

CAPACITANCE

g

(TA = 25°C, f = 1.0MHz)

Note g: These parameters are guaranteed but not tested.

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V

Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns

Input and Output Timing Reference Levels . . . . . . . . . . . . . . .1.5V

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

SYMBOL PARAMETER MAX UNITS CONDITIONS

C

IN

Input Capacitance 8 pF ∆V = 0 to 3V

C

OUT

Output Cap ac itance 7 pF ∆V = 0 to 3V

Figure 1: AC Output Loading

480 Ohms

30 pF

255 Ohm s

5.0V

INCLUDING

SCOPE AN D

OUTPUT

FIXTURE

STK22C48

July 1999 3-23

SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)b,

f

Note h: W and HSB must be high durin g SRAM READ cycles.
Note i: Device is continuously selected with E

and G both low.

Note j: Measured ± 200mV from steady state output voltage.

SRAM READ CYCLE #1: Ad d r es s Co ntrolledh,

i

SRAM READ CYCLE #2: E Controlled

h

NO.

SYMBOLS

PARAMETER

STK22C48-20 STK22C48-25 STK22C48-35 STK22C48-45

UNITS

#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX

1t

ELQV

t

ACS

Chip Enable Access Time 20 25 35 45 ns

2t

AVAV

h

t

RC

Read Cycle Time 20 25 35 45 ns

3t

AVQV

i

t

AA

Address Access Time 22 25 35 45 ns

4t

GLQV

t

OE

Output Enable to Data Valid 8 10 15 20 ns

5t

AXQX

i

t

OH

Output Hol d after Address Ch ange 5 5 5 5 ns

6t

ELQX

t

LZ

Chip Enable to Output Active 5 5 5 5 ns

7t

EHQZ

j

t

HZ

Chip Disable to Output Inactive 7 10 13 15 ns

8t

GLQX

t

OLZ

Output Enable to Output Active 0 0 0 0 ns

9t

GHQZ

j

t

OHZ

Output Disable to Output Inactive 7 10 13 15 ns

10 t

ELICCH

g

t

PA

Chip Enable to Power Activ e 0 0 0 0 ns

11 t

EHICCL

g

t

PS

Chip Disable to Power Standby 25 25 35 45 ns

DATA VALID

5

t

AXQX

3

t

AVQV

DQ (DATA OUT)

ADDRESS

2

t

AVAV

6

t

ELQX

STANDBY

DATA VALID

8

t

GLQX

4

t

GLQV

Q (DATA OUT)

E

ADDRESS

2

t

AVAV

G

I

CC

ACTIVE

1

t

ELQV

10

t

ELICCH

11

t

EHICCL

7

t

EHQZ

9

t

GHQZ