SIMTEK STK20C04-W45, STK20C04-W45I, STK20C04-W35I, STK20C04-W30I, STK20C04-W35 Datasheet

STK20C04

STK20C04

CMOS nvSRAM

High Performance

512 x 8 Nonvolatile Static RAM

FEATURES

• 30, 35 and 45ns Access Times

• 15, 20 and 25ns Output Enable Access

• Unlimited Read and Write to

• Hardware

• Automatic

5

• 10

STORE

STORE

STORE

Initiation

Timing

cycles to EEPROM

SRAM

• 10 year data retention in EEPROM

• Automatic

• Hardware

• Unlimited

RECALL
RECALL
RECALL

on Power Up
Initiation
cycles from EEPROM

• Single 5V±10% Operation

• Commercial and Industrial Temperatures

• Available in 600 mil PDIP package

LOGIC BLOCK DIAGRAM

EEPROM ARRAY

64 X 64

A

3

A

4

A

5

A

6

A

7

A

8

ROW DECODER

STATIC RAM

ARRAY
64 X 64

STORE

RECALL

DESCRIPTION

The Simtek STK20C04 is a fast static RAM (30, 35,
45ns), with a nonvolatile electrically-erasable PROM
(EEPROM) element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent nonvolatile data
resides in EEPROM. Data may easily be transferred
from the SRAM to the EEPROM (

EEPROM to the SRAM (

RECALL

STORE

), or from the

) using the NE pin. It
combines the high performance and ease of use of a
fast

SRAM with nonvolatile data integrity.

The STK20C04 features the industry standard pinout
for nonvolatile RAMs in a 28-pin 600 mil plastic DIP.

PIN CONFIGURATIONS

DQ
DQ
DO

1

NE

2

NC

3

A

7

4

A

6

5

A

5

6

A

4

7

A

3

8

A

2

9

A

1

10

A

0

11

0

12

1

13

2

14

V

SS

28

V

CC

W

27
26

NC

25

A

8

24

NC
NC

23
22

G

21

NC

20

E
DQ

19
18

17
16
15

DQ
DQ
DQ
DQ

7
6
5
4
3

DQ
DQ
DQ
DQ
DQ

DQ
DQ
DQ

28 - 600 PDIP

0

1

2

3

4

5

6

7

INPUT BUFFERS

COLUMN I/O

COLUMN DECODER

AA A

01

2

STORE/
RECALL

CONTROL

NE

PIN NAMES

A0 - A
W Write Enable
DQ0 - DQ7Data In/Out

G

E
W

E Chip Enable
G Output Enable
NE Nonvolatile Enable
V

CC

V

SS

8

Address Inputs

Power (+5V)
Ground

2-39

STK20C04

ABSOLUTE MAXIMUM RATINGS

Voltage on typical input relative to V
Voltage on DQ

and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V)

0-7

Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W

DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA

. . . . . . . . . . . . . –0.6V to 7.0V

SS

a

Note a: Stresses greater than those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

(One output at a time, one second duration)
DC CHARACTERISTICS (VCC = 5.0V ± 10%)

SYMBOL PARAMETER UNITS NOTES

b

I

CC

I

CC

I

SB

I

SB

I

ILK

I

OLK

V
V
V
V
T

1

2

1

2

IH
IL
OH
OL
A

Average VCC Current 80 85 mA t

d

Average VCC Current 50 50 mA All inputs at

STORE

during

c

Average VCC Current 27 30 mA t
(Standby, Cycling TTL Input Levels) 23 27 mA t

c

Average VCC Current 1 1 mA E ≥ (VCC – 0.2V)
(Standby, Stable CMOS Input Levels) all others V
Input Leakage Current (Any Input) ±1 ±1 µAVCC = max

Off State Output Leakage Current ±5 ±5 µAVCC = max

Input Logic "1" Voltage 2.2 VCC+.5 2.2 VCC+.5 V All Inputs
Input Logic "0" Voltage VSS–.5 0.8 VSS–.5 0.8 V All Inputs
Output Logic "1" Voltage 2.4 2.4 V I
Output Logic "0" Voltage 0.4 0.4 V I
Operating Temperature 0 70 –40 85 °C

cycle VIN ≤ 0.2V or ≥ (VCC – 0.2V)

COMMERCIAL INDUSTRIAL

MIN MAX MIN MAX

75 80 mA t
65 75 mA t

20 23 mA t

= 30ns

AVAV

= 35ns

AVAV

= 45ns

AVAV

= 30ns

AVAV

= 35ns

AVAV

= 45ns

AVAV

; all others cycling

E ≥ V

IH

= VSS to V

V

IN

= VSS to V

V

IN

= –4mA

OUT

= 8mA

OUT

≤ 0.2V or ≥ (VCC – 0.2V)

IN

CC

CC

Note b: ICC is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: I

1

is the average current required for the duration of the store cycle (t

CC

2

) after the sequence (tWC) that initiates the cycle.

STORE

AC TEST CONDITIONS

Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V

Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V

Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

CAPACITANCE (T

SYMBOL PARAMETER MAX UNITS CONDITIONS

C

IN

C

OUT

Note e: These parameters are guaranteed but not tested.

Input Capacitance 7 pF ∆V = 0 to 3V
Output Capacitance & W 7 pF ∆V = 0 to 3V

=25°C, f=1.0MHz)

A

e

Output

255 Ohms

Figure 1: AC Output Loading

5.0V

480 Ohms

INCLUDING

AND FIXTURE

30pF

SCOPE

2-40

STK20C04

READ CYCLES #1 & #2

(VCC = 5.0V ± 10%)

SYMBOLS STK20C04-30 STK20C04-35 STK20C04-45

NO. PARAMETER UNITS

1t
2t
3t
4t
5t
6t
7t
8t

9t
10 t
11 t

11A t

#1, #2 Alt. MIN MAX MIN MAX MIN MAX

t

ELQV

AVAVR

AVQV

GLQV

AXQX

ELQX

EHQZ

GLQX

GHQZ

ELICCH

EHICCL

WHQV

g

h

i

i

e

c,e

Chip Enable Access Time 30 35 45 ns

ACS

t

Read Cycle Time 30 35 45 ns

RC

t

Address Access Time 30 35 45 ns

AA

t

Output Enable to Data Valid 15 20 25 ns

OE

t

Output Hold After Address Change 5 5 5 ns

OH

t

Chip Enable to Output Active 5 5 5 ns

LZ

t

Chip Disable to Output Inactive 18 20 25 ns

HZ

t

Output Enable to Output Active 0 0 0 ns

OLZ

t

Output Disable to Output Inactive 18 20 25 ns

OHZ

t

Chip Enable to Power Active 0 0 0 ns

PA

t

Chip Disable to Power Standby 25 25 25 ns

PS

t

Write Recovery Time 35 45 55 ns

WR

Note c: Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note f: NE must be high during entire cycle.
Note g: For READ CYCLE #1 and #2, W and NE must be high for entire cycle.
Note h: Device is continuously selected with E low and G low.
Note i: Measured ± 200mV from steady state output voltage.

f,g,h

READ CYCLE #1

2

t

AVAVR

ADDRESS

3

t

AVQV

DATA VALID

DQ (Data Out)

t

AXQX

5

W

READ CYCLE #2

ADDRESS

E

G

DQ (Data Out)

I

CC

W

ACTIVE
STANDBY

f,g

10

t

ELICCH

11A

t

WHQV

t

6

ELQX

11A

t

WHQV

t

GLQX

8

t

ELQV

t

GLQV

t

AVAVR

1

4

2-41

2

11

t

EHICCL

7

t

EHQZ

9

t

GHQZ

DATA VALID