查询STK17TA8供应商查询STK17TA8供应商
STK17TA8
nvTime™ Event Data Recorder
128K x 8 AutoStore™nvSRAM
with Real-Time Clock
Product Preview
FEATURES
• Data Integrity of Simtek nvSRAM Combined
with Full-Featured Real-Time Clock
• 25ns, 35ns and 45ns Access Times
• Software or AutoStore™STORE to Quan-
tumTrap™ Nonvolatile Elements
• RECALL to SRAM Initiated by Software or
Power Restore
• Unlimited READ, WRITE and RECALL Cycles
• 100-Year Data Retention
• Watchdog Timer
• Clock Alarm with programmable Interrupts
• Capacitor or battery backup for RTC
• Single 3V +20%, -10% Operation
• Commercial and Industrial Temperatures
• Packages: 48 pin SSOP, 40 pin DIP
BLOCK DIAGRAM
Quantum Trap
1024 x 1024
ARRAY
10 A11
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
0
1
2
3
4
5
6
7
STATIC RAM
1024 x 1024
ROW DECODER
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A
INPUT BUFFERS
DESCRIPTION
The Simtek STK17TA8 combines a 1 Mbit nonvolatile static RAM with a full-featured real-time clock in
a reliable, monolithic integrated circuit. The embedded nonvolatile elements incorporate Simtek’s
QuantumTrap™ technology producing the world’s
V
V
rtcbat
rtccap
16
SRAM can be
most reliable nonvolatile memory. The
read and written an unlimited number of times, while
independent, nonvolatile data resides in the nonvolatile elements.
The Real-Time Clock function provides an accurate
clock with leap year tracking and a programmable,
high accuracy oscillator. The Alarm function is programmable for one-time alarms or periodic seconds,
minutes, hours, or days. There is also a programmable Watchdog Timer for process control.
STORE
RECALL
HSB
STORE/
RECALL
CONTROL
RTC
MUX
V
CCXVCAP
POWER
CONTROL
SOFTWARE
DETECT
A0 A
16
A0 - A
X
1
X
2
INT
G
E
W
February 2004 1 Document Control # ML0023 rev 0.3
STK17TA8
PACKAGES
48 Pin 300 mil SSOP
(not to scale)
40 Pin 600 mil DIP
PIN DESCRIPTIONS
Pin Name I/O Description
A0 - A
16
-DQ
DQ
0
7
E
W
G
, X
X
1
2
V
rtccap
V
rtcbat
V
CCX
HSB
INT Output Interrupt Output: Can be programmed to respond to the clock alarm,
V
CAP
V
SS
Input Address: The 17 address inputs select one of 131,072 bytes in the
nvSRAM array or one of 16 bytes in the clock register map.
I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM array and
clock.
Input Chip Enable: The active low E input selects the device.
Input Write Enable: The active low W enables data on the DQ pins to be
written to the adddress location latched by the falling edge of E.
Input Output Enable: The active low G input enables the data output buffers
during read cycles. Deasserting G high causes the DQ pins to tri-state.
Input Crystal: Connections for 32.768 kHz crystal.
Power Supply Capacitor supplied backup RTC supply voltage.
Power Supply Battery supplied backup RTC supply voltage.
Power Supply Power (+ 3V)
I/O Hardware Store Busy (I/O)
the watchdog timer and the power monitor. Programmable to either
active high (push/pull) or active low (open-drain).
Power Supply Autostore Capacitor: Supplies power to nvSRAM during power loss to
store data from SRAM to nonvolatile elements.
Power Supply Ground
February 2004 2 Document Control # ML0023 rev 0.3
STK17TA8
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . .–0.5V to +3.9V
Voltage on Input Relative to V
Voltage on DQ
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
0-7
. . . . . . . . . . –0.5V to (VCC + 0.5V)
SS
a
Note a: Stresses greater than those listed under “Absolute Maximum
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
DC CHARACTERISTICS(VCC = 3.0V +20%, -10%)
SYMBOL PARAMETER
b
I
I
I
I
I
I
I
I
V
V
V
V
V
T
Note b: I
Note c: I
Note d: E
Note e: V
Average VCC Current 70
CC
1
c
Average VCC Current during STORE 1 1 mA All Inputs Don’t Care, VCC = max
CC
2
b
Average V
CC
3
3V, 25°C, Typical
c
Average V
CC
4
AutoStore™ Cycle
d
V
SB
ILK
OLK
BAK
BAK
IH
IL
OH
OL
A
CC
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
RTC Backup Current 200 300 nA
RTC Backup Voltage 1.6 1.6 V
Input Logic “1” Voltage 2 .0 VCC + .3 2.0 VCC + .3 V All Inputs
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 – 40 85 °C
and I
CC
1
and I
CC
2
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
reference levels throughout this datasheet refer to V
CC
Current at t
CC
Current during
CAP
Standby Current
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
are the average currents required for the duration of the respective STORE cycles (t
CC
4
AVAV
= 200ns
COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX
60
55
55mA
0.5 0.5 mA
0.3 0.3 mA
±1 ±1 µA
±1 ±1 µA
.
CCX
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCE
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
Input Capacitance 5 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V
f
(TA = 25°C, f = 1.0MHz)
Note f: These parameters are guaranteed but not tested.
OUTPUT
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
e
UNITS NOTES
75
65
60
mA
t
= 25ns
mA
mA
AVAV
t
= 35ns
AVAV
t
= 45ns
AVAV
W ≥ (V
– 0.2V)
CC
All Others Cycling, CMOS Levels
All Inputs Don’t Care
E ≥ (VCC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
V
= max
CC
STORE
VIN = VSS to V
V
CC
V
IN
OUT
OUT
).
CC
= max
= VSS to VCC, E or G ≥ VIH
= – 2mA
= 4mA
3.0V
577 Ohms
789 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
February 2004 3 Document Control # ML0023 rev 0.3
STK17TA8
SRAM READ CYCLES #1 & #2 (VCC = 3.0V +20%, -10%)
NO.
1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
Note g: W must be high during SRAM READ cycles.
Note h: Device is continuously selected with E
SYMBOLS
#1, #2 Alt. MINMAXMINMAXMINMAX
ELQV
AVAV
AVQ V
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
t
g
t
h
t
t
h
t
t
i
t
t
i
t
f
t
f
t
Chip Enable Access Time 25 35 45 ns
ACS
Read Cycle Time 25 35 45 ns
RC
Address Access Time 25 35 45 ns
AA
Output Enable to Data Valid 10 15 20 ns
OE
Output Hold after Address Change 3 3 3 ns
OH
Chip Enable to Output Active 3 3 3 ns
LZ
Chip Disable to Output Inactive 10 13 15 ns
HZ
Output Enable to Output Active 0 0 0 ns
OLZ
Output Disable to Output Inactive 10 13 15 ns
OHZ
Chip Enable to Power Active 0 0 0 ns
PA
Chip Disable to Power Standby 25 35 45 ns
PS
PARAMETER
and G both low.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg,
2
t
t
AVQ V
AVAV
3
ADDRESS
DQ (DATA OUT)
t
AXQX
5
h
STK17TA8-25 STK17TA8-35 STK17TA8-45
DATA VALID
UNITS
e
t
GLQV
g
2
t
AVAV
1
t
ELQV
4
ACTIVE
t
DATA VALID
9
GHQZ
t
EHQZ
t
7
11
EHICCL
SRAM READ CYCLE #2: E Controlled
ADDRESS
STANDBY
t
ELQX
10
t
ELICCH
6
t
GLQX
8
DQ (DATA OUT)
I
E
G
CC
February 2004 4 Document Control # ML0023 rev 0.3
STK17TA8
SRAM WRITE CYCLES #1 & #2 (VCC = 3.0V +20%, -10%)
NO.
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E
Note l: HSB
SRAM WRITE CYCLE #1: W Controlled
ADDRESS
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX
AVAV
WLWH
ELWH
DVWH
WHDX
AVW H
AVW L
WHAX
WLQZ
WHQX
or W must be ≥ V
must be high during SRAM write cycles.
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVE H
t
AVE L
t
EHAX
i, j
t
Write Cycle Time 25 35 45 ns
WC
t
Write Pulse Width 20 25 30 ns
WP
t
Chip Enable to End of Write 20 25 30 ns
CW
t
Data Set-up to End of Write 10 12 15 ns
DW
t
Data Hold after End of Write 0 0 0 ns
DH
t
Address Set-up to End of Write 20 25 30 ns
AW
tASAddress Set-up to Start of Write 0 0 0 ns
t
Address Hold after End of Write 0 0 0 ns
WR
t
Write Enable to Output Disable 10 13 15 ns
WZ
t
Output Active after End of Write 3 3 3 ns
OW
during address transitions.
IH
PARAMETER
k, l
12
t
AVAV
14
t
ELWH
E
STK17TA8-25 STK17TA8-35 STK17TA8-45
19
t
WHAX
UNITS
e
17
t
DATA IN
DATA IN
DATA OUT
18
t
AVWL
W
PREVIOUS DATA
20
t
WLQZ
AVW H
13
t
WLWH
SRAM WRITE CYCLE #2: E Controlled
ADDRESS
E
W
DATA IN
DATA OUT
18
t
AVEL
t
AVE H
17
k, l
12
t
AVAV
14
t
ELEH
13
t
WLEH
HIGH IMPEDANCE
15
t
DVWH
DATA VALID
HIGH IMPEDANCE
15
t
DVEH
DATA VALID
t
WHDX
t
16
19
t
EHAX
16
EHDX
t
WHQX
21
February 2004 5 Document Control # ML0023 rev 0.3
STK17TA8
MODE SELECTION
E W G A15 - A0 (hex) MODE I/O POWER NOTES
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
4E38
B1C7
LHL
LHL
LHL
LHL
Note m: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note n: While there are 17 addresses on the STK17TA8, only the lower 16 are used to control software modes.
Note o: I/O state depends on the state of G
83E0
7C1F
703F
8B45
4E38
B1C7
83E0
7C1F
703F
4B46
4E38
B1C7
83E0
7C1F
703F
8FC0
4E38
B1C7
83E0
7C1F
703F
4C63
. The I/O table shown assumes G low.
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore Inhibit
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore inhibit off
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
Active
Active
l
CC
Active
m, n, o
m, n, o
m, n, o
2
m, n, o
February 2004 6 Document Control # ML0023 rev 0.3
STK17TA8
AutoStore™/POWER-UP RECALL (VCC = 3.0V +20%, -10%)
NO.
22 t
23 t
24 V
Note p: t
RESTORE
Note q: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
SYMBOLS
Standard Alternate MIN MAX
RESTORE
STORE
SWITCH
t
HLHZ
starts from the time VCC rises above V
Power-up RECALL Duration 5 ms p
STORE Cycle Duration 10 ms q
Low Voltage Trigger Level 2.55 2.65 V
SWITCH
PARAMETER
.
STK17TA8
UNITS NOTES
AutoStore™/POWER-UP RECALL
V
CC
24
V
SWITCH
AutoStore™
POWER-UP RECALL
22
t
RESTORE
t
STORE
23
e
W
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
NO STORE
BROWN OUT
AutoStore™
BROWN OUT
AutoStore™
(NO SRAM WRITES)
RECALL WHEN
V
RETURNS
CC
ABOVE V
SWITCH
February 2004 7 Document Control # ML0023 rev 0.3
STK17TA8
SOFTWARE-CONTROLLED STORE/RECALL CYCLE
NO.
25 t
26 t
27 t
28 t
29 t
Note r: The software sequence is clocked with E controlled READs or G controlled READs.
Note s: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (4E38, B1C7, 83E0, 7C1F, 703F, 8FC0) for a
SYMBOLS
E cont G cont Alternate MIN MAX MIN MAX MIN MAX
AVAV
AVE L
ELEH
ELAX
RECALLtRECALL
t
AVAV
t
AVG L
t
GLGH
t
GLAX
t
t
t
STORE/RECALL Initiation Cycle Time 25 35 45 ns s
RC
Address Set-up Time 0 0 0 ns
AS
Clock Pulse Width 20 25 30 ns
CW
Address Hold Time 20 20 20 ns
RECALL Duration 20 20 20 µs
PARAMETER
STORE cycle or (4E38, B1C7, 83E0, 7C1F, 703F, 4C63) for a RECALL cycle. W
SOFTWARE STORE/RECALL CYCLE: E CONTROLLED
25
t
ADDRESS
t
AVEL
AVAV
26
t
ELEH
27
ADDRESS #6ADDRESS #1
s
(VCC = 3.0V +20%, -10%)
STK17TA8-25 STK17TA8-35 STK17TA8-45
must be high during all six consecutive cycles.
s
25
t
AVAV
UNITS NOTES
E
28
t
G
DQ (DATA)
ELAX
DATA VALID
DATA VALID
DATA VALID
23 29
t
/ t
STORE
HIGH IMPEDANCE
RECALL
e
t
25
AVAV
s
SOFTWARE STORE/RECALL CYCLE: G CONTROLLED
25
t
ADDRESS
AVAV
ADDRESS #6ADDRESS #1
E
t
AVG L
26
t
GLGH
27
G
23 29
t
/ t
STORE
RECALL
HIGH IMPEDANCE
DQ (DATA)
28
t
GLAX
DATA VALID
DATA VALID
DATA VALID
February 2004 8 Document Control # ML0023 rev 0.3
STK17TA8
HARDWARE STORE CYCLE
NO.
30 t
31 t
32 t
33 t
34 t
Note t: t
RECOVER
SYMBOLS
Standard Alternate MIN MAX
STORE
DELAY
RECOVER
HLHX
HLBL
t
HLHZ
t
HLQZ
t
HHQX
is only applicable after t
STORE Cycle Duration 10 ms i
Time Allowed to Complete SRAM Cycle 1 µsi
Hardware STORE High to Inhibit Off 100 ns t
Hardware STORE Pulse Width 15 ns
Hardware STORE Low to STORE Busy 300 ns
STORE
HARDWARE STORE CYCLE
33
t
HSB (IN)
HSB (OUT)
DQ (DATA OUT)
HIGH IMPEDANCE
HLHX
DATA VALID
t
(VCC = 3.0V +20%, -10%)
PARAMETER
is complete.
30
t
STORE
34
t
HLBL
31
t
DELAY
e
32
t
RECOVER
STK17TA8
UNITS NOTES
HIGH IMPEDANCE
DATA VALID
February 2004 9 Document Control # ML0023 rev 0.3
STK17TA8
DEVICE OPERATION
nvSRAM
The STK17TA8 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
RAM. In nonvolatile mode, data is transferred
static
from SRAM to the nonvolatile elements (the STORE
operation) or from the nonvolatile elements to SRAM
(the RECALL operation). In this mode SRAM functions are disabled. The STK17TA8 supports unlimited reads and writes to the SRAM, unlimited recalls
from the nonvolatile elements and up to 1 million
stores to the nonvolatile elements
SRAM READ
The STK17TA8 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A
bytes will be accessed. When the
determines which of the 131,072 data
0-16
READ is initiated
by an address transition, the outputs will be valid
after a delay of t
initiated by E
at t
, whichever is later (READ cycle #2). The data
GLQV
(READ cycle #1). If the READ is
AVQV
or G, the outputs will be valid at t
ELQV
or
outputs will repeatedly respond to address changes
within the t
access time without the need for tran-
AVQ V
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high, or W
is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the
WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W controlled WRITE or t
controlled WRITE.
E
It is recommended that G
WRITE cycle to avoid data bus contention on
entire
common I/O lines. If G
is left low, internal circuitry
will turn off the output buffers t
before the end of an
DVEH
be kept high during the
WLQZ
will be writ-
0-7
before the end
DVWH
after W goes low.
AutoStore™ OPERATION
The STK17TA8 can be powered in one of three
modes.
During normal operation, the STK17TA8 will draw
current from V
the V
pin. This stored charge will be used by the
CAP
chip to perform a single
power up, when the voltage on the V
below V
the V
SWITCH
pin from V
CAP
to charge a capacitor connected to
CCX
STORE operation. After
pin drops
CCX
, the part will automatically disconnect
and initiate a STORE opera-
CCX
tion.
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 10µF and
100µF (± 20%) rated at minimum of 5V should be
provided.
In order to prevent unneeded
STORE operations,
automatic STOREs as well as those initiated by
externally driving HSB low, will be ignored unless at
least one
WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of
whether a
WRITE operation has taken place. HSB
can be used to signal the system that the
AutoStore™ cycle is in progress.
10k
Ω∗
Vccx
Vcap
+
F
µ
10
5v, ±20%
Figure 2: AutoStore™ Mode
If HSB is not used it should be left unconnected
W
Vss
Ω
10k
F
µ
0.1
Bypass
HSB OPERATION
The STK17TA8 provides the HSB pin for controlling
and acknowledging the
pin can be used to request a hardware STORE cycle.
When the HSB
pin is driven low, the STK17TA8 will
conditionally initiate a
an actual STORE cycle will only begin if a WRITE to
SRAM took place since the last STORE or
the
STORE operations. The HSB
STORE operation after t
DELAY
;
February 2004 10 Document Control # ML0023 rev 0.3
STK17TA8
RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a
busy condition while the
STORE (initiated by any
means) is in progress.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the
STORE operation
is initiated. After HSB goes low, the STK17TA8 will
continue SRAM operations for t
multiple
WRITE is in progress when HSB is pulled low it will
be allowed a time, t
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB
The HSB
SRAM READ operations may take place. If a
, to complete. However, any
DELAY
returns high.
pin can be used to synchronize one
. During t
DELAY
DELAY
STK17TA8 with one or more STK14CA8 nvSRAMs
to expand the memory space. To operate in this
mode the HSB
pins from each device should be
connected together. An external pull-up resistor to +
3.0V is required since HSB acts as an open drain
pull down. The V
pins from the other parts can be
CAP
tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
devices detects a power loss and asserts HSB
, the
common HSB pin will cause all parts to request a
STORE cycle (a STORE will take place in those
devices that have been written since the last nonvolatile cycle).
During any STORE operation, regardless of how it
was initiated, the STK17TA8 will continue to drive
the HSB
pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation
the STK17TA8 will remain disabled until the HSB
pin
returns high.
If HSB is not used, it should be left unconnected.
POWER-UP RECALL
During power up, or after any low-power condition
< V
(V
CCX
latched. When V
voltage of V
be initiated and will take t
If the STK17TA8 is in a WRITE state at the end of
power-up RECALL, the WRITE will be inhibited and E
or W must be brought high and then low for a write
to initiate.
), an internal RECALL request will be
SWITCH
SWITCH
once again exceeds the sense
CAP
, a RECALL cycle will automatically
to complete.
RESTORE
SOFTWARE NONVOLATILE STORE
The STK17TA8 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
six specific address locations. During the
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile elements. The program operation copies the
SRAM data into nonvolatile memory. Once a STORE
,
cycle is initiated, further input and output are disabled until the cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be
aborted and no
STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address 4E38 (hex) Valid READ
2. Read address B1C7 (hex) Valid READ
3. Read address 83E0 (hex) Valid READ
4. Read address 7C1F (hex) Valid READ
5. Read address 703F (hex) Valid READ
6. Read address 8FC0 (hex) Initiate STORE cycle
The software sequence may be clocked with E controlled READs or G controlled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not
WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the t
been fulfilled, the
READ and WRITE operation.
SRAM will again be activated for
cycle time has
STORE
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
STORE initiation. To initiate the RECALL cycle,
ware
the following sequence of
tions must be performed:
1. Read address 4E38 (hex) Valid READ
2. Read address B1C7 (hex) Valid READ
3. Read address 83E0 (hex) Valid READ
4. Read address 7C1F (hex) Valid READ
5. Read address 703F (hex) Valid READ
6. Read address 4C63 (hex) Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
E controlled READ opera-
STORE
February 2004 11 Document Control # ML0023 rev 0.3
STK17TA8
information is transferred into the SRAM cells. After
the t
ready for
operation in no way alters the data in the nonvolatile
elements.
PREVENTING STORES
The AutoStore™ function can be disabled by initiating an AutoStore Inhibit sequence. A sequence of
read operations is performed in a manner similar to
the software STORE initiation. To initiate the
AutoStore Inihibit sequence, the following sequence
of E
cycle time the SRAM will once again be
RECALL
READ and WRITE operations. The RECALL
controlled read operations must be performed:
1. Read address 4E38 (hex) Valid READ
2. Read address B1C7 (hex) Valid READ
3. Read address 83E0 (hex) Valid READ
4. Read address 7C1F (hex) Valid READ
5. Read address 703F (hex) Valid READ
6. Read address 8B45 (hex) AutoStore Inhibit
s will be inhibited.
WRITE
LOW AVERAGE ACTIVE POWER
The STK17TA8 draws significantly less current
when it is cycled at times longer than 50ns. Figure 3
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
commercial temperature range, V
= 3.6V, and
CC
100% duty cycle on chip enable. Figure 4 shows the
same relationship for
WRITE cycles. If the chip
enable duty cycle is less than 100%, only standby
current is drawn when the chip is disabled. The
overall average current drawn by the STK17TA8
depends on the following items: 1) the duty cycle of
chip enable; 2) the overall cycle rate for accesses;
3) the ratio of
temperature; 5) the V
50
READs to WRITEs; 4) the operating
level; and 6) I/O loading.
cc
The AutoStore Inhibit can be disabled by initiating
an AutoStore Inhibit Off sequence. A sequence of
read operations is performed in a manner similar to
the software RECALL initiation. To initiate the
AutoStore Inhibit Off sequence, the following
sequence of E controlled read operations must be
performed:
1. Read address 4E38 (hex) Valid READ
2. Read address B1C7 (hex) Valid READ
3. Read address 83E0 (hex) Valid READ
4. Read address 7C1F (hex) Valid READ
5. Read address 703F (hex) Valid READ
6. Read address 4B46 (hex) AutoStore Inhibit Off
The last AutoStore Inhibit state is stored in nonvola-
tile memory and is retained through power cycling.
NOISE CONSIDERATIONS
The STK17TA8 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between V
, using leads and traces that are as short as pos-
V
SS
sible. As with all high-speed
CMOS ICs, normal care-
CAP
and
ful routing of power, ground and signals will help
prevent noise problems.
HARDWARE WRITE PROTECT
The STK17TA8 offers hardware protection against
inadvertent
ing low-voltage conditions. When V
externally initiated STORE operations and SRAM
STORE operation and SRAM WRITEs dur-
CCX
< V
SWITCH
, all
40
30
20
10
Average Active Current (mA)
0
50 100 150 200
Cycle Time (ns)
Figure 3: Icc (max) Reads
50
40
30
20
10
Average Active Current (mA)
0
50 100 150 200
Cycle Time (ns)
Figure 4: I
(max) Writes
cc
February 2004 12 Document Control # ML0023 rev 0.3
STK17TA8
nvTIME OPERATION
The STK17TA8 offers internal registers that contain
Clock, Alarm, Watchdog, Interrupt, and Control functions. Internal double buffering of the clock and the
clock/timer information registers prevents accessing
transitional internal clock data during a read or write
operation. Double buffering also circumvents disrupting normal timing counts or clock accuracy of
the internal clock while accessing clock data. Clock
and Alarm Registers store data in BCD format.
CLOCK OPERATIONS
The clock registers maintain time up to 9,999 years
in one second increments. The user can set the time
to any calendar time and the clock automatically
keeps track of days of the week and month, leap
years and century transitions. There are eight registers dedicated to the clock functions which are used
to set time with a write cycle and to read time during
a read cycle. These registers contain the Time of
Day in BCD format. Bits defined as “X” are currently
not used and are reserved for future use by Simtek.
READING THE CLOCK
While the double-buffered RTC register structure
reduces the chance of reading incorrect data from the
clock, the user should halt internal updates to the
STK17TA8 clock registers before reading clock data
to prevent the reading of data in transition. Stopping
the internal register updates does not affect clock
accuracy.
The updating process is stopped by writing a “1” to
the read bit (in the control register 1FFF0h), and will
not restart until a “0” is written to the read bit. The
RTC registers can then be read while the internal
clock continues to run.
Within 10 msec after a “0” is written to the read bit,
all STK17TA8 registers are simultaneously updated.
SETTING THE CLOCK
Setting the write bit (in the control register 1FFF0h)
to a “1” halts updates to the STK17TA8 registers.
The correct day, date and time can then be written
into the registers in 24-hour
the write bit to “0” transfers those values to the
actual clock counters, after which the clock resumes
normal operation.
BCD format. Resetting
BACKUP POWER
The STK17TA8 is intended for permanently powered operation, but when primary power, Vcc, fails
and drops below Vswitch the device will switch to
backup power from either Vbakcap or Vbakbat,
depending on whether a capacitor or battery is chosen for the application.
The clock oscillator uses very little current, which
maximizes the backup time available from the
backup source. Regardless of clock operation with
the primary source removed, the data stored in
vSRAM is secure, having been stored in the nonvolatile elements as power was lost. Factors to be considered when choosing a backup power source
include: the expected duration of power outages and
the cost tradeoff of using a battery versus a capacitor.
During backup operation the STK17TA8 consumes
a maximum of 300 nanoamps at 2 volts. Capacitor
or battery values should be chosen according to the
application. Backup time values based on maximum
current specs are shown below. Nominal times are
approximately 3 times longer.
Capacitor Value Backup Time
0.1 F 72 hours
0.47 F 14 days
1.0 F 30 days
Using a capacitor has the obvious advantage of
recharging the backup source each time the system
is powered up.
If a battery is used a 3V lithium is recommended and
the STK17TA8 will only source current from the battery when the primary power is removed. The battery will not, however, be recharged at any time by
the STK17TA8. The battery capacity should be chosen for total anticipated cumulative down-time
required over the life of the system.
STOPPING AND STARTING THE OSCILLATOR
The oscillator may be stopped at any time. This feature may be used to save battery or capacitor
energy during long-term storage to increase shelf
life. Setting the OSCEN
halts the oscillator. Setting the bit to 0 enables the
oscillator. The RTC does not run until the oscillator
bit in register 1FFF8h to 1
February 2004 13 Document Control # ML0023 rev 0.3
STK17TA8
is enabled.
CALIBRATING THE CLOCK
The RTC is driven by a quartz controlled oscillator
with a nominal frequency of 32.768 KHz. Clock
accuracy will depend on the quality of the crystal,
usually specified to 35 ppm limits at 25°C. This error
could equate to +
STK17TA8 employs a calibration circuit that can
improve the accuracy to + 1/-2 ppm at 25°C. The
calibration circuit adds or subtracts counts from the
oscillator divider circuit.
The number of times pulses are suppressed (subtracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into the
five calibration bits found in control register 1FFF8h.
Adding counts speeds the clock up; subtracting
counts slows the clock down. The Calibration bits
occupy the the five lower order bits in the control
register 8. These bits can be set to represent any
value between 0 and 31 in binary form. Bit D5 is a
Sign bit, where a “1” indicates positive calibration
and a “0” indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second
either shortened by 128 or lengthened by 256 oscillator cycles.
If a binary “1” is loaded into the register, only the first
2 minutes of the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected, and
so on. Therefore each calibration step has the effect
of adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles. That is
+4.068 or -2.034 ppm of adjustment per calibration
step in the calibration register.
In order to determine how to set the calibration one
may set the CAL bit in register 1FFF0h to 1, which
causes the INT pin to toggle at a nominal 512 Hz.
Any deviation measured from the 512 Hz will indicate the degree and direction of the required correction. For example, a reading of 512.010124 Hz
would indicate a +20 ppm error, requiring a -10
(001010) to be loaded into the Calibration register.
Note that setting or changing the calibration register
does not affect the frequency test output frequency.
1.53 minutes per month. The
ALARM
The alarm function compares user-programmed val-
ues to the corresponding time-of-day values. When
a match occurs, the alarm event occurs. The alarm
drives an internal flag, AF, and may drive the INT pin
if desired.
There are four alarm match fields. They are date,
hours, minutes and seconds. Each of these fields
also has a Match bit that is used to determine if the
field is used in the alarm match logic. Setting the
Match bit to “0” indicates that the corresponding field
will be used in the match process.
Depending on the Match bits, the alarm can occur
as specifically as one particular second on one day
of the month, or as frequently as once per second
continuously. The MSB of each alarm register is a
Match bit. Selecting none of the Match bits (all 1’s)
indicates that no match is required. The alarm
occurs every second. Setting the match select bit for
seconds to “0” causes the logic to match the seconds alarm value to the current time of day. Since a
match will occur for only one value per minute, the
alarm occurs once per minute. Likewise, setting the
seconds and minutes Match bits causes an exact
match of these values. Thus, an alarm will occur
once per hour. Setting seconds, minutes and hours
causes a match once per day. Lastly, selecting all
match values causes an exact time and date match.
Selecting other bit combinations will not produce
meaningful results, however the alarm circuit should
follow the functions described.
There are two ways a user can detect an alarm
event, by reading the AF flag or monitoring the INT
pin. The AF flag in the register 1FFF0h will indicate
that a date/time match has occurred. The AF bit will
be set to 1 when a match occurs. Reading the
Flags/Control register clears the alarm flag bit (and
all others). A hardware interrupt pin may also be
used to detect an alarm event.
WATCHDOG TIMER
The watchdog timer is a free running down counter
that uses the 32 Hz clock (31.25 ms) derived from
the crystal oscillator. The oscillator must be running
for the watchdog to function. It begins counting
down from the value loaded in the Watchdog Timer
register.
The counter consists of a loadable register and a
free running counter. On power up, the watchdog
timeout value in register 1FFF7h is loaded into the
February 2004 14 Document Control # ML0023 rev 0.3
STK17TA8
counter load register. Counting begins on power up
and restarts from the loadable value any time the
Watchdog Strobe (WDS) bit is set to 1. The counter
is compared to the terminal value of 0. If the counter
reaches this value, it causes an internal flag and an
optional interrupt output. The user can prevent the
timeout interrupt by setting WDS bit to 1 prior to the
counter reaching 0. This causes the counter to be
reloaded with the watchdog timeout value and to be
restarted. As long as the user sets the WDS bit prior
to the counter reaching the terminal value, the interrupt and flag never occurs.
New timeout values can be written by setting the
watchdog write bit to 0. When the WDW
the previous operation), new writes to the watchdog
timeout value bits D5-D0 allow the timeout value to
be modified. When WDW
D5-D0 will be ignored. The WDW function allows a
user to set the WDS bit without concern that the
watchdog timer value will be modified. A logical diagram of the watchdog timer is shown below. Note
that setting the watchdog timeout value to 0 would
be otherwise meaningless and therefore disables
the watchdog function.
The output of the watchdog timer is a flag bit WDF
that is set if the watchdog is allowed to timeout. The
flag is set upon a watchdog timeout and cleared
when the Flags/Control register is read by the user.
The user can also enable an optional interrupt
source to drive the INT pin if the watchdog timeout
occurs.
is a 1, then writes to bits
is 0 (from
POWER MONITOR
The STK17TA8 provides a power management
scheme with power-fail interrupt capability. It also
controls the internal switch to backup power for the
clock and protects the memory from low-Vcc
access. The power monitor is based on an internal
band-gap reference circuit that compares the Vcc
voltage to various thresholds.
As descibed in the AutoStore™ section previously,
when Vswitch is reached as Vcc decays from power
loss, a data store operation is initiated from SRAM
to the nonvolatile elements, securing the last SRAM
data state. Power is also switched from Vccx to the
backup supply (battery or capacitor) to operate the
RTC oscillator.
When operating from the backup source no data
may be read or written and the clock functions are
not available to the user. The clock continues to
operate in the background. Updated clock data is
available to the user 10 msec after Vcc has been
restored to the device.
INTERRUPTS
The STK17TA8 provides three potential interrupt
sources. They include the watchdog timer, the
power monitor, and the clock/calendar alarm. Each
can be individually enabled and assigned to drive
the INT pin. In addition, each has an associated flag
bit that the host processor can use to determine the
cause of the interrupt.
Some of the sources have additional control bits that
determine functional behavior. In addition, the pin
driver has three bits that specify its behavior when
an interrupt occurs. A functional diagram of the
interrupt logic is shown below.
Figure 6. Interrupt Block Diagram
The three interrupts each have a source and an
Figure 5. Watchdog Timer Block Diagram
enable. Both the source and the enable must be
active (true high) in order to generate an interrupt
February 2004 15 Document Control # ML0023 rev 0.3
STK17TA8
output. Only one source is necessary to drive the
pin. The user can identify the source by reading the
Flags/Control register, which contains the flags
associated with each source. All flags are cleared to
0 when the register is read. The cycle must be a
complete read cycle (WE
will not be cleared. The power monitor has two programmable settings that are explained in the power
monitor section.
Once an interrupt source is active, the pin driver
determines the behavior of the output. It has two
programmable settings as shown below. Pin driver
control bits are located in the Interrupts register.
According to the programming selections, the pin
can be driven in the backup mode for an alarm interrupt. In addition, the pin can be an active low (opendrain) or an active high (push-pull) driver. If programmed for operation during backup mode, it can
only be active low. Lastly, the pin can provide a oneshot function so that the active condition is a pulse
or a level condition. In one-shot mode, the pulse
width is internally fixed at approximately 200 ms.
This mode is intended to reset a host microcontroller. In level mode, the pin goes to its active polarity
until the Flags/Control register is read by the user.
This mode is intended to be used as an interrupt to
a host microcontroller. The control bits are summarized as follows:
Watchdog Interrupt Enable - WIE. When set to 1,
the watchdog timer drives the INT pin as well as an
internal flag when a watchdog timeout occurs.
WhenWIE is set to 0, the watchdog timer affects
only the internal flag.
Alarm Interrupt Enable - AIE. When set to 1, the
alarm match drives the INT pin as well as an internal
fla. When set to 0, the alarm match only affects to
internal flag.
Power Fail Interrupt Enable - PFE. When set to 1,
the power fail monitor drives the pin as well as an
internal flag. When set to 0, the power fail monitor
affects only the internal flag.
Alarm Battery-backup Enable - ABE. When set to 1,
the clock alarm interrupt (as controlled by AIE) will
function even in battery backup mode. When set to
0, the alarm will occur only when Vcc>Vswitch. AIE
should only be set when the INT pin is programmed
for active low operation. In addition, it only functions
high); otherwise the flags
with the clock alarm, not the watchdog. If enabled,
the power monitor will drive the interrupt during all
normal Vcc conditions regardless of the ABE bit.
The application for ABE is intended for power control, where the system powers up at a predetermined time. Depending on the application, it may
require dedicating the INT pin to this function.
High/Low - H/L. When set to a 1, the INT pin is
active high and the driver mode is push-pull. The
INT pin can drive high only when Vcc>Vswitch.
When set to a 0, the INT pin is active low and the
drive mode is open-drain. Active low (open drain) is
operational even in battery backup mode.
Pulse/Level - P/L. When set to a 1 and an interrupt
occurs, the INT pin is driven for approximately 200
ms. When P/L is set to a 0, the INT pin is driven high
or low (determined by H/L) until the Flags/Control
register is read.
When an enabled interrupt source activates the INT
pin, as external host can read the Flags/Control register to determine the cause. Remember that all
flags will be cleared when the register is read. If the
INT pin is programmed for Level mode, then the
condition will clear and the INT pin will return to its
inactive state. If the pin is programmed for Pulse
mode, then reading the flag also will clear the flag
and the pin. The pulse will not complete its specified
duration if the Flags/Control register is read. If the
INT pin is used as a host reset, then the Flags/Control register cannot be read during a reset.
During a power-on reset with no battery, the interrupt register is automatically loaded with the value
24h. This causes power-fail interrupt to be enabled
with an active-low pulse.
February 2004 16 Document Control # ML0023 rev 0.3
RTC Register Map
STK17TA8
Register
D7 D6 D5 D4 D3 D2 D1 D0
1FFFFh 10 Years Years Years: 00 - 99
1FFFEh X X X
1FFFDh X X 10s Day of month Day of Month Day of Month:01 - 31
1FFFCh XXXXX Day of Week Day of Week:01 - 07
1FFFBh X X 10s Hours Hours Hours: 00 - 23
1FFFAh X 10s Minutes Minutes Minutes: 00 - 59
1FFF9h X 10s Seconds Seconds Seconds: 00 - 59
1FFF8h OSCEN
1FFF7h WDS WDW WDT Watchdog*
1FFF6h WIE AIE PFE ABE H/L P/L X X Interrupts*
1FFF5h M X 10s alarm date alarm date Alarm, Day of the Month: 01-31
1FFF4h M X 10s alarm hours alarm hours Alarm, Hours: 00-23
1FFF3h M 10 alarm minutes alarm minutes Alarm, minutes: 00-59
1FFF2h M 10 alarm seconds alarm seconds Alarm, seconds: 00-59
1FFF1h 10s Centuries Centuries Centuries: 00 - 99
1FFF0h WDF AF PF X X CAL W R Flags*
X - resevered for future use
* - not BCD values
X Cal Sign Calibration Calibration values*
BCD DATA
10s
Months
FUNCTION/RANGE
Months Months: 01 - 12
Register Map Detail
1FFFFh
D7 D6 D5 D4 D3 D2 D1 D0
10 Years Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years.
Each nibble operates from 0 to 9. The range for the register is 0-99.
Timekeeping - Years
1FFFEh
1FFFDh
D7 D6 D5 D4 D3 D2 D1 D0
X X X 10s Months Months
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble ( one bit) contains the
upper digit and operates from 0 to 1. The range for the register is 1-12.
D7 D6 D5 D4 D3 D2 D1 D0
X X 10s Day of month Day of Month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the
upper digit and operates from 0 to 3. The range for the register is 1-31.
Timekeeping - Months
Timekeeping - Date
February 2004 17 Document Control # ML0023 rev 0.3
STK17TA8
1FFFCh
1FFFBh
1FFFAh
1FFF9h
D7 D6 D5 D4 D3 D2 D1 D0
XXXXXDay of Week
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1.
The user must assign meanting to the day value, as the day is not integrated with the date.
D7 D6 D5 D4 D3 D2 D1 D0
12/24 X 10s Hours Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits)
contains the upper digit and operates from 0 to 2. The range for the register is 0-23.
D7 D6 D5 D4 D3 D2 D1 D0
X 10s Minutes Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper n ibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59.
D7 D6 D5 D4 D3 D2 D1 D0
X 10s Seconds Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit
and operates from 0 to 5. The range for the register is 0-59.
Timekeeping - Day
Timekeeping - Hours
Timekeeping - Minutes
Timekeeping - Seconds
1FFF8h
OSCEN
Calibration Sign Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base.
Calibration These five bits control the calibration of the clock.
1FFF7h
WDS
WDW
D7 D6 D5 D4 D3 D2 D1 D0
OSCEN
Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the oscillator saves battery/capacitor
power during storage. On a no-battery power-up, this bit is set to 1. The RTC will not run until the oscillator is enabled. Set this bit to 0 to
activate the RTC.
D7 D6 D5 D4 D3 D2 D1 D0
WDS WDW
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is write only. Reading it always will return a 0.
Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT5-WDT0) so it cannot be written. This allows the user
to strobe the watchdg without disturbing the timeout value. Setting this bit to 0 allows bits 5-0 to be witten on the next write to the Watchdog
register. The new value will be loaded on the nex internal watchdog clock after the write cycle is complete. This function is explained in
more detail in the watchdog timer section.
X
Calibration
Sign
Contol/Calibration
Calibration
Watchdog Timer
WDT
February 2004 18 Document Control # ML0023 rev 0.3
STK17TA8
1FFF7h
WDT
1FFF6h
WIE
AIE
PFE
ABE
H/L High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open drain, active low.
P/L
1FFF5h
M
D7 D6 D5 D4 D3 D2 D1 D0
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32 Hz
count (31.25 ms). The minimum range o r timeout value is 31.25 ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3Fh).
Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW
cycle.
D7 D6 D5 D4 D3 D2 D1 D0
WIE AIE PFE ABE H/L
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives the INT pin as well as the WDF flag.
When set to 0, the watchdog timeout affects only the WDF flag.
Alarm Interrup Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When set to 0, the alarm match only
affects the AF flag.
Power-Fail Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When set to 0, the p ower-fail monitor affects
only the PF flag.
Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function even in battery backup mode. When
set to 0, the alarm will occur only when Vcc>Vswitch.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately 200 ms. When set
to a 0, the INT pin is driven to an active level (as set by H/L) until the Flags/Control register is read.
D7 D6 D5 D4 D3 D2 D1 D0
M 0 10s alarm date alarm date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the
date value.
Watchdog Timer
bit was cleared to 0 on a previous
Interrupt Status/Control
P/L XX
Alarm - Day
1FFF4h
M
1FFF3h
M
1FFF2h
D7 D6 D5 D4 D3 D2 D1 D0
M 0 10s alarm hours alarm hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the
hours value.
D7 D6 D5 D4 D3 D2 D1 D0
M 10s alarm minutes alarm minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value
Match. Setting this bit to 0 causes the minutes value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore
the minutes value.
D7 D6 D5 D4 D3 D2 D1 D0
M 10s alarm seconds alarm seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds value
Alarm - Hours
Alarm - Minutes
Alarm - Seconds
February 2004 19 Document Control # ML0023 rev 0.3
STK17TA8
1FFF2h
M
1FFF1h
1FFF0h
WDF
AF
PF
CAL Calibration Mode. When set to 1, the clock enters calibration mode. When set to 0, the clock operates normally.
W
R
D7 D6 D5 D4 D3 D2 D1 D0
Match. Setting this bit to 0 causes the seconds value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore
the seconds value.
D7 D6 D5 D4 D3 D2 D1 D0
X X 10s Centuries Centuries
D7 D6 D5 D4 D3 D2 D1 D0
WDF AF PF X X CAL W R
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. It is
cleared to 0 when the Flags/Control register is read.
Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. It is
cleared when the Flags/Control register is read.
Power-fail Flag. This read-only bit is set to 1 when power fal ls below the power-fail threshold Vswitch. It is cleared to 0 whe n the Flags/Control register is read.
Write Time. Setting the W bit to 1 freezes updates of the timekeeping registers. The user can then write them with updated values. Setting
the W bit to 0 causes the contents of the time registers to be transferred to the timekeeping counters.
Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a holding register. The user can
then read them without concerns over changing values causing system errors. The R bit going from 0 to 1 causes the timekeeping capture,
so the bit must be returned to 0 prior to reading again.
Alarm - Seconds
Timekeeping - Centuries
Flags
February 2004 20 Document Control # ML0023 rev 0.3
ORDERING INFORMATION
STK17TA8 - R F 45 I
STK17TA8
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (-40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
R = Plastic 48-pin 300 mil SSOP
W = Plastic 40-pin 600 mil DIP
February 2004 21 Document Control # ML0023 rev 0.3
STK17TA8
Document Revision History
Revision
0.0
0.1
0.2
0.3
Date Summary
February 2003 Publish new datasheet
March 2003
June 2003
February 2004 Change part number from STK17CA8 to STK17TA8; Add lead-free finish option
Remove 525 mil SOIC, Add 48 Pin SSOP and 40 Pin DIP packages; Modified Block Diagram in AutoStore description section
Modify 600 mil DIP pinout (switch pins 32 and 33), Update Power-up Recall specs, Update
Software Controlled Store/Recall Cycle, Added Hardware Store Description, Modified Mode
Selection Table, Updated Vswitch, Updated t
store
, Modify I
BAK
and V
BAK
February 2004 22 Document Control # ML0023 rev 0.3
Loading...