SIMTEK STK1743-D45I, STK1743-D35I, STK1743-D45, STK1743-D35, STK1743-D25I Datasheet

STK1743

8K x 8

FEATURES

• Data Integrity of Simtek nvSRAM Combined
with Full-Featured Real-Time Clock

• Stand-Alone Nonvolatile Memory and Time­Keepin g S olution—No Other Parts Required

• No Batteries to Fail

• Fast 25ns, 35ns and 45ns Access Times

• Software- and

AutoStore

Nonvolatile Cycles

• Year 2000 Compliant with Leap Year
Compensation

• 24-Hour BCD Format

• 100-Y ear Data Retention over Full Industrial
Temperature Range

• Full 30-Day RTC Operation on Each Power
Loss

• Single 5V ± 10% Power Supply

™-Controlled

AutoStore

nvTime

™ nvSRAM

™

with Real-Time Clock

ADVANCE

DESCRIPTION

The Simtek STK1743 DIP module houses 64Kb of
nonvolatile static
crystal and a high-value capacitor to support sys­tems that require high reliability and ease of manu­facturing.

READ and WRITE access to all RTC

functions and the memory is the same as a conven­tional x 8

RAM support clock registers for centuries, years,

SRAM. The highest eight addresses of the

months, dates, days, hours, minutes and seconds.
Independent data resides in the integral

all times. Automatic
the

EEPROM data to the SRAM, while an automatic

STORE

on power down transfers SRAM data to the

EEPROM. A software

possible on user command.

ited accesses to

STORE

s.

RAM, a real-time clock (RTC) with

EEPROM at

RECALL

RECALL

SRAM, unlimited

on power up transfers

and

nvTime

STORE

™ allows unlim-

RECALL

are also

s and 10

6

BLOCK DIAGRAM

A

5

A

6

A

7

A

8

A

9

A

DQ
DQ
DQ
DQ

DQ
DQ

DQ
DQ

11

A

12

0
1
2
3

4
5

6
7

ROW DECOD ER

COLUMN DEC

A0A

INPUT BUFFERS

EEPROM ARRAY

STATIC RAM

ARRA Y

128 x 512

CO L UM N I/O

A3A

2

1

128 x 512

A

A

10

4

STORE

RECALL

STORE/

RECALL

CONTROL

RTC

MUX

POWER

CONTROL

SOFTW ARE

DETECT

A0 ­A

12

PIN CONFIGURATIONS

NC

DQ
DQ
DQ

V

1
2

A

12

3

A

7

A

4

6

A

5

5

A

6

4

A

7

3

8

A

2

9

A

1

10

A

0

11

0

12

1

13

2

14

SS

V

CC

A0 - A

12

28

V

CC

27

W

26

NC

25

A

8

A

24

9

23

A

11

22

G

21

A

10

20

E

19

DQ

7

DQ
DQ
DQ
DQ

6
5
4
3

600 mil
Dual
In-Line
Module

18
17
16
15

PIN NAM ES

A0 - A

12

W

- DQ

DQ

0

E

G

E
W

G
V

CC

V

SS

7

Address I nputs
Write E nable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground

March 1999 7-1

STK1743

ABSOLUTE MAXIMUM RATINGS

a

Voltage on Inpu t Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V)

Voltage on DQ

. . . . . . . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)

0-7

Temperature under Bias. . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

DC Output Current (1 output at a time, 1s duration ) . . . . . . . 15mA

DC CHARAC TERISTICS (VCC = 5.0V ± 10%)

Note a: Stresses greater than those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device.
This a stress rating only, and functional operation of the
device at conditions above those indicated in the opera­tional sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.

SYMBOL PARAMETER

b

I

CC

I

CC

I

CC

I

CC

I

SB

I

SB

I

ILK

I

OLK

V

IH

V

IL

V

OH

V

OL

T

A

Note b: I
Note c: I
Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.

Average VCC Current 85

1

c

Average VCC Current during

2

b

Average VCC Current at t

3

c

Average VCC Current during

4

AutoStore

d

Average VCC Current

1

(Standby, Cycling TTL Input Levels)

d

VCC Standby Current

2

(Standby, Stable CMOS Input Lev els)
Input Leakage Current

Off-Stat e Output Leakage Current

Input Logic “ 1” Voltage 2.2 V
Input Logic “ 0” Voltage VSS – .5 0 . 8 VSS – .5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Vo ltage 0.4 0.4 V I
Operating Temperatur e 0 70 –40 85

and I

CC

1

and I

CC

2

™ Cycle

are dependent on output loading and cycle rate. The specified values are obtained at minimum cycle with outputs unloaded.

CC

3

are the average currents required for the duration of the respective

CC

4

AVAV

STORE

= 200ns

COMMERCIAL INDUSTRIAL

MIN MAX MIN MAX

80
75

67mAAll Inputs Don’t Care, VCC = max

15 15 mA

44mA

30
26
23

33mA

1

±

5

±

+ .5 2.2 VCC + .5 V All Inputs

CC

95
85
80

31
27
24

±

±

1

5

STORE

UNITS NOTES

mA
mA
mA

mA
mA
mA

A

µ

A

µ

C

°

cycles (t

t

= 25ns

AVAV

t

= 35ns

AVAV

t

= 45ns

AVAV

W

≥ (V

– 0.2V)

CC

All Others Cyc ling, CMOS Levels
All Inputs Don’t Care

t

= 25ns, E

AVAV

t

= 35ns, E ≥ V

AVAV

t

= 45ns, E ≥ V

AVAV

E ≥ (VCC – 0.2V)
All Others V

V

= max

CC

V

= VSS to V

IN

V

= max

CC

V

= V

IN

SS

= –4mA

OUT

= 8mA

OUT

).

STORE

V

≥

IH
IH
IH

≤ 0.2V or ≥ (VCC – 0.2V)

IN

CC

to VCC, E or G ≥

V

IH

AC TEST CO NDITIONS

Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V

Input Ris e and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns

Input and Output Timing Reference Levels. . . . . . . . . . . . . . . .1.5V

Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

CAPACITANCE

SYMBOL PARAMETER MAX UNITS CONDITIONS

C

IN

C

OUT

Note e: These parameters are guaranteed but not tested.

Input Capacitance
Output Cap ac itance

e

(TA = 25°C, f = 1.0M Hz)

10 pF
12 pF

∆V = 0 to 3V
∆V = 0 to 3V

March 1999 7-2

OUTPUT

5.0V

480 Ohms

30 pF

255 Ohm s

INCLUDING
SCOPE AND
FIXTURE

Figure 1: AC Output Loading

STK1743

READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)

NO.

10 t
11 t

#1, #2 Alt. MIN MAX MIN MA X MI N M AX

1t

ELQV

2t

AVAV

3t

AVQV

4t

GLQV

5t

AXQX

6t

ELQX

7t

EHQZ

8t

GLQX

9t

GHQZ
ELICCH
EHICCL

SYMBOLS

f

g

g

h

h

e

d, e

t

ACS

t

RC

t

AA

t

OE

t

OH

t

LZ

t

HZ

t

OLZ

t

OHZ

t

PA

t

PS

Chip Enable Access Time 25 35 45 ns
Read Cycle Time 25 35 45 ns
Address Access Time 25 35 45 ns
Output Enable to Data Valid 10 15 20 ns
Output Hold after Address Change 5 5 5 ns
Chip Enable t o Output Activ e 5 5 5 ns
Chip Disable to Output Inac tive 10 13 15 ns
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 10 13 15 ns
Chip Enable t o P ower Active 0 0 0 ns
Chip Disable to Power Standby 25 35 45 ns

PARAMETER

Note f: W must be high during SRAM READ cycles and low during SRA M WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.

READ CY C LE #1: Add ress Controlled

f, g

t

AVAV

2

ADDRESS

3

t

t

AXQX

5

AVQV

DQ (DATA OUT)

STK1743-25 STK1743-35 STK1743-45

DATA VALID

UNITS

READ CY C LE #2: E Contro lled

ADDRESS

6

STANDBY

t

ELQX

t

GLQX

10

t

ELICCH

DQ (DATA OUT)

I

CC

E

G

f

2

t

AVAV

1

t

ELQV

4

t

GLQV

8

DATA VALID

ACTIVE

t

GHQZ

9

t

EHQZ

t

7

11

EHICCL

March 1999 7-3