Datasheet STK16C88-W25, STK16C88-W20, STK16C88-S35I, STK16C88-S25I, STK16C88-S35 Datasheet (SIMTEK)
...
July 1999 5-65
STK16C88
32K x 8 AutoStorePlus™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• Transparent Data Save on Power Down
• Internal Capacitor Guarantees AutoStore™
Regardless of Power-Down Slew Rate
• Nonvolatile Storage without Battery Problems
• Directly Replaces 32K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 20ns, 25ns, 35ns and 45ns Access Times
• STORE to EEPROM Initiated by Software or
AutoStorePlus™ on Power Down
• No Data Loss from Undershoot
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA T ypical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention over Full Industrial
Temperature Range
• Commercial and Industrial Temperatures
• 28-Pin PDIP and SOIC Packages
DESCRIPTION
The STK16C88 is a fast SRAM with a nonvolatile
EEPROM element incorporated in each static mem-
ory cell. The
SRAM can be read and written an
unlimited number of times, while independent nonvolatile data resides in
EEPROM. Data transfers from
the
SRAM to the EEPROM (the STORE operation) can
take place automatically on power down. An internal
capacitor guarantees the
STORE operation regard-
less of power-down slew rate. Transfers from the
EEPROM to the SRAM (the RECALL operation) take
place automatically on restoration of power. Initiation of
STORE and RECALL cycles can also be con-
trolled by entering control sequences on the
SRAM
inputs. The STK16C88 is pin-compatible with 32k x
8
SRAMs and battery-backed SRAMs, allowing direct
substitution while enhancing performance. The
STK14C88, which uses an external capacitor, and
the STK15C88, which uses charge stored in system
capacitance, are alternatives for systems needing
AutoStorePlus™ operation.
BLOCK DIAGRAM
EEPROM ARRAY
512 x 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
512 x 512
ROW DECODER
INPUT BUFFERS
STORE/
RECALL
CONTROL
POWER
CONTROL
A
6
A
7
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
SOFTWARE
DETECT
V
CC
A0 - A
13
G
E
W
A
9
A
8
A
10
A3A
2
A0A
1
A
4
A
5
INTERNAL
CAPACITOR
PIN CONFIGURATIONS
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
D
Q
2
V
SS
V
CC
A
13
A
8
A
9
A
11
G
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - 600 PDIP
28 - 350 SOIC*
*see order info
PIN NAMES
A0 - A
14
Address Inputs
W Write Enable
DQ0 - DQ
7
Data In/Out
E Chip Enable
G Output Enable
V
CC
Power (+ 5V)
V
SS
Ground
STK16C88
July 1999 5-66
ABSOLUTE MAXIMUM RATINGS
a
Volt age on Input Relati ve to VSS. . . . . . . . . . –0.6V to (VCC + 0.5V)
Volt age on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
b
Note b: The STK16C88-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
CC
1
and I
CC
3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note d: I
CC
2
and I
CC
4
are the average currents required for the duration of the respective STORE cycles (t
STORE
).
Note e: E
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
CAPACITANCE
f
(TA = 25°C, f = 1.0MHz)
Note f: These parameters are guaranteed but not tested.
SYMBOL PARAMETER
COMMERCIAL INDUSTRIAL
UNITS NOTES
MIN MAX MIN MAX
I
CC
1
c
Average VCC Current 110
97
80
70
N/A
100
85
70
mA
mA
mA
mA
t
AVAV
= 20ns
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
I
CC
2
d
Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max
I
CC
3
c
Average VCC Current at t
AVAV
= 200ns
5V, 25°C, Typical
10 10 mA
W
≥ (V
CC
– 0.2V)
All Others Cycling, CMOS Levels
I
SB
1
e
Average VCC Current
(Standby, Cycling TTL Input Levels)
35
30
25
22
N/A
31
26
23
mA
mA
mA
mA
t
AVAV
= 20ns, E ≥ V
IH
t
AVAV
= 25ns, E ≥ V
IH
t
AVAV
= 35ns, E ≥ V
IH
t
AVAV
= 45ns, E ≥ V
IH
I
SB
2
e
VCC Standby Current
(Standby, Stable CMOS Input Levels)
1.5 1.5 mA
E
≥ (VCC – 0.2V)
All Others V
IN
≤ 0.2V or ≥ (VCC – 0.2V)
I
ILK
Input Leakage Current
±1 ±1 µA
V
CC
= max
V
IN
= VSS to V
CC
I
OLK
Off-State Output Leakage Current
±5 ±5 µA
V
CC
= max
V
IN
= V
SS
to VCC, E or G ≥ VIH
V
IH
Input Logic “1” Voltage 2.2 V
CC
+ .5 2.2 VCC + .5 V All Inputs
V
IL
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
V
OH
Output Logic “1” Voltage 2.4 2.4 V I
OUT
= –4mA
V
OL
Output Logic “0” Voltage 0.4 0.4 V I
OUT
= 8mA
T
A
Operating Temperature 0 70 –40 85 °C
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
Input Capacitance
5pF
∆V = 0 to 3V
C
OUT
Output Capacitance
7pF
∆V = 0 to 3V
Figure 1: AC Output Loading
480 Ohms
30 pF
255 Ohms
5.0V
INCLUDING
UTPUT
SCOPE AND
FIXTURE
STK16C88
July 1999 5-67
SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)
b
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E
, G < VIL and W > VIH; device is continuously selected.
Note i: Measured +
200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
g, h
SRAM READ CYCLE #2: E Controlled
g
NO.
SYMBOLS
PARAMETER
STK16C88-20 STK16C88-25 STK16C88-35 STK16C88-45
UNITS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1t
ELQV
t
ACS
Chip Enable Access Time 2 0 25 35 45 ns
2t
AVAV
g
t
RC
Read Cycle Time 20 25 35 45 ns
3t
AVQV
h
t
AA
Address Access Time 22 25 35 45 ns
4t
GLQV
t
OE
Output Enable to Data Valid 8 10 15 20 ns
5t
AXQX
h
t
OH
Output Hol d after Address Chang e 5 5 5 5 ns
6t
ELQX
t
LZ
Chip Enable to Output Active 5 5 5 5 ns
7t
EHQZ
i
t
HZ
Chip Disable to Output Inactive 7 10 13 15 ns
8t
GLQX
t
OLZ
Output Enable to Output Active 0 0 0 0 ns
9t
GHQZ
i
t
OHZ
Output Disable to Output Inactive 7 10 13 15 ns
10 t
ELICCH
f
t
PA
Chip Enable to Power Active 0 0 0 0 ns
11 t
EHICCL
e, f
t
PS
Chip Disable to Power Standby 25 25 35 45 ns
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
STANDBY
DATA VALID
DQ (DATA OUT)
E
ADDRESS
2
t
AVAV
G
I
CC
ACTIVE
1
t
ELQV
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
6
t
ELQX
8
t
GLQX
4
t
GLQV
10
t
ELICCH
STK16C88
July 1999 5-68
SRAM WRITE CYC LES #1 & #2 (VCC = 5.0V ± 10%)
b
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E
or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlled
k
SRAM WRITE CYCLE #2: E Controlled
k
NO.
SYMBOLS
PARAMETER
STK16C88-20 STK16C88-25 STK16C88-35 STK16C88-45
UNITS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
12 t
AVAV
t
AVAV
t
WC
Write Cycle Time 20 25 35 45 ns
13 t
WLWH
t
WLEH
t
WP
Write Pulse Width 15 20 25 30 ns
14 t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write 15 20 25 30 ns
15 t
DVWH
t
DVEH
t
DW
Data Set-up to End of Write 8 10 12 15 ns
16 t
WHDX
t
EHDX
t
DH
Data Hold after End of Write 0 0 0 0 ns
17 t
AVWH
t
AVEH
t
AW
Address Set-up to End of Write 15 20 25 30 ns
18 t
AVWL
t
AVEL
t
AS
Address Set-up to Start of Write 0 0 0 0 ns
19 t
WHAX
t
EHAX
t
WR
Address Hold after End of Writ e 0 0 0 0 ns
20 t
WLQZ
i, j
t
WZ
Write Enable to Output Disable 7 10 13 15 ns
21 t
WHQX
t
OW
Output Active after End of Write 5 5 5 5 ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
t
AVAV
W
16
t
WHDX
DATA IN
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVWH
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
DATA OUT
E
ADDRESS
12
t
AVAV
W
DATA IN
13
t
WLEH
DATA VALID
HIGH IMPEDANCE
14
t
ELEH
18
t
AVEL
17
t
AVEH
15
t
DVEH
19
t
EHAX
16
t
EHDX
STK16C88
July 1999 5-69
AutoStorePlus™/POWER-UP RECALL (VCC = 5.0V ± 10%)
b
Note l: t
RESTORE
starts from the time VCC rises above V
SWITCH
.
AutoStorePlus™/POWER-UP RECALL
NO.
SYMBOLS
PARAMETER
STK16C88
UNITS NOTES
Standard MIN MAX
22 t
RESTORE
Power-up RECALL Duration 550 µsl
23 t
PDI
Power-down AutoStore™ Initiation Time 500 ns f, h
24 V
SWITCH
Low Voltage Trigger Level 4.0 4.5 V
25 V
RESET
Low Voltage Reset Level 3.9 V
V
CC
V
SWITCH
V
RESET
OWER-UP RECALL
W
DQ (DATA OUT)
AutoStore™
5V
22
t
RESTORE
23
t
FB
24
25
BROWN OUT
AutoStorePlus™
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStorePlus™
RECALL WHEN
V
CC
RETURNS
ABOVE V
SWITCH
POWER-UP
RECALL
BROWN OUT
NO STORE DUE TO
NO SRAM WRITES
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
STK16C88
July 1999 5-70
SOFTW ARE ST ORE/RECALL MODE SELECTION
Note m: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note n: While there are 15 addresses on the STK16C88, only the lower 14 are used to control software modes.
SOFTW ARE ST ORE/RECALL CYCLE
o, p
(VCC = 5.0V ± 10%)
b
Note o: The software sequence is clocked with E controlled reads.
Note p: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,
303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W
must be high during all six consecutive
cycles.
SOFTW ARE ST ORE/RECALL CYCLE: E Controlled
p
E W A13 - A0 (hex) MODE I/O NOTES
LH
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
m, n
LH
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
m, n
NO. SYMBOLS PARAMETER
STK16C88-20 STK16C88-25 STK16C88-35 STK16C88-45
UNITS
MIN MAX MIN MAX MIN MAX MIN MAX
26 t
AVAV
STORE/RECALL Initiation Cycle Time 20 25 35 45 ns
27 t
AVEL
o
Address Set-up Time 0000ns
28 t
ELEH
o
Clock Pulse Width 15 20 25 30 ns
29 t
ELAX
h, o
Address Hold Time 15 20 20 20 ns
30 t
RECALL
RECALL Cycle Duration 20 20 20 20 µs
31 t
STORE
STORE Cycle Duration 10 10 10 10 ms
HIGH IMPEDANCE
ADDRESS #6ADDRESS #1
DATA VALID
26
t
AVAV
DATA VALID
DQ (DATA
E
ADDRESS
26
t
AVAV
27
t
AVEL
28
t
ELEH
29
t
ELAX
31 30
t
STORE
/ t
RECALL
STK16C88
July 1999 5-71
The AutoStorePlus™ STK16C88 is a fast 32K x 8
SRAM that does not lose its data on power-down.
The data is preserved in integral QuantumTrap™
EEPROM while power is unavailable. The nonvolatil-
ity of the STK16C88 does not require any system
intervention or support: AutoStorePlus™ on powerdown and automatic RECALL on power-up guarantee data integrity without the use of batteries
NOISE CONSIDERATIONS
Note that the STK16C88 is a high-speed memory
and so must have a high-frequency bypass capacitor of approximately 0.1µF connected between V
CC
and VSS, using leads and traces that are as short as
possible. As with all high-speed
CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK16C88 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A
0-14
determines which of the 32,768 data
bytes will be accessed. When the
READ is initiated
by an address transition, the outputs will be valid
after a delay of t
AVQV
(READ cycle #1). If the READ is
initiated by E
or G, the outputs will be valid at t
ELQV
or
at t
GLQV
, whichever is later (READ cycle #2). T h e d a ta
outputs will repeatedly respond to address changes
within the t
AVQV
access time without the need for transitions on any control input pins, and will remain valid
until another address change or until E
or G is
brought high.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the
WRITE cycle and must remain stable
until either E
or W goes high at the end of the cycle.
The data on the common I/O pins DQ
0-7
will be writ-
ten into the memory if it is valid t
DVWH
before the end
of a W
controlled WRITE or t
DVEH
before the end of an
E
controlled WRITE.
It is recommended that G
be kept high during the
entire
WRITE cycle to avoid data bus contention on
the common I/ O li nes. If G
is left low, internal circuitry
will turn off the output buffers t
WLQZ
after W goes low.
AutoStorePlus™ OPERATION
The STK16C88’s automatic STORE on power-down
is completely transparent to the system. The
AutoStore™ initiation takes less than 500ns when
power is lost (V
CC
< V
SWITCH
) at which point the part
depends only on its internal capacitor for
STORE
completion. This safe transfer of data from SRAM to
EEPROM takes place regardless of power supply
slew rate.
In order to prevent unneeded
STORE operations,
automatic
STOREs will be ignored unless at least
one
WRITE operation has taken place since the
most recent
STORE or RECALL cycle. Software-
initiated
STORE cycles are performed regardless of
whether or not a
WRITE operation has taken place.
POWER-UP RECALL
During power up, or after any low-power condition
(V
CC
< V
RESET
), an internal RECALL request will be
latched. When V
CC
once again exceeds the sense
voltage of V
SWITCH
, a RECALL cycle will automatically
be initiated and will take t
RESTORE
to complete.
If the STK16C88 is in a
WRITE state at the end of
power-up
RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10kΩ resistor should
be connected either between W
and system VCC or
between E
and system VCC.
SOFTWARE NONVOLATILE STORE
The STK16C88 software STORE cycle is initiated by
executing sequential
READ cycles from six specific
address locations. During the
STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the
SRAM data into
nonvolatile memory. Once a
STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of
READs from specific
addresses is used for
STORE initiation, it is impor-
tant that no other
READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no
STORE or RECALL will take place.
To initiate the software
STORE cycle, the following
READ sequence must be performed:
DEVICE OPERATION
STK16C88
July 1999 5-72
1. Read address 0E38 (hex) Vali d READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Vali d READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0FC0 (hex) Initiate STORE cycle
The software sequence must be clocked with E
controlled READs.
Once the sixth address in the sequence has been
entered, the
STORE cycle will commence and the
chip will be disabled. It is important that
READ
cycles and not WRITE cycles be used in the
sequence, although it is not necessary that G
be
low for the sequence to be valid. After the t
STORE
cycle time has been fulfilled, the SRAM will again be
activated for
READ and WRITE operation.
SOFTWARE NONVOL ATILE RECALL
A software RECALL cycle is initiated with a
sequence of
READ operations in a manner similar
to the software
STORE initiation. To initiate the
RECALL cycle, the following sequence of READ
operations must be performed:
1. Read address 0E38 (hex) Vali d READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Vali d READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0C63 (hex) Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First,
the
SRAM data is cleared, and second, the nonvola-
tile information is transferred into the
SRAM cells.
After the t
RECALL
cycle time the SRAM will once again
be ready for
READ and WRITE operations. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled
an unlimited number of times.
HARDWARE PROTECT
The STK16C88 offers hardware protection against
inadvertent
STORE operation and SRAM WRITEs
during low-voltage conditions. When V
CC
< V
SWITCH
,
all software
STORE operations and SRAM WRITEs
are inhibited.
LOW AVERAGE ACTIVE POW ER
The STK16C88 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
CC
and READ cycle
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
perature range, V
CC
= 5.5V, 100% duty cycle on
chip enable). Figure 3 shows the same relationship
for
WRITE cycles. If the chip enable duty cycle is
less than 100%, only standby current is drawn
when the chip is disabled. The overall average current drawn by the STK16C88 depends on the following items: 1)
CMOS vs. TTL input levels; 2) the
duty cycle of chip enable; 3) the overall cycle rate
for accesses; 4) the ratio of
READs to WRITEs; 5)
the operating temperature; 6) the V
CC
level; and 7) I/
O loading.
Figure 2: ICC (max) Reads
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
Figure 3: ICC (max) Writes
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
STK16C88
July 1999 5-73
ORDERING INFORM ATION
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C
)
Access Time
20 = 20ns (Commercial only)
25 = 25ns
35 = 35ns
45 = 45ns
Package
W = Plastic 28-pin 600 mil DIP
S = Plastic 28-pin 350 mil SOIC*
*(call factory for availability of this package)
- W 25 I
STK16C88
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