SIMTEK STK16C88-W25, STK16C88-W20, STK16C88-S35I, STK16C88-S25I, STK16C88-S35 Datasheet

July 1999 5-65

STK16C88

32K x 8 AutoStorePlus™ nvSRAM

QuantumTrap™ CMOS

Nonvolatile Static RAM

FEATURES

• Transparent Data Save on Power Down

• Internal Capacitor Guarantees AutoStore™

Regardless of Power-Down Slew Rate

• Nonvolatile Storage without Battery Problems

• Directly Replaces 32K x 8 Static RAM, Battery-

Backed RAM or EEPROM

• 20ns, 25ns, 35ns and 45ns Access Times

• STORE to EEPROM Initiated by Software or
AutoStorePlus™ on Power Down

• No Data Loss from Undershoot

• RECALL to SRAM Initiated by Software or

Power Restore

• 10mA T ypical I

CC

at 200ns Cycle Time

• Unlimited READ, WRITE and RECALL Cycles

• 1,000,000 STORE Cycles to EEPROM

• 100-Year Data Retention over Full Industrial

Temperature Range

• Commercial and Industrial Temperatures

• 28-Pin PDIP and SOIC Packages

DESCRIPTION

The STK16C88 is a fast SRAM with a nonvolatile

EEPROM element incorporated in each static mem-

ory cell. The

SRAM can be read and written an

unlimited number of times, while independent non­volatile data resides in

EEPROM. Data transfers from

the

SRAM to the EEPROM (the STORE operation) can

take place automatically on power down. An internal
capacitor guarantees the

STORE operation regard-

less of power-down slew rate. Transfers from the

EEPROM to the SRAM (the RECALL operation) take

place automatically on restoration of power. Initia­tion of

STORE and RECALL cycles can also be con-

trolled by entering control sequences on the

SRAM

inputs. The STK16C88 is pin-compatible with 32k x
8

SRAMs and battery-backed SRAMs, allowing direct

substitution while enhancing performance. The
STK14C88, which uses an external capacitor, and
the STK15C88, which uses charge stored in system
capacitance, are alternatives for systems needing
AutoStorePlus™ operation.

BLOCK DIAGRAM

EEPROM ARRAY

512 x 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

STATIC RAM

ARRAY

512 x 512

ROW DECODER

INPUT BUFFERS

STORE/

RECALL

CONTROL

POWER

CONTROL

A

6

A

7

A

11

A

12

A

13

A

14

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

SOFTWARE

DETECT

V

CC

A0 - A

13

G

E
W

A

9

A

8

A

10

A3A

2

A0A

1

A

4

A

5

INTERNAL

CAPACITOR

PIN CONFIGURATIONS

A

14

A

12

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

DQ

0

DQ

1

D

Q

2

V

SS

V

CC

A

13

A

8

A

9

A

11

G

W

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

A

10

E
DQ

7

DQ

6

DQ

5

DQ

4

DQ

3

28 - 600 PDIP
28 - 350 SOIC*
*see order info

PIN NAMES

A0 - A

14

Address Inputs
W Write Enable
DQ0 - DQ

7

Data In/Out
E Chip Enable
G Output Enable
V

CC

Power (+ 5V)
V

SS

Ground

STK16C88

July 1999 5-66

ABSOLUTE MAXIMUM RATINGS

a

Volt age on Input Relati ve to VSS. . . . . . . . . . –0.6V to (VCC + 0.5V)

Volt age on DQ

0-7

. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)

Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA

Note a: Stresses greater than those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions
above those indicated in the operational sections of this specifica­tion is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect reliability.

DC CHARACTERISTICS (VCC = 5.0V ± 10%)

b

Note b: The STK16C88-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I

CC

1

and I

CC

3

are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

Note d: I

CC

2

and I

CC

4

are the average currents required for the duration of the respective STORE cycles (t

STORE

).

Note e: E

≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.

AC TEST CONDITIONS

CAPACITANCE

f

(TA = 25°C, f = 1.0MHz)

Note f: These parameters are guaranteed but not tested.

SYMBOL PARAMETER

COMMERCIAL INDUSTRIAL

UNITS NOTES

MIN MAX MIN MAX

I

CC

1

c

Average VCC Current 110

97
80
70

N/A
100

85
70

mA
mA
mA
mA

t

AVAV

= 20ns

t

AVAV

= 25ns

t

AVAV

= 35ns

t

AVAV

= 45ns

I

CC

2

d

Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max

I

CC

3

c

Average VCC Current at t

AVAV

= 200ns

5V, 25°C, Typical

10 10 mA

W

≥ (V

CC

– 0.2V)

All Others Cycling, CMOS Levels

I

SB

1

e

Average VCC Current
(Standby, Cycling TTL Input Levels)

35
30
25
22

N/A

31
26
23

mA
mA
mA
mA

t

AVAV

= 20ns, E ≥ V

IH

t

AVAV

= 25ns, E ≥ V

IH

t

AVAV

= 35ns, E ≥ V

IH

t

AVAV

= 45ns, E ≥ V

IH

I

SB

2

e

VCC Standby Current
(Standby, Stable CMOS Input Levels)

1.5 1.5 mA

E

≥ (VCC – 0.2V)

All Others V

IN

≤ 0.2V or ≥ (VCC – 0.2V)

I

ILK

Input Leakage Current

±1 ±1 µA

V

CC

= max

V

IN

= VSS to V

CC

I

OLK

Off-State Output Leakage Current

±5 ±5 µA

V

CC

= max

V

IN

= V

SS

to VCC, E or G ≥ VIH

V

IH

Input Logic “1” Voltage 2.2 V

CC

+ .5 2.2 VCC + .5 V All Inputs

V

IL

Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs

V

OH

Output Logic “1” Voltage 2.4 2.4 V I

OUT

= –4mA

V

OL

Output Logic “0” Voltage 0.4 0.4 V I

OUT

= 8mA

T

A

Operating Temperature 0 70 –40 85 °C

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V

Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels. . . . . . . . . . . . . . . 1.5V

Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1

SYMBOL PARAMETER MAX UNITS CONDITIONS

C

IN

Input Capacitance

5pF

∆V = 0 to 3V

C

OUT

Output Capacitance

7pF

∆V = 0 to 3V

Figure 1: AC Output Loading

480 Ohms

30 pF

255 Ohms

5.0V

INCLUDING

UTPUT

SCOPE AND
FIXTURE

STK16C88

July 1999 5-67

SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)

b

Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E

, G < VIL and W > VIH; device is continuously selected.

Note i: Measured +

200mV from steady state output voltage.

SRAM READ CYCLE #1: Address Controlled

g, h

SRAM READ CYCLE #2: E Controlled

g

NO.

SYMBOLS

PARAMETER

STK16C88-20 STK16C88-25 STK16C88-35 STK16C88-45

UNITS

#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX

1t

ELQV

t

ACS

Chip Enable Access Time 2 0 25 35 45 ns

2t

AVAV

g

t

RC

Read Cycle Time 20 25 35 45 ns

3t

AVQV

h

t

AA

Address Access Time 22 25 35 45 ns

4t

GLQV

t

OE

Output Enable to Data Valid 8 10 15 20 ns

5t

AXQX

h

t

OH

Output Hol d after Address Chang e 5 5 5 5 ns

6t

ELQX

t

LZ

Chip Enable to Output Active 5 5 5 5 ns

7t

EHQZ

i

t

HZ

Chip Disable to Output Inactive 7 10 13 15 ns

8t

GLQX

t

OLZ

Output Enable to Output Active 0 0 0 0 ns

9t

GHQZ

i

t

OHZ

Output Disable to Output Inactive 7 10 13 15 ns

10 t

ELICCH

f

t

PA

Chip Enable to Power Active 0 0 0 0 ns

11 t

EHICCL

e, f

t

PS

Chip Disable to Power Standby 25 25 35 45 ns

DATA VALID

5

t

AXQX

3

t

AVQV

DQ (DATA OUT)

ADDRESS

2

t

AVAV

STANDBY

DATA VALID

DQ (DATA OUT)

E

ADDRESS

2

t

AVAV

G

I

CC

ACTIVE

1

t

ELQV

11

t

EHICCL

7

t

EHQZ

9

t

GHQZ

6

t

ELQX

8

t

GLQX

4

t

GLQV

10

t

ELICCH