SIMTEK STK16C68-W45I, STK16C68-W35I, STK16C68-W45, STK16C68-W35, STK16C68-W25I Datasheet
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STK16C68
8K x 8 AutoStorePlus™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• Transparent Data Save on Power Down
• Internal Capacitor Guarantees AutoStore™
Regardless of Power-Down Slew Rate
• Nonvolatile Storage without Battery Problems
• Directly Replaces 8K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 20ns, 25ns, 35ns and 45ns Access Times
• STORE to EEPROM Initiated by Software or
AutoStorePlus™ on Power Down
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA T ypical I
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention over Full Industrial
Temperature Range
• No Data Loss from Undershoot
• Commercial and Industrial Temperatures
• 28-Pin 600 mil PDIP and 350 mil SOIC Packages
at 200ns Cycle Time
CC
DESCRIPTION
The STK16C68 is a fast SRAM with a nonvolatile
EEPROM element incorporated in each static memory
cell. The
number of times, while independent nonvolatile data
resides in
the
automatically on power down. An internal capacitor
guarantees the
down slew rate. Transfers from the
SRAM (the RECALL operation) take place automatically
on restoration of power. Initiation of
RECALL cycles can also be controlled by entering con-
trol sequences on the
pin-compatible with 8k x 8
SRAMs, allowing direct substitution while enhancing
performance. The STK12C68, which uses an external
capacitor, and the STK15C68, which uses charge
stored in system capacitance, are alternatives for systems needing AutoStore™ operation.
SRAM can be read and written an unlimited
EEPROM. Data transfers from the SRAM to
EEPROM (the STORE operation) can take place
STORE operation regardless of power-
EEPROM to the
STORE and
SRAM inputs. The STK16C68 is
SRAMs and battery-backed
BLOCK DIAGRAM
EEPROM ARRAY
128 x 512
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
5
A
6
A
7
A
8
A
9
A
11
A
12
0
1
2
3
4
5
6
7
INPUT BUFFERS
ROW DECODER
STATIC RAM
ARRAY
128 x 512
COLUMN I/O
COLUMN DEC
A0A
2
1
A3A
STORE
RECALL
A
A
10
4
STORE/
RECALL
CONTROL
SOFTWARE
July 1999 4-73
CAPACITOR
DETECT
V
CC
POWER
CONTROL
INTERNAL
G
E
W
A0 - A
PIN CONFIGURATIONS
NC
1
A
2
12
3
A
7
A
4
6
A
5
5
A
6
4
A
7
3
8
A
2
9
A
1
10
A
0
11
DQ
0
12
DQ
1
DQ
13
2
V
14
SS
PIN NAMES
12
A0 - A
W Write Enable
DQ0 - DQ
E Chip Enable
G Output Enable
V
CC
V
SS
28
V
CC
27
W
26
NC
25
A
8
A
24
9
A
23
11
22
G
21
A
10
20
E
19
DQ
7
18
DQ
6
17
DQ
5
16
15
28 - 600 PDIP
DQ
4
28 - 350 SOIC*
DQ
3
*see order info
7
Address Inputs
Data In/Out
Power (+ 5V)
Ground
12
STK16C68
ABSOLUTE MAXIMUM RATINGS
Volt age on Input Rel ative to VSS. . . . . . . . . . –0.6V to (VCC + 0.5V)
Volt age on DQ
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
0-7
a
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
SYMBOL PARAMETER
c
I
CC
I
CC
I
CC
I
SB
I
SB
I
ILK
I
OLK
V
V
V
V
T
IH
IL
OH
OL
A
Average VCC Current 100
1
d
Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max
2
c
Average VCC Current at t
3
5V, 25°C, Typical
e
Average VCC Current
1
(Standby, Cycling TTL Input Levels)
e
VCC Standby Current
2
(Standby, Stable CMOS Input Levels )
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Volta ge 2.2 V
Input Logic “0” Volta ge VSS – .5 0.8 VSS – .5 0. 8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 –40 85 °C
AVAV
= 200ns
Note b: The STK16C68-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
Note d: I
Note e: E
and I
CC
1
and I
CC
2
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
are the average currents required for the duration of the respective STORE cycles (t
CC
4
COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX
N/A
90
75
65
10 10 mA
32
27
23
20
1.5 1.5 mA
±1 ±1 µA
±5 ±5 µA
+ .5 2.2 VCC + .5 V All Inputs
CC
90
75
65
N/A
28
24
21
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
t
= 20ns
AVAV
t
= 25ns
AVAV
t
= 35ns
AVAV
t
= 45ns
AVAV
W
≥ (V
– 0.2V)
CC
All Others Cycling, CMOS Levels
t
= 20ns, E ≥ V
AVAV
t
AVAV
t
AVAV
t
AVAV
E
≥ (VCC – 0.2V)
All Others V
V
CC
V
= VSS to V
IN
V
CC
V
= V
IN
OUT
OUT
).
STORE
= 25ns, E ≥ V
= 35ns, E ≥ V
= 45ns, E ≥ V
= max
= max
SS
= –4mA
= 8mA
IH
IH
IH
IH
≤ 0.2V or ≥ (VCC – 0.2V)
IN
CC
to VCC, E or G ≥ VIH
b
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
CAPACITANCE
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
C
IN
OUT
Input Capacitance
Output Capacitance
f
(TA = 25°C, f = 1.0MHz)
8pF
7pF
∆V = 0 to 3V
∆V = 0 to 3V
Note f: These parameters are guaranteed but not tested.
July 1999 4-74
OUTPUT
5.0V
480 Ohms
30 pF
255 Ohms
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
STK16C68
SRAM READ CYCLES #1 & #2 (V
NO.
10 t
11 t
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1t
ELQV
2t
AVAV
3t
AVQV
4t
GLQV
5t
AXQX
6t
ELQX
7t
EHQZ
8t
GLQX
9t
GHQZ
ELICCH
EHICCL
SYMBOLS
g
h
h
i
i
f
e, f
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time 20 25 35 45 ns
Read Cycle Time 20 25 35 45 ns
Address Access Time 22 25 35 45 ns
Output Enable to Data Valid 8 10 15 20 ns
Output Hol d after Address Change 5 5 5 5 ns
Chip Enable to Output Active 5 5 5 5 ns
Chip Disable to Output Inactive 7 10 13 15 ns
Output Enable to Output Active 0 0 0 0 ns
Output Disa ble to Outpu t Inactive 7 10 13 15 ns
Chip Enable to Power Active 0 0 0 0 ns
Chip Disable to Power Standby 25 25 35 45 ns
PARAMETER
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E
Note i: Measured +
, G < VIL and W > VIH; device is continuously selected.
200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
ADDRESS
t
AVQV
DQ (DATA OUT)
t
AXQX
5
STK16C68-20 STK16C68-25 STK16C68-35 STK16C68-45
g, h
2
t
AVAV
3
DATA VALID
= 5.0V ± 10%)
CC
b
UNITS
SRAM READ CYCLE #2: E Controlled
ADDRESS
t
ELQX
t
ELICCH
6
t
GLQX
10
4
t
GLQV
8
DQ (DATA OUT)
I
CC
E
G
STANDBY
g
t
AVAV
2
t
ELQV
ACTIVE
1
t
GHQZ
DATA VALID
t
9
7
EHQZ
t
EHICCL
11
July 1999 4-75
STK16C68
SRAM WRITE CYCLES #1 & #2 (V
NO.
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
WLWH
ELWH
DVWH
WHDX
AVWH
AVWL
WHAX
WLQZ
WHQX
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
AVAV
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
i, j
t
Write Cycle Time 20 25 35 45 ns
WC
t
Write Pulse Width 15 20 25 30 ns
WP
t
Chip Enable to End of Write 15 20 25 30 ns
CW
t
Data Set-up to End of Write 8 10 12 15 ns
DW
t
Data Hold after End of Write 0 0 0 0 ns
DH
t
Address Set-up to End of Wri te 15 20 25 30 ns
AW
t
Address Set-up to Start of Write 0 0 0 0 ns
AS
t
Address Hold after En d of Write 0 0 0 0 ns
WR
t
Write Enable to Output Disable 7 10 13 15 ns
WZ
t
Output Active afte r En d of Write 5 5 5 5 ns
OW
PARAMETER
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E
or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlled
ADDRESS
t
ELWH
E
STK16C68-20 STK16C68-25 STK16C68-35 STK16C68-45
k
12
t
AVAV
14
19
t
WHAX
= 5.0V ± 10%)
CC
b
UNITS
17
t
20
t
WLQZ
AVWH
13
t
WLWH
W
DATA IN
DA TA OUT
18
t
AVWL
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlled
ADDRESS
18
t
AVEL
E
1 7
t
AVEH
W
DATA IN
15
t
DVWH
DATA VALID
HIGH IMPEDANCE
16
t
WHDX
21
t
WHQX
k
12
t
AVAV
t
ELEH
14
13
t
WLEH
15
t
DVEH
DATA VALID
t
EHAX
t
EHDX
19
16
DA TA OUT
HIGH IMPEDANCE
July 1999 4-76
STK16C68
AutoStorePlus™/POWER-UP RECALL (V
NO.
22 t
23 t
24 V
25 V
Note l: t
SYMBOLS
Standard MIN MAX
RESTORE
FB
SWITCH
RESET
starts from the time VCC rises above V
RESTORE
Power-up RECALL Duration 550 µsl
Maximum VCC Slew Time to Ground 500 ns f , h
Low Voltage Trigger Level 4.0 4.5 V
Low Voltage Reset Level 3.9 V f
SWITCH
PARAMETER
.
AutoStorePlus™/POWER-UP RECALL
V
CC
5V
24
V
SWITCH
25
V
RESET
23
t
FB
AutoStore™
= 5.0V ± 10%)
CC
STK16C68
UNITS NOTES
b
OWER-UP RECALL
W
DQ (DATA OUT)
22
t
RESTORE
POWER-UP
RECALL
BROWN OUT
NO STORE DUE TO
NO SRAM WRITES
NO RECALL
(V
DID NOT GO
CC
BELOW V
RESET
)
BROWN OUT
AutoStorePlus™
NO RECALL
(V
DID NOT GO
CC
BELOW V
RESET
BROWN OUT
AutoStorePlus™
RECALL WHEN
V
RETURNS
CC
)
ABOVE V
SWITCH
July 1999 4-77
STK16C68
SOFTW ARE ST ORE/RECALL MODE SELECTION
E W G A12 - A0 (hex) MODE I/O with G Low I/O with G High NOTES
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
LHX
LHX
0000
1555
0AAA
1FFF
10F0
0F0F
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Note m: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
m
m
SOFTW ARE ST ORE/RECALL CYCLE
NO. SYMBOLS P ARAMETER
26 t
27 t
28 t
29 t
30 t
31 t
AVAV
n
AVEL
ELEH
h, n
ELAX
RECALL
STORE
n
STORE/RECALL Initiation Cycle Time 20 25 35 45 ns
Address Set-up Time 0 0 0 0 ns
Clock Pulse Width 15202530 ns
Address Hold Time 15 20 20 20 ns
RECALL Cycle Duration 20 20 20 20 µs
STORE Cycle Duration 10 10 10 10 ms
n, o
STK16C68-20 STK16C68-25 STK16C68-35 STK16C68-45
MIN MAX MIN MAX MIN MAX MIN MAX
(VCC = 5.0V ± 10%)
UNITS
Note n: The software sequence is clocked with E controlled READs.
Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0000, 1555, 0AAA, 1FFF,
10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W
must be high during all six consecutive
cycles.
SOFTW ARE ST ORE/RECALL CYCLE: E Controlled
26
t
AVAV
ADDRESS
27
t
AVEL
E
t
ELEH
28
o
26
t
AVAV
ADDRESS #6ADDRESS #1
b
29
t
ELAX
Q (DATA OUT)
DATA VALID
July 1999 4-78
DATA VALID
31 30
t
/ t
STORE
HIGH IMPEDANCE
RECALL
DEVICE OPERATION
STK16C68
The AutoStorePlus™ STK16C68 is a fast 8K x 8
SRAM that does not lose its data on power-down.
The data is preserved in integral QuantumTrap™
EEPROM while power is unavailable. The nonvolatil-
ity of the STK16C68 does not require any system
intervention or support: AutoStorePlus™ on powerdown and automatic RECALL on power-up guarantee data integrity without the use of batteries.
NOISE CONSIDERATIONS
Note that the STK16C68 is a high-speed memory
and so must have a high-frequency bypass capacitor of approximately 0.1µF connected between V
CC
and VSS, using leads and traces that are as short as
possible. As with all high-speed
CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK16C68 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A
bytes will be accessed. When the
determines which of the 8,192 data
0-12
READ is initiated
by an address transition, the outputs will be valid
after a delay of t
initiated by E
at t
, whichever is later (READ cycle #2). T h e d a ta
GLQV
or G, the outputs will be valid at t
(READ cycle #1). If the READ is
AVQV
ELQV
or
outputs will repeatedly respond to address changes
within the t
access time without the need for tran-
AVQV
sitions on any control input pins, and will remain valid
until another address change or until E
brought high or W
is brought low.
or G is
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the
until either E
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W
E
controlled WRITE or t
controlled WRITE.
It is recommended that G
entire
WRITE cycle to avoid data bus contention on
the common I/ O li nes. If G
will turn off the output buffers t
WRITE cycle and must remain stable
or W goes high at the end of the cycle.
will be writ-
0-7
before the end
DVWH
before the end of an
DVEH
be kept high during the
is left low, internal circuitry
after W goes low.
WLQZ
AutoStorePlus™ OPERATION
The STK16C68’s automatic STORE on power-down
is completely transparent to the system. The
AutoStore™ initiation takes less than 500ns when
power is lost (V
depends only on its internal capacitor for
CC
< V
) at which point the part
SWITCH
STORE
completion. This safe transfer of data from SRAM to
EEPROM takes place regardless of power supply
slew rate.
In order to prevent unneeded
automatic
WRITE operation has taken place since the most
recent
STORE cycles are performed regardless of whether
or not a
STORE will be ignored unless at least one
STORE or RECALL cycle. Software-initiated
WRITE operation has taken place.
STORE operations, the
POWER-UP RECALL
During power up, or after any low-power condition
(V
< V
CC
latched. When V
voltage of V
be initiated and will take t
If the STK16C68 is in a
power-up
), an internal RECALL request will be
RESET
once again exceeds the sense
CC
, a RECALL cycle will automatically
SWITCH
to complete.
RESTORE
WRITE state at the end of
RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10kΩ resistor should
be connected either between W
between E
and system VCC.
and system VCC or
SOFTWARE NONVOLATILE STORE
The STK16C68 software STORE cycle is initiated by
executing sequential
address locations. During the
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the
nonvolatile memory. Once a
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of
addresses is used for
tant that no other
vene in the sequence or the sequence will be
aborted and no
To initiate the software
READ sequence must be performed:
READ cycles from six specific
STORE cycle an erase
SRAM data into
STORE cycle is initi-
READs from specific
STORE initiation, it is impor-
READ or WRITE accesses inter-
STORE or RECALL will take place.
STORE cycle, the following
July 1999 4-79
STK16C68
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid REA D
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0F (hex) Initiate STORE cycle
The software sequence must be clocked with E
controlled READs.
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
STORE cycle will commence and the
READ
cycles and not WRITE cycles be used in the
sequence, although it is not necessary that G
low for the sequence to be valid. After the t
be
STORE
cycle time has been fulfilled, the SRAM will again be
activated for
READ and WRITE operation.
SOFTWARE NONVO LATILE RECALL
A software RECALL cycle is initiated with a
sequence of
to the software
RECALL cycle, the following sequence of READ
operations must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid REA D
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0E (hex) Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First,
the
SRAM data is cleared, and second, the nonvola-
READ operations in a manner similar
STORE initiation. To initiate the
tile information is transferred into the
After the t
be ready for
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled
cycle time the SRAM will once again
RECALL
READ and WRITE operations. The
SRAM cells.
an unlimited number of times.
HARDWARE PROTECT
The STK16C68 offers hardware protection against
inadvertent
during low-voltage conditions. When V
software
STORE operation and SRAM WRITEs
< V
CC
STORE operations and SRAM WRITEs are
SWITCH
inhibited.
LOW AVERAGE ACTIVE POW ER
The STK16C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
perature range, V
= 5.5V, 100% duty cycle on
CC
chip enable). Figure 3 shows the same relationship
for
WRITE cycles. If the chip enable duty cycle is
less than 100%, only standby current is drawn
when the chip is disabled. The overall average current drawn by the STK16C68 depends on the following items: 1)
CMOS vs. TTL input levels; 2) the
duty cycle of chip enable; 3) the overall cycle rate
for accesses; 4) the ratio of
the operating temperature; 6) the V
O loading.
and READ cycle
CC
READs to WRITEs; 5)
level; and 7) I/
CC
,
Figure 2: ICC (max) Reads
July 1999 4-80
100
Average Active Current (mA)
80
60
40
20
0
50 100 150 200
Cycle Time (ns)
Figure 3: ICC (max) Writes
TTL
CMOS
ORDERING INFOR M ATION
STK16C68
STK16C68
- W 25 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C
Access Time
20 = 20ns (Commercial only)
25 = 25ns
35 = 35ns
45 = 45ns
Package
W = Plastic 28-pin 600 mil DIP
*(call factory for availability of this package)
S = Plastic 28-pin 350 mil SOIC*
)
July 1999 4-81
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