SIMTEK STK16C68-W45I, STK16C68-W35I, STK16C68-W45, STK16C68-W35, STK16C68-W25I Datasheet

STK16C68

8K x 8 AutoStorePlus™ nvSRAM

QuantumTrap™ CMOS

Nonvolatile Static RAM

FEATURES

• Transparent Data Save on Power Down

• Internal Capacitor Guarantees AutoStore™

Regardless of Power-Down Slew Rate

• Nonvolatile Storage without Battery Problems

• Directly Replaces 8K x 8 Static RAM, Battery-

Backed RAM or EEPROM

• 20ns, 25ns, 35ns and 45ns Access Times

• STORE to EEPROM Initiated by Software or
AutoStorePlus™ on Power Down

• RECALL to SRAM Initiated by Software or

Power Restore

• 10mA T ypical I

• Unlimited READ, WRITE and RECALL Cycles

• 1,000,000 STORE Cycles to EEPROM

• 100-Year Data Retention over Full Industrial

Temperature Range

• No Data Loss from Undershoot

• Commercial and Industrial Temperatures

• 28-Pin 600 mil PDIP and 350 mil SOIC Packages

at 200ns Cycle Time

CC

DESCRIPTION

The STK16C68 is a fast SRAM with a nonvolatile

EEPROM element incorporated in each static memory

cell. The
number of times, while independent nonvolatile data
resides in
the
automatically on power down. An internal capacitor
guarantees the
down slew rate. Transfers from the

SRAM (the RECALL operation) take place automatically

on restoration of power. Initiation of

RECALL cycles can also be controlled by entering con-

trol sequences on the
pin-compatible with 8k x 8

SRAMs, allowing direct substitution while enhancing

performance. The STK12C68, which uses an external
capacitor, and the STK15C68, which uses charge
stored in system capacitance, are alternatives for sys­tems needing AutoStore™ operation.

SRAM can be read and written an unlimited

EEPROM. Data transfers from the SRAM to

EEPROM (the STORE operation) can take place

STORE operation regardless of power-

EEPROM to the

STORE and

SRAM inputs. The STK16C68 is

SRAMs and battery-backed

BLOCK DIAGRAM

EEPROM ARRAY

128 x 512

A

DQ
DQ
DQ
DQ

DQ
DQ

DQ
DQ

5

A

6

A

7

A

8

A

9

A

11

A

12

0
1
2
3

4
5

6
7

INPUT BUFFERS

ROW DECODER

STATIC RAM

ARRAY

128 x 512

COLUMN I/O

COLUMN DEC

A0A

2

1

A3A

STORE

RECALL

A

A

10

4

STORE/

RECALL

CONTROL

SOFTWARE

July 1999 4-73

CAPACITOR

DETECT

V

CC

POWER

CONTROL

INTERNAL

G

E
W

A0 - A

PIN CONFIGURATIONS

NC

1

A

2

12

3

A

7

A

4

6

A

5

5

A

6

4

A

7

3

8

A

2

9

A

1

10

A

0

11

DQ

0

12

DQ

1

DQ

13

2

V

14

SS

PIN NAMES

12

A0 - A
W Write Enable
DQ0 - DQ
E Chip Enable
G Output Enable
V

CC

V

SS

28

V

CC

27

W

26

NC

25

A

8

A

24

9

A

23

11

22

G

21

A

10

20

E

19

DQ

7

18

DQ

6

17

DQ

5

16
15

28 - 600 PDIP

DQ

4

28 - 350 SOIC*

DQ

3

*see order info

7

Address Inputs

Data In/Out

Power (+ 5V)
Ground

12

STK16C68

ABSOLUTE MAXIMUM RATINGS

Volt age on Input Rel ative to VSS. . . . . . . . . . –0.6V to (VCC + 0.5V)

Volt age on DQ

Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA

. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)

0-7

a

Note a: Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi­tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat­ing conditions for extended periods may affect reliability.

DC CHARACTERISTICS (VCC = 5.0V ± 10%)

SYMBOL PARAMETER

c

I

CC

I

CC

I

CC

I

SB

I

SB

I

ILK

I

OLK

V
V
V
V
T

IH
IL
OH
OL

A

Average VCC Current 100

1

d

Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max

2

c

Average VCC Current at t

3

5V, 25°C, Typical

e

Average VCC Current

1

(Standby, Cycling TTL Input Levels)

e

VCC Standby Current

2

(Standby, Stable CMOS Input Levels )
Input Leakage Current

Off-State Output Leakage Current

Input Logic “1” Volta ge 2.2 V
Input Logic “0” Volta ge VSS – .5 0.8 VSS – .5 0. 8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 –40 85 °C

AVAV

= 200ns

Note b: The STK16C68-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
Note d: I
Note e: E

and I

CC

1

and I

CC

2

≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.

are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

CC

3

are the average currents required for the duration of the respective STORE cycles (t

CC

4

COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX

N/A
90
75
65

10 10 mA

32
27
23
20

1.5 1.5 mA

±1 ±1 µA

±5 ±5 µA

+ .5 2.2 VCC + .5 V All Inputs

CC

90
75
65

N/A

28
24
21

UNITS NOTES

mA
mA
mA
mA

mA
mA
mA
mA

t

= 20ns

AVAV

t

= 25ns

AVAV

t

= 35ns

AVAV

t

= 45ns

AVAV

W

≥ (V

– 0.2V)

CC

All Others Cycling, CMOS Levels
t

= 20ns, E ≥ V

AVAV

t

AVAV

t

AVAV

t

AVAV

E

≥ (VCC – 0.2V)

All Others V
V

CC

V

= VSS to V

IN

V

CC

V

= V

IN

OUT
OUT

).

STORE

= 25ns, E ≥ V

= 35ns, E ≥ V
= 45ns, E ≥ V

= max

= max

SS

= –4mA
= 8mA

IH
IH
IH
IH

≤ 0.2V or ≥ (VCC – 0.2V)

IN

CC

to VCC, E or G ≥ VIH

b

AC TEST CONDITIONS

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V

Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels. . . . . . . . . . . . . . . 1.5V

Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1

CAPACITANCE

SYMBOL PARAMETER MAX UNITS CONDITIONS

C
C

IN

OUT

Input Capacitance
Output Capacitance

f

(TA = 25°C, f = 1.0MHz)

8pF
7pF

∆V = 0 to 3V
∆V = 0 to 3V

Note f: These parameters are guaranteed but not tested.

July 1999 4-74

OUTPUT

5.0V

480 Ohms

30 pF

255 Ohms

INCLUDING
SCOPE AND
FIXTURE

Figure 1: AC Output Loading

STK16C68

SRAM READ CYCLES #1 & #2 (V

NO.

10 t
11 t

#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX

1t

ELQV

2t

AVAV

3t

AVQV

4t

GLQV

5t

AXQX

6t

ELQX

7t

EHQZ

8t

GLQX

9t

GHQZ
ELICCH
EHICCL

SYMBOLS

g

h

h

i

i

f

e, f

t

ACS

t

RC

t

AA

t

OE

t

OH

t

LZ

t

HZ

t

OLZ

t

OHZ

t

PA

t

PS

Chip Enable Access Time 20 25 35 45 ns
Read Cycle Time 20 25 35 45 ns
Address Access Time 22 25 35 45 ns
Output Enable to Data Valid 8 10 15 20 ns
Output Hol d after Address Change 5 5 5 5 ns
Chip Enable to Output Active 5 5 5 5 ns
Chip Disable to Output Inactive 7 10 13 15 ns
Output Enable to Output Active 0 0 0 0 ns
Output Disa ble to Outpu t Inactive 7 10 13 15 ns
Chip Enable to Power Active 0 0 0 0 ns
Chip Disable to Power Standby 25 25 35 45 ns

PARAMETER

Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E
Note i: Measured +

, G < VIL and W > VIH; device is continuously selected.

200mV from steady state output voltage.

SRAM READ CYCLE #1: Address Controlled

ADDRESS

t

AVQV

DQ (DATA OUT)

t

AXQX

5

STK16C68-20 STK16C68-25 STK16C68-35 STK16C68-45

g, h

2

t

AVAV

3

DATA VALID

= 5.0V ± 10%)

CC

b

UNITS

SRAM READ CYCLE #2: E Controlled

ADDRESS

t

ELQX

t

ELICCH

6

t

GLQX

10

4

t

GLQV

8

DQ (DATA OUT)

I

CC

E

G

STANDBY

g

t

AVAV

2

t

ELQV

ACTIVE

1

t

GHQZ

DATA VALID

t

9

7

EHQZ

t

EHICCL

11

July 1999 4-75