SIMTEK STK15C68-P45I, STK15C68-P35I, STK15C68-P45, STK15C68-P35, STK15C68-P25I Datasheet
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STK15C68
8K x 8
FEATURES
• Nonvolatile Storage Without Battery Problems
• Directly Replaces 8K x 8 static RAM, Battery
Backed RAM or EEPROM
• 25ns, 35ns and 45ns Access Times
• Store to EEPROM Initiated by Software or
AutoStore
• Recall to SRAM by Software or Power Restore
• 15mA I
• Unlimited Read, Write and Recall Cycles
• 1,000,000 Store Cycles to EEPROM
• 100 Year Data Retention Over Full Industrial
Temperature Range
• Commercial and Industrial Temp. Ranges
• 28 Pin 600 or 300 mil PDIP and 350 mil SOIC
™ on Power Down
at 200ns Cycle Time
CC
AutoStore
™ nvSRAM
High Performance CMOS
Nonvolatile Static RAM
DESCRIPTION
The STK15C68 is a fast SRAM with a nonvolatile
EEPROM element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent, nonvolatile data
resides in EEPROM. Data transfers from the SRAM to
EEPROM (the
STORE
matically on power down using charge stored in system
capacitance. Transfers from the EEPROM to the SRAM
(the
RECALL
operation) take place automatically on restoration of power. Initiation of STORE and RECALL
cycles can also be controlled by entering control
sequences on the SRAM inputs. The nvSRAM can be
used in place of existing 8K x 8 SRAMs and also matches
the pinout of 8k x 8 Battery Backed SRAMs, EPROMs,
and EEPROMs, allowing direct substitution while enhancing performance. There is no limit on the number of read
or write cycles that can be executed and no support circuitry is required for microprocessor interface.
operation) can take place auto-
BLOCK DIAGRAM
A
5
A
6
A
7
A
8
A
9
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
11
A
12
0
1
2
3
4
5
6
7
ROW DECODER
AA
INPUT BUFFERS
EEPROM ARRAY
128 x 512
STATIC RAM
ARRAY
128 x 512
COLUMN I/O
COLUMN DEC
A AA
2A1
43
STORE
RECALL
100
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
VCC
PIN CONFIGURATIONS
1
NC
2
A
12
3
A
7
A
4
6
5
A
5
6
A
4
7
3
821
A
2
9
A
1
10
A
0
11
DQ
0
12
DQ
1
DQ
13
A
0
A
12
2
V
14
SS
28 - 300 PDIP
28
V
27
W
NC
26
25
A
A
24
23
A
GA
22
A
E
20
19
DQ
18 DQ
DQ
17
DQ
16
DQ
15
CC
8
9
11
10
7
6
5
4
3
28 - 600 PDIP
28 - 350 SOIC
PIN NAMES
A0 - A
12
G
E
W
W Write Enable
DQ0 - DQ
E Chip Enable
G Output Enable
V
CC
V
SS
7
Address Inputs
Data In/Out
Power (+5V)
Ground
4-61
STK15C68
ABSOLUTE MAXIMUM RATINGS
a
Voltage on input relative to VSS. . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
0-7
Temperature under bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
Note a: Stresses greater than those listed under “Absolute Max-
mum Ratings” may cause permanent damage to the
device. This a stress rating only, and functional operation
of the device at conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC CHARACTERISTICS (Vcc = 5.0V ± 10%)
SYMBOL PARAMETER
b
I
CC
I
CC
I
CC
I
CC
I
SB
I
SB
I
ILK
I
OLK
SRAM READ CYCLES #1 & SRAM READ
V
IH
V
IL
V
OH
V
OL
T
A
Note b: I
Note c: I
Note d:
Average Current 85
1
c
Average Current During STORE 6 7 mA All inputs Don’t Care
2
b
Average VCC Current at t
3
c
Average Current During
4
Cycle
d
Average Current
1
(Standby, Cycling TTL Input Levels)
d
Standby Current
2
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage 2.2 VCC+ .5 2.2 VCC + .5 V All inputs
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 -40 85 °C
and I
CC
1
and I
CC
2
E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
are the average currents required for the duration of the respective
CC
4
= 200ns
AVAV
AutoStore
™
COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX
95
80
75
15 15 mA
44mA
35
32
28
33mA
±1 ±1 µA
±5 ±5 µA
85
80
39
35
32
UNITS NOTES
t
= 25ns
AVAV
t
= 35ns
AVAV
t
= 45ns
AVAV
W ≥ (VCC– 0.2V)
All others cycling, CMOS levels
All inputs Don’t Care
t
= 25ns, E ≥ V
AVAV
t
= 35ns, E ≥ V
AVAV
t
= 45ns, E ≥ V
AVAV
E ≥ (VCC – 0.2V)
All others V
VCC= max
V
= VSS to V
IN
VCC= max
V
= VSSto VCC, E or G ≥ V
IN
=–4mA
OUT
= 8mA
OUT
).
STORE
STORE
mA
mA
mA
mA
mA
mA
cycles (t
IH
IH
IH
≤ 0.2V or ≥ (VCC – 0.2V)
IN
CC
IH
AC TEST CONDITIONS
Input pulse levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and output timing reference levels . . . . . . . . . . . . . . . . . 1.5V
Output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
CAPACITANCE
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
Note e: These parameters are guaranteed but not tested.
Input capacitance
Output capacitance
e
(TA = 25°C, f = 1.0MHz)
8pF
7pF
∆V = 0 to 3V
∆V = 0 to 3V
4-62
Output
255 Ohms
Figure 1: AC Output Loading
5.0V
480 Ohms
30pF
INCLUDING
SCOPE
AND FIXTURE
STK15C68
SRAM READ CYCLES #1 & #2 (V
NO.
10 t
11 t
#1, #2 Alt. MIN MAX MIN MAX MIN MAX
1t
ELQV
2t
AVAV
3t
AVQV
4t
GLQV
5t
AXQX
6t
ELQX
7t
EHQZ
8t
GLQX
9t
GHQZ
ELICCH
EHICCL
SYMBOLS
f
g
g
h
h
e
d, e
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time 25 35 45 ns
Read Cycle Time 25 35 45 ns
Address Access Time 25 35 45 ns
Output Enable to Data Valid 10 20 25 ns
Output Hold After Address Change 3 3 3 ns
Chip Enable to Output Active 5 5 5 ns
Chip Disable to Output Inactive 10 17 20 ns
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 10 17 20 ns
Chip Enable to Power Active 0 0 0 ns
Chip Disable to Power Standby 25 35 45 ns
PARAMETER
Note f: W must be high during SRAM read cycles and low during SRAM write cycles.
Note g: I/O state assumes
Note h: Measured
SRAM READ CYCLE #1 (Address Controlled)
E, G, < VIL and W > VIH; device is continuously selected
+ 200mV from steady state output voltage
f, g
STK15C68-25 STK15C68-35 STK15C68-45
= 5.0V ± 10%)
cc
UNITS
ADDRESS
5
t
AXQX
DQ(Data Out)
SRAM READ CYCLE #2 (E Controlled)
2
t
t
GLQV
AVAV
t
ELQV
4
ACTIVE
ADDRESS
DQ(Data Out)
I
CC
6
t
E
ELQX
G
8
t
GLQX
10
t
ELICCH
STANDBY
t
AVQV
f
1
t
3
2
AVAV
DATA VALID
DATA VALID
t
GHQZ
t
9
7
EHQZ
11
t
EHICCL
4-63
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