SIMTEK STK15C68-P45I, STK15C68-P35I, STK15C68-P45, STK15C68-P35, STK15C68-P25I Datasheet
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STK15C68
8K x 8
FEATURES
• Nonvolatile Storage Without Battery Problems
• Directly Replaces 8K x 8 static RAM, Battery
Backed RAM or EEPROM
• 25ns, 35ns and 45ns Access Times
• Store to EEPROM Initiated by Software or
AutoStore
• Recall to SRAM by Software or Power Restore
• 15mA I
• Unlimited Read, Write and Recall Cycles
• 1,000,000 Store Cycles to EEPROM
• 100 Year Data Retention Over Full Industrial
Temperature Range
• Commercial and Industrial Temp. Ranges
• 28 Pin 600 or 300 mil PDIP and 350 mil SOIC
™ on Power Down
at 200ns Cycle Time
CC
AutoStore
™ nvSRAM
High Performance CMOS
Nonvolatile Static RAM
DESCRIPTION
The STK15C68 is a fast SRAM with a nonvolatile
EEPROM element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent, nonvolatile data
resides in EEPROM. Data transfers from the SRAM to
EEPROM (the
STORE
matically on power down using charge stored in system
capacitance. Transfers from the EEPROM to the SRAM
(the
RECALL
operation) take place automatically on restoration of power. Initiation of STORE and RECALL
cycles can also be controlled by entering control
sequences on the SRAM inputs. The nvSRAM can be
used in place of existing 8K x 8 SRAMs and also matches
the pinout of 8k x 8 Battery Backed SRAMs, EPROMs,
and EEPROMs, allowing direct substitution while enhancing performance. There is no limit on the number of read
or write cycles that can be executed and no support circuitry is required for microprocessor interface.
operation) can take place auto-
BLOCK DIAGRAM
A
5
A
6
A
7
A
8
A
9
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
11
A
12
0
1
2
3
4
5
6
7
ROW DECODER
AA
INPUT BUFFERS
EEPROM ARRAY
128 x 512
STATIC RAM
ARRAY
128 x 512
COLUMN I/O
COLUMN DEC
A AA
2A1
43
STORE
RECALL
100
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
VCC
PIN CONFIGURATIONS
1
NC
2
A
12
3
A
7
A
4
6
5
A
5
6
A
4
7
3
821
A
2
9
A
1
10
A
0
11
DQ
0
12
DQ
1
DQ
13
A
0
A
12
2
V
14
SS
28 - 300 PDIP
28
V
27
W
NC
26
25
A
A
24
23
A
GA
22
A
E
20
19
DQ
18 DQ
DQ
17
DQ
16
DQ
15
CC
8
9
11
10
7
6
5
4
3
28 - 600 PDIP
28 - 350 SOIC
PIN NAMES
A0 - A
12
G
E
W
W Write Enable
DQ0 - DQ
E Chip Enable
G Output Enable
V
CC
V
SS
7
Address Inputs
Data In/Out
Power (+5V)
Ground
4-61
STK15C68
ABSOLUTE MAXIMUM RATINGS
a
Voltage on input relative to VSS. . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
0-7
Temperature under bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
Note a: Stresses greater than those listed under “Absolute Max-
mum Ratings” may cause permanent damage to the
device. This a stress rating only, and functional operation
of the device at conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC CHARACTERISTICS (Vcc = 5.0V ± 10%)
SYMBOL PARAMETER
b
I
CC
I
CC
I
CC
I
CC
I
SB
I
SB
I
ILK
I
OLK
SRAM READ CYCLES #1 & SRAM READ
V
IH
V
IL
V
OH
V
OL
T
A
Note b: I
Note c: I
Note d:
Average Current 85
1
c
Average Current During STORE 6 7 mA All inputs Don’t Care
2
b
Average VCC Current at t
3
c
Average Current During
4
Cycle
d
Average Current
1
(Standby, Cycling TTL Input Levels)
d
Standby Current
2
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage 2.2 VCC+ .5 2.2 VCC + .5 V All inputs
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 -40 85 °C
and I
CC
1
and I
CC
2
E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
are the average currents required for the duration of the respective
CC
4
= 200ns
AVAV
AutoStore
™
COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX
95
80
75
15 15 mA
44mA
35
32
28
33mA
±1 ±1 µA
±5 ±5 µA
85
80
39
35
32
UNITS NOTES
t
= 25ns
AVAV
t
= 35ns
AVAV
t
= 45ns
AVAV
W ≥ (VCC– 0.2V)
All others cycling, CMOS levels
All inputs Don’t Care
t
= 25ns, E ≥ V
AVAV
t
= 35ns, E ≥ V
AVAV
t
= 45ns, E ≥ V
AVAV
E ≥ (VCC – 0.2V)
All others V
VCC= max
V
= VSS to V
IN
VCC= max
V
= VSSto VCC, E or G ≥ V
IN
=–4mA
OUT
= 8mA
OUT
).
STORE
STORE
mA
mA
mA
mA
mA
mA
cycles (t
IH
IH
IH
≤ 0.2V or ≥ (VCC – 0.2V)
IN
CC
IH
AC TEST CONDITIONS
Input pulse levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and output timing reference levels . . . . . . . . . . . . . . . . . 1.5V
Output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
CAPACITANCE
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
Note e: These parameters are guaranteed but not tested.
Input capacitance
Output capacitance
e
(TA = 25°C, f = 1.0MHz)
8pF
7pF
∆V = 0 to 3V
∆V = 0 to 3V
4-62
Output
255 Ohms
Figure 1: AC Output Loading
5.0V
480 Ohms
30pF
INCLUDING
SCOPE
AND FIXTURE
STK15C68
SRAM READ CYCLES #1 & #2 (V
NO.
10 t
11 t
#1, #2 Alt. MIN MAX MIN MAX MIN MAX
1t
ELQV
2t
AVAV
3t
AVQV
4t
GLQV
5t
AXQX
6t
ELQX
7t
EHQZ
8t
GLQX
9t
GHQZ
ELICCH
EHICCL
SYMBOLS
f
g
g
h
h
e
d, e
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time 25 35 45 ns
Read Cycle Time 25 35 45 ns
Address Access Time 25 35 45 ns
Output Enable to Data Valid 10 20 25 ns
Output Hold After Address Change 3 3 3 ns
Chip Enable to Output Active 5 5 5 ns
Chip Disable to Output Inactive 10 17 20 ns
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 10 17 20 ns
Chip Enable to Power Active 0 0 0 ns
Chip Disable to Power Standby 25 35 45 ns
PARAMETER
Note f: W must be high during SRAM read cycles and low during SRAM write cycles.
Note g: I/O state assumes
Note h: Measured
SRAM READ CYCLE #1 (Address Controlled)
E, G, < VIL and W > VIH; device is continuously selected
+ 200mV from steady state output voltage
f, g
STK15C68-25 STK15C68-35 STK15C68-45
= 5.0V ± 10%)
cc
UNITS
ADDRESS
5
t
AXQX
DQ(Data Out)
SRAM READ CYCLE #2 (E Controlled)
2
t
t
GLQV
AVAV
t
ELQV
4
ACTIVE
ADDRESS
DQ(Data Out)
I
CC
6
t
E
ELQX
G
8
t
GLQX
10
t
ELICCH
STANDBY
t
AVQV
f
1
t
3
2
AVAV
DATA VALID
DATA VALID
t
GHQZ
t
9
7
EHQZ
11
t
EHICCL
4-63
STK15C68
SRAM WRITE CYCLES #1 & #2 (V
NO.
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
WLWH
DVWH
WHDX
WHAX
WLQZ
WHQX
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX
AVAV
ELWH
AVWH
AVWL
h, i
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
t
Write Cycle Time 25 35 45 ns
WC
t
Write Pulse Width 20 30 35 ns
WP
t
Chip Enable to End of Write 20 30 35 ns
CW
t
Data Set-up to End of Write 10 18 20 ns
DW
t
Data Hold After End of Write 0 0 0 ns
DH
t
Address Set-up to End of Write 20 30 35 ns
AW
t
Address Set-up to Start of Write 0 0 0 ns
AS
t
Address Hold After End of Write 0 0 0 ns
WR
t
Write Enable to Output Disable 10 17 20 ns
WZ
t
Output Active After End of Write 5 5 5 ns
OW
PARAMETER
Note i: If W is low when E goes low the outputs remain in the high impedance state.
Note j:
SRAM WRITE CYCLE #1: W CONTROLLED
E or W must be ≥ VIH during address transitions.
t
AVAV
j
12
ADDRESS
14
t
ELWH
E
STK15C68-25 STK15C68-35 STK15C68-45
19
t
WHAX
= 5.0V ± 10%)
cc
UNITS
17
t
DATA IN
DATA OUT
18
t
AVWL
W
PREVIOUS DATA
20
t
WLQZ
AVWH
13
t
WLWH
SRAM WRITE CYCLE #2: E CONTROLLED
12
t
ADDRESS
DATA IN
18
t
AVEL
E
17
t
AVEH
W
AVAV
t
ELEH
j
14
13
t
WLEH
15
t
DVWH
DATA VALID
HIGH IMPEDENCE
15
t
DVEH
DATA VALID
16
t
WHDX
19
t
EHAX
16
t
EHDX
21
t
WHQX
DATA OUT
HIGH IMPEDENCE
4-64
STK15C68
AutoStore
NO.
22 t
23 t
24 t
25 V
26 V
Note k: t
SYMBOLS
Standard MIN MAX
RESTORE
STORE
DELAY
SWITCH
RESET
RESTORE
AutoStore
V
25
V
SWITCH
26
V
RESET
™ / POWER-UP RECALL (Vcc = 5.0V ± 10%)
STK15C68
UNITS NOTES
Power Up RECALL Duration 550 µsk
STORE Cycle Duration 10 ms g
Time Allowed to Complete SRAM Cycle 1 µsg
Low Voltage Trigger Level 4.0 4.5 V
e
Low Voltage Reset Level 3.6 V
starts from the time VCC rises above V
SWITCH
PARAMETER
.
™ / POWER UP RECALL
CC
5V
AUTOSTORE
POWER UP RECALL
W
DQ
(Data Out)
TM
22
t
RESTORE
POWER-UP
RECALL
BROWN OUT
NO STORE DUE TO
NO SRAM WRITES
NO RECALL
(V
DID NOT GO
CC
BELOW V
RESET
)
24
t
DELAY
BROWN OUT
AutoStore
NO RECALL
(V
DID NOT GO
CC
BELOW V
™
RESET
23
t
STORE
BROWN OUT
AutoStore
™
RECALL WHEN
ABOVE V
SWITCH
)
4-65
STK15C68
SOFTWARE MODE SELECTION
E W GA
LHX
LHX
- A0 (hex) MODE I/O with G Low I/O with G High NOTES
12
0000
1555
0AAA
1FFF
10F0
0F0F
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
RECALL
Output data
Output data
Output data
Output data
Output data
Output high Z
Output data
Output data
Output data
Output data
Output data
Output high Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
Output High Z
l
l
Note l: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
SOFTWARE CYCLES #1 & #2
SYMBOLS
NO.
27 t
28 t
29 t
30 t
31 t
32 t
#1 MIN MAX MIN MAX MIN MAX
AVAV
ELQZ
m
AVEL
ELEH
g,m
ELAX
RECALL
g,m
m
STORE/RECALL
End of Sequence to Outputs Inactive 650 650 650 ns
Address Set-up Time 0 0 0 ns
Clock Pulse Width 20 25 30 ns
Address Hold Time 20 20 20 ns
Recall Cycle Duration 20 20 20 µs
PARAMETER
Initiation Cycle Time 25 35 45 ns
m,n
(VCC = 5.0V ± 10%)
STK15C68-25 STK15C68-35 STK15C68-45
UNITS
Note m: The software sequence is clocked with E controlled reads.
Note n: The six consecutive addresses must be in the order listed in the SOFTWARE MODE SELECTION Table - (0000, 1555, 0AAA, 1FFF, 10F0,
0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle.
W must be high during all six consecutive cycles.
SOFTWARE CYCLE: E CONTROLLED
t
ADDRESS
t
E
DQ(Data Out)
ADDRESS #1
3029
t
ELEHAVEL
t
ELAX
DATA VALID
31
4-66
2727
t
AVAVAVAV
ADDRESS #6
28
t
ELQZ
DATA VALID
t
STORE
3223
t
RECALL
HIGH IMPEDANCE
DEVICE OPERATION
STK15C68
The STK15C68 is a versatile memory chip that provides several modes of operation. The STK15C68
can operate as a standard 8K x 8
x 8
EEPROM shadow to which the SRAM information
can be copied, or from which the
SRAM. It has a 8K
SRAM can be
updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK15C68 is a high speed memory
and so must have a high frequency bypass capacitor of approximately 0.1µF connected between DUT
V
and VSS, using leads and traces that are as short
CC
as possible. As with all high speed CMOS ICs, normal careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK15C68 performs a READ cycle whenever E
and
G are low and W is high. The address specified
on pins A
bytes will be accessed. When the
determines which of the 8,192 data
0-12
READ is initiated
by an address transition, the outputs will be valid
after a delay of t
initiated by
at t
GLQV
E or G, the outputs will be valid at t
, whichever is later (READ CYCLE #2). The
(READ CYCLE #1). If the READ is
AVQV
ELQV
or
data outputs will repeatedly respond to address
changes within the t
AVQV access time without the
need for transitions on any control input pins, and will
remain valid until another address change or until
or
G is brought high or W is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the
until either
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a
W controlled WRITE or t
E controlled WRITE.
It is recommended that
entire
WRITE cycle to avoid data bus contention on
the common I/O lines. If
will turn off the output buffers t
WRITE cycle and must remain stable
E or W goes high at the end of the cycle.
will be writ-
0-7
before the end
DVWH
before the end of an
DVEH
G be kept high during the
G is left low, internal circuitry
after W goes low.
WLQZ
SOFTWARE NONVOLATILE STORE
The STK15C68 software STORE cycle is initiated by
executing sequential
address locations. During the
READ cycles from six specific
STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the
nonvolatile memory. Once a
SRAM data into
STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of reads from specific
addresses is used for
tant that no other
STORE initiation, it is impor-
READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no
To initiate the software
READ sequence must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0F (hex) Initiate STORE cycle
STORE or RECALL will take place.
STORE cycle, the following
The software sequence is clocked with E controlled
reads.
Once the sixth address in the sequence has been
entered, the
E
chip will be disabled. It is important that
and not
although it is not necessary that
sequence to be valid. After the t
been fulfilled, the
READ and WRITE operation.
STORE cycle will commence and the
WRITE cycles be used in the sequence,
G be low for the
cycle time has
STORE
SRAM will again be activated for
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of
READ operations in a manner similar to the soft-
ware
STORE initiation. To initiate the RECALL cycle,
the following sequence of
performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0E (hex) Initiate RECALL cycle
READ operations must be
READ cycles
4-67
STK15C68
Internally, RECALL is a two step procedure. First,
the
SRAM data is cleared and second, the nonvola-
tile information is transferred into the
After the t
be ready for
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled
cycle time the SRAM will once again
RECALL
READ and WRITE operations. The
SRAM cells.
an unlimited number of times.
AutoStore
TM
OPERATION
The STK15C68 uses the intrinsic system capacitance to perform an automatic store on power
down. As long as the system power supply takes at
least t
to decay from V
STORE
down to 3.6V the
SWITCH
STK15C68 will safely and automatically store the
SRAM data in EEPROM on power-down.
In order to prevent unneeded
automatic
one
most recent
ated
whether a
STORE will be ignored unless at least
WRITE operation has taken place since the
STORE or RECALL cycle. Software initi-
STORE cycles are performed regardless of
WRITE operation has taken place.
STORE operations,
POWER UP RECALL
During power up, or after any low power condition
(V
< V
CC
latched. When V
) an internal recall request will be
RESET
once again exceeds the sense
CC
voltage of V
be initiated and will take t
, a RECALL cycle will automatically
SWITCH
to complete.
RESTORE
HARDWARE PROTECT
The STK15C68 offers hardware protection against
inadvertent
conditions. When V
STORE operation during low voltage
< V
CC
Software STORE
SWITCH
operations will be inhibited.
LOW AVERAGE ACTIVE POWER
The STK15C68 draws significantly less current
when it is cycled at times longer than 55ns.
2
, below, shows the relationship between ICC and
READ cycle time. Worst case current consumption
is shown for both CMOS and TTL input levels (commercial temperature range, V
cycle on chip enable).
relationship for
WRITE cycles. If the chip enable
Figure 3
= 5.5V, 100% duty
CC
shows the same
duty cycle is less than 100%, only standby current
is drawn when the chip is disabled. The overall
average current drawn by the STK15C68 depends
on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall
cycle rate for accesses; 4) the ratio of
WRITE’s; 5) the operating temperature; 6) the VCC
level and; 7) I/O loading.
Figure
READ’s to
100
80
60
40
20
Average Active Current (ma)
0
100
50
Fig. 2 - Icc (max) Reads
TTL
CMOS
100
80
60
40
20
TTL
CMOS
Average Active Current (ma)
0
200150
50
100
200150
Cycle Time (ns)Cycle Time (ns)
Fig. 3 - Icc (Max) Writes
4-68
ORDERING INFORMATION
STK15C68
STK15C68
- W 25 I
Temperature Range
blank = Commercial (0 to 70 degrees C)
I = Industrial (–40 to 85 degrees C
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Package
W = Plastic 28 pin 600 mil DIP
P = Plastic 28 pin 300 mil DIP
S = Plastic 28 pin 350 mil SOIC
)
4-69
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