Datasheet STK14C88-W45I, STK14C88-W45, STK14C88-W35I, STK14C88-W35, STK14C88-W25I Datasheet (SIMTEK)
...
July 1999 5-21
PIN CONFIGUR ATIONS
V
CAP
A
14
A
12
A
7
A
6
A
5
A
4
A
3
NC
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
V
CCX
HSB
A
13
A
8
A
9
A
11
G
NC
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32 - 300 SOIC
32 - 600 PDIP
PIN NAMES
A0 - A
14
Address Inputs
DQ
0
-DQ7Data In/Out
E
Chip Enable
W
Write Enable
G
Output Enable
HSB
Hardware Store Busy (I/O)
V
CCX
Power (+ 5V)
V
CAP
Capacitor
V
SS
Ground
STK14C88
32K x 8 AutoStore™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• 20ns, 25ns, 35ns and 45ns Access Times
•“Hands-off” Automatic STORE with External
68µF Capacitor on Power Down
• STORE to EEPROM Initiated by Hardware,
Software or AutoStore™ on Power Down
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA T ypical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• Single 5V +
10% Operation
• Not Sensitive to Power On/Off Ramp Rates
• No Data Loss from Undershoot
• Commercial and Industrial Temperatures
• 32-Pin SOIC and DIP Packages
DESCRIPTION
The Simtek STK14C88 is a fast static RAM with a
nonvolatile, electrically erasable
PROM element
incorporated in each static memory cell. The
SRAM
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation) can take place
automatically on power down. A 68µF or larger
capacitor tied from V
CAP
to ground guarantees the
STORE operation, regardless of power-down slew
rate or loss of power from “hot swapping”. Transfers
from the
EEPROM to the SRAM (the RECALL opera-
tion) take place automatically on restoration of
power. Initiation of
STORE and RECALL cycles can
also be software controlled by entering specific read
sequences. A hardware
STORE may be initiated with
the HSB
pin.
BLOCK DIAGRAM
A0 A1 A2 A3 A4 A
10
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
512 x 512
ROW DECODER
INPUT BUFFERS
EEPROM ARRAY
512 x 512
STORE/
RECALL
CONTROL
STORE
RECALL
POWER
CONTROL
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
SOFTWARE
DETECT
G
E
W
HSB
V
CCXVCAP
A0 - A
13
STK14C88
July 1999 5-22
ABSOLUTE MAXIMUM RATINGS
a
Volt age on Input Relati ve to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V)
Volt age on DQ
0-7
or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sec tions of thi s
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
b, f
Note b: The STK14C88-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
CC
1
and I
CC
3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note d: I
CC
2
and I
CC
4
are the average currents required for the duration of the respective STORE cycles (t
STORE
).
Note e: E
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Note f: V
CC
reference levels throughout this datasheet refer to V
CCX
if that is where the power supply connection is made, or V
CAP
if V
CCX
is con-
nected to ground.
SYMBOL PARAMETER
COMMERCIAL INDUSTRIAL
UNITS NOTES
MIN MAX MIN MAX
I
CC
1
c
Average VCC Current 110
97
80
70
N/A
100
85
70
mA
mA
mA
mA
t
AVAV
= 20ns
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
I
CC
2
d
Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max
I
CC
3
c
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
10 10 mA
W
≥ (V
CC
– 0.2V)
All Others Cycling, CMOS Levels
I
CC
4
d
Average V
CAP
Current during
AutoStore™ Cycle
22mA
All Inputs Don’t Care
I
SB
1
e
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
35
30
25
22
N/A
31
26
23
mA
mA
mA
mA
t
AVAV
= 20ns, E ≥ V
IH
t
AVAV
= 25ns, E ≥ V
IH
t
AVAV
= 35ns, E ≥ V
IH
t
AVAV
= 45ns, E ≥ V
IH
I
SB
2
e
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
1.5 1.5 mA
E
≥ (VCC – 0.2V)
All Others V
IN
≤ 0.2V or ≥ (VCC – 0.2V)
I
ILK
Input Leakage Current
±1 ±1 µA
V
CC
= max
V
IN
= VSS to V
CC
I
OLK
Off-State Output Leakage Current
±5 ±5 µA
V
CC
= max
V
IN
= VSS to VCC, E or G ≥ VIH
V
IH
Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
V
IL
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
V
OH
Output Logic “1” Voltage 2.4 2.4 V I
OUT
= – 4mA except HSB
V
OL
Output Logic “0” Voltage 0.4 0.4 V I
OUT
= 8mA except HSB
V
BL
Logic “0” Voltage on HSB Output 0.4 0.4 V I
OUT
= 3mA
T
A
Operating Temperature 0 70 –40 85 °C
AC TEST CONDITIONS
CAPACIT ANCE
g
(TA = 25°C, f = 1.0MHz)
Note g: These parameters are guaranteed but not tested.
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
Input Capacitance 5 pF ∆V = 0 to 3V
C
OUT
Output Capacitance 7 pF ∆V = 0 to 3V
Figure 1: AC Output Loading
480 Ohms
30 pF
255 Ohms
5.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
STK14C88
July 1999 5-23
SRAM READ CYCLES #1 & #2 (VCC = 5.0V ±± 10%)
b,f
Note h: W and HSB must be high during SRAM READ cycles.
Note i: Device is continuously selected with E
and G both low.
Note j: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledh,
i
SRAM READ CYCLE #2: E Controlled
h
NO.
SYMBOLS
PARAMETER
STK14C88-20 STK14C88-25 STK14C88-35 STK14C88-45
UNITS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1t
ELQV
t
ACS
Chip Enable Access Time 20 25 35 45 ns
2t
AVAV
h
t
RC
Read Cycle Time 20 25 35 45 ns
3t
AVQV
i
t
AA
Address Access Time 22 25 35 45 ns
4t
GLQV
t
OE
Output Enable to Data Valid 8 10 15 20 n s
5t
AXQX
i
t
OH
Output Hold after Address Change 5 5 5 5 ns
6t
ELQX
t
LZ
Chip Enable to Output Active 5 5 5 5 ns
7t
EHQZ
j
t
HZ
Chip Disable to Output Inactive 7 10 13 15 ns
8t
GLQX
t
OLZ
Output Enable to Output Active 0 0 0 0 ns
9t
GHQZ
j
t
OHZ
Output Disable to Output Inactive 7 10 13 15 n s
10 t
ELICCH
g
t
PA
Chip Enable to Power Active 0 0 0 0 ns
11 t
EHICCL
g
t
PS
Chip Disable to Power Standby 25 25 35 45 ns
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
6
t
ELQX
STANDBY
DATA VALID
4
t
GLQV
DQ (DATA OUT)
E
ADDRESS
2
t
AVAV
G
I
CC
ACTIVE
10
t
ELICCH
11
t
EHICCL
7
t
EHQZ
8
t
GLQX
1
t
ELQV
9
t
GHQZ
STK14C88
July 1999 5-24
SRAM WRITE CYC LES #1 & #2 (VCC = 5.0V ± 10%)b,
f
Note k: If W is low when E goes low, the outputs remain in the high-impedance state.
Note l: E
or W must be ≥ V
IH
during address transitions.
Note m: HSB
must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlled
l, m
SRAM WRITE CYCLE #2: E Controlled
l, m
NO.
SYMBOLS
PARAMETER
STK14C88-20 STK14C88-25 STK14C88-35 STK14C88-45
UNITS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
12 t
AVAV
t
AVAV
t
WC
Write Cycle Time 20 25 35 45 n s
13 t
WLWH
t
WLEH
t
WP
Write Pulse Width 15202530 ns
14 t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write 15 20 25 30 ns
15 t
DVWH
t
DVEH
t
DW
Data Set-up to End of Write 8 10 12 15 ns
16 t
WHDX
t
EHDX
t
DH
Data Hold after End of Write 0 0 0 0 ns
17 t
AVWH
t
AVEH
t
AW
Address Set-up to End of Write 15 20 25 30 ns
18 t
AVWL
t
AVEL
t
AS
Address Set-up to Start of Write 0 0 0 0 ns
19 t
WHAX
t
EHAX
t
WR
Address Hold after End of Wr ite 0 0 0 0 ns
20 t
WLQZ
j, k
t
WZ
Write Enable to Output Disable 7 10 13 15 ns
21 t
WHQX
t
OW
Output Active after End of Write 5 5 5 5 ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
t
AVAV
W
16
t
WHDX
DATA IN
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVWH
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
DATA IN
12
t
AVAV
16
t
EHDX
13
t
WLEH
19
t
EHAX
18
t
AVEL
17
t
AVEH
DATA VALID
15
t
DVEH
HIGH IMPEDANCE
14
t
ELEH
DATA OUT
E
ADDRESS
W
DATA IN
STK14C88
July 1999 5-25
HARDWARE MODE SELECTION
Note n: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,
the part will go into standby mode, inhibiting all operations until HSB
rises.
Note o: The six consecutive addresses must be in the order listed. W
must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note p: While there are 15 addresses on the STK14C88, only the lower 14 are used to control software modes.
Note q: I/O state assumes G
< VIL. Activation of nonvolatile cycles does not depend on state of G.
HARDWARE STORE CYCLE (VCC = 5.0V ± 10%)b,
f
Note r: E and G low and W high for output behavior.
Note s: t
RECOVER
is only applicable after t
STORE
is complete.
HARDWARE STORE CYCLE
E W HSB A13 - A0 (hex) MODE I/O POWER NOTES
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active q
L L H X Write SRAM Input Data Active
X X L X Nonvolatile STORE Output High Z l
CC
2
n
LHH
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l
CC
2
o, p, q
LHH
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
o, p, q
NO.
SYMBOLS
PARAMETER
STK14C88
UNITS NOTES
Standard Alternate MIN MAX
22 t
STORE
t
HLHZ
STORE Cycle Duration 10 ms j, r
23 t
DELAY
t
HLQZ
Time Allowed to Complete SRAM Cycle 1 µsj, r
24 t
RECOVER
t
HHQX
Hardware STORE High to Inhibit Off 700 ns r, s
25 t
HLHX
Hardware STORE Pulse Width 15 ns
26 t
HLBL
Hardware STORE Low to STORE Busy 300 ns
DATA VALID
HSB (IN)
DATA VALID
25
t
HLHX
23
t
DELAY
22
t
STORE
24
t
RECOVER
HIGH IMPEDANCE
26
t
HLBL
HIGH IMPEDANCE
DQ (DATA OUT)
HSB (OUT)
STK14C88
July 1999 5-26
AutoStore™/POWER-UP RECALL (VCC = 5.0V ± 10%)b,
f
Note t: t
RESTORE
starts from the time VCC rises above V
SWITCH
.
Note u: HSB
is asserted low for 1µs when V
CAP
drops through V
SWITCH
. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB
will be released and no STORE will take place.
AutoStore™/POWER-UP RECALL
NO.
SYMBOLS
PARAMETER
STK14C88
UNITS NOTES
Standard Alternate MIN MAX
27 t
RESTORE
Power-up RECALL Duration 550 µst
28 t
STORE
t
HLHZ
STORE Cycle Duration 10 ms r, u
29 t
VSBL
Low Voltage Trigger (V
SWITCH
) to HSB Low 300 ns m
30 t
DELAY
t
BLQZ
Time Allowed to Complete SRAM Cycle 1 µsr
31 V
SWITCH
Low Voltage Trigger Level 4.0 4.5 V
32 V
RESET
Low Voltage Reset Level 3.9 V
30
t
DELAY
29
t
VSBL
POWER-UP
RECALL
BROWN OUT
NO STORE
(NO SRAM WRITES)
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore™
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore™
RECALL WHEN
V
CC
RETURNS
ABOVE V
SWITCH
AutoStore™
HSB
W
28
t
STORE
27
t
RESTORE
POWER-UP RECALL
31
V
SWITCH
32
V
RESET
V
CC
DQ (DATA OUT)
STK14C88
July 1999 5-27
SOFTW ARE-CONTROLLED STORE/RECALL CYCLE
w
(VCC = 5.0V ± 10%)b,
f
Note v: The software sequence is clocked with E controlled READs.
Note w: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for
a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W
must be high during all six consecutive cycles.
SOFTW ARE STORE/RECALL CYCLE: E CONTROLLED
w
NO.
SYMBOLS
PARAMETER
STK14C88-20 STK14C88-25 STK14C88-35 STK14C88-45
UNITS NOTES
Standard Alternate MIN MAX MIN MAX MIN MAX MIN MAX
33 t
AVAV
t
RC
STORE/RECALL Initiation Cycle Time 20 25 35 45 ns r
34 t
AVEL
t
AS
Address Set-up Time 0 0 0 0 ns v
35 t
ELEH
t
CW
Clock Pulse Width 15202530nsv
36 t
ELAX
Address Hold Time 15 20 20 20 ns v
37 t
RECALL
RECALL Duration 20 20 20 20 µs
DATA VALID
HIGH IMPEDANCE
ADDRESS #6ADDRESS #1
DATA VALID
33
t
AVAV
DATA VALID
DQ (DATA
E
ADDRESS
28 37
t
STORE
/ t
RECALL
33
t
AVAV
34
t
AVEL
35
t
ELEH
36
t
ELAX
STK14C88
July 1999 5-28
The STK14C88 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static
RAM. In nonvolatile mode, data is transferred
from
SRAM to EEPROM (the STORE operation) or
from
EEPROM to SRAM (the RECALL operation). In
this mode
SRAM functions are disabled.
NOISE CONSIDERATIONS
The STK14C88 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between V
CAP
and
V
SS
, using leads and traces that are as short as pos-
sible. As with all high-speed
CMOS ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK14C88 performs a READ cycle whenever E
and G are low and W and HSB are high. The
address specified on pins A
0-14
determines which of
the 32,768 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of t
AVQV
(READ cycle
#1). If the
READ is initiated by E or G, the outputs will
be valid at t
ELQV
or at t
GLQV
, whichever is later (READ
cycle #2). The data outputs will repeatedly respond
to address changes within the t
AVQV
access time without the need for transitions on any control input pins,
and will remain valid until another address change or
until E
or G is brought high, or W or H SB is brought
low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB
is high. The address inputs must be
stable prior to entering the
WRITE cycle and must
remain stable until either E
or W goes high at the
end of the cycle. The data on the common I/O pins
DQ
0-7
will be written into the memory if it is valid t
DVWH
before the end of a W controlled WRITE or t
DVEH
before the end of an E controlled WRITE.
It is recommended that G
be kept high during the
entire
WRITE cycle to avoid data bus contention on
common I/O lines. If G
is left low, internal circuitry
will turn off the output buffers t
WLQZ
after W goes low.
POWER-UP RECALL
During power up, or after any low-power condition
(V
CAP
< V
RESET
), an internal RECALL request will be
latched. When V
CAP
once again exceeds the sense
voltage of V
SWITCH
, a RECALL cycle will automatically
be initiated and will take t
RESTORE
to complete.
If the STK14C88 is in a
WRITE state at the end of
power-up
RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W
and system
V
CC
or between E and system VCC.
SOFTWARE NONVOLATILE STORE
The STK14C88 software STORE cycle is initiated by
executing sequential
E controlled R EAD cycles from
six specific address locations. During the
STORE
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile elements. The program operation copies the
SRAM data into nonvolatile memory. Once a STORE
cycle is initiated, further input and output are disabled until the cycle is completed.
Because a sequence of READs from specific
addresses is used for
STORE initiation, it is impor-
tant that no other
READ or WRITE accesses inter-
vene in the sequence, or the sequence will be
aborted and no
STORE or RECALL will take place.
To initiate the software
STORE cycle, the following
READ sequence must be performed:
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0FC0 (hex) Initiate STORE cycle
The software sequence must be clocked with E controlled
READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that
READ cycles
and not
WRITE cycles be used in the sequence,
although it is not necessary that G
be low for the
sequence to be valid. After the t
STORE
cycle time has
been fulfilled, the
SRAM will again be activated for
READ and WRITE operation.
DEVICE OPERATION
STK14C88
July 1999 5-29
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of
READ operations in a manner similar to the soft-
ware
STORE initiation. To initiate the RECALL cycle,
the following sequence of
E controlled READ opera-
tions must be performed:
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Vali d READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0C63 (hex) Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the
SRAM cells. After
the t
RECALL
cycle time the SRAM will once again be
ready for
READ and WRITE operations. The RECALL
operation in no way alters the data in the EEPROM
cells. The nonvolatile data can be recalled an unlimited number of times.
AutoStore™ OPERATION
The STK14C88 can be powered in one of three
modes.
During normal AutoStore™ operation, the
STK14C88 will draw current from V
CCX
to charge a
capacitor connected to the V
CAP
pin. This stored
charge will be used by the chip to perform a single
STORE operation. After power up, when the voltage
on the V
CAP
pin drops below V
SWITCH
, the part will
automatically disconnect the V
CAP
pin from V
CCX
and
initiate a
STORE operation.
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68µF and
220µF (± 20%) rated at 6V should be provided.
In system power mode (Figure 3), both V
CCX
and
V
CAP
are connected to the + 5V power supply without
the 68µF capacitor. In this mode the AutoStore™
function of the STK14C88 will operate on the stored
system charge as power goes down. The user must,
however, guarantee that V
CCX
does not drop below
3.6V during the 10ms
STORE cycle.
If an automatic
STORE on power loss is not required,
then V
CCX
can be tied to ground and + 5V applied to
V
CAP
(Figure 4). This is the AutoStore™ Inhibit
mode, in which the AutoStore™ function is disabled.
If the STK14C88 is operated in this configuration,
references to V
CCX
should be changed to V
CAP
throughout this data sheet. In this mode, STORE
operations may be triggered through software control or the HSB
pin. It is not permissable to change
between these three options “on the fly”.
In order to prevent unneeded STORE operations,
automatic
STOREs as well as those initiated by
externally driving HSB
low will be ignored unless at
least one
WRITE operation has taken place since the
most recent
STORE or RECALL cycle. Software-
initiated
STORE cycles are performed regardless of
whether a
WRITE operation has taken place. An
optional pull-up resistor is shown connected to HSB
.
This can be used to signal the system that the
AutoStore™ cycle is in progress.
Figure 2: AutoStore™ Mode
1
16
32
31
17
68µF
6v, ±20%
0.1µF
Bypass
30
+
10kΩ
10kΩ∗
Figure 3: System Power Mode
1
16
32
31
17
30
0.1µF
Bypass
10kΩ∗
10kΩ
Figure 4: AutoStore™
Inhibit Mode
1
16
32
31
17
0.1µF
Bypass
30
10kΩ∗
10kΩ
*If HSB is not used, it should be left unconnected.
STK14C88
July 1999 5-30
HSB OPERATION
The STK14C88 provides the HSB pin for controlling
and acknowledging the
STORE operations. T he HSB
pin can be used to request a hardware STORE cycle.
When the HSB
pin is driven low, the STK14C88 will
conditionally initiate a
STORE operation after t
DELAY
;
an actual
STORE cycle will only begin if a WRITE to
the
SRAM took place since the last STORE or
RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a
busy condition while the
STORE (initiated by any
means) is in progress.
SRAM READ and WRITE operations that are in
progress when HSB
is driven low by any means are
given time to complete before the
STORE operation
is initiated. After HSB
goes low, the STK14C88 will
continue
SRAM operations for t
DELAY
. During t
DELAY
,
multiple
SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low it will
be allowed a time, t
DELAY
, to complete. However, any
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB
returns high.
The HSB
pin can be used to synchronize multiple
STK14C88s while using a single larger capacitor. To
operate in this mode the HSB
pin should be con-
nected together to the HSB
pins from the other
STK14C88s. An external pull-up resistor to + 5V is
required since HSB
acts as an open drain pull down.
The V
CAP
pins from the other STK14C88 parts can
be tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
STK14C88s detects a power loss and asserts HSB
,
the common HSB
pin will cause all parts to request
a
STORE cycle (a STORE will take place in those
STK14C88s that have been written since the last
nonvolatile cycle).
During any
STORE operation, regardless of how it
was initiated, the STK14C88 will continue to drive
the HSB
pin low, releasing it only when the STORE is
complete. Upon completion of the
STORE operation
the STK14C88 will remain disabled until the HSB
pin returns high.
If HSB
is not used, it should be left unconnected.
PREVENTING STORES
The STORE function can be disabled on the fly by
holding HSB
high with a driver capable of sourcing
30mA at a V
OH
of at least 2.2V, as it will have to
overpower the internal pull-down device that drives
HSB
low for 20µs at the onset of a STORE. When
the STK14C88 is connected for AutoStore™ operation (system V
CC
connected to V
CCX
and a 68µF
capacitor on V
CAP
) and VCC crosses V
SWITCH
on the
way down, the STK14C88 will attempt to pull HSB
low; if HSB doesn’t actually get below VIL, the part
will stop trying to pull HSB
low and abort the STORE
attempt.
HARDWARE PROTECT
The STK14C88 offers hardware protection against
inadvertent
STORE operation and SRAM WRITEs dur-
ing low-voltage conditions. When V
CAP
< V
SWITCH
, all
externally initiated
STORE operations and SRAM
WRITEs will be inhibited.
AutoStore™ can be completely disabled by tying
V
CCX
to ground and applying + 5V to V
CAP
. This is the
AutoStore™
Inhibit mode; in this mode STOREs are
only initiated by explicit request using either the software sequence or the HSB
pin.
LOW AVERAGE ACTIVE POWER
The STK14C88 draws significantly less current
when it is cycled at times longer than 50ns. Figure 5
shows the relationship between I
CC
and READ cycle
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
perature range, V
CC
= 5.5V, 100% duty cycle on chip
enable). Figure 6 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK14C88 depends on the following items:
1)
CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of
READs to WRITEs; 5) the operating
temperature; 6) the V
cc
level; and 7) I/O loading.
STK14C88
July 1999 5-31
Figure 5: Icc (max) Reads
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
Figure 6: Icc (max) Writes
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
STK14C88
July 1999 5-32
ORDERING INFORM ATION
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (-40 to 85°C)
Access Time
20 = 20ns (Commercial only)
25 = 25ns
35 = 35ns
45 = 45ns
Package
N = Plastic 32-pin 300 mil SOIC
W = Plastic 32-pin 600 mil DIP
STK14C88 - N 45 I
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