SIMTEK STK14C88-W45I, STK14C88-W45, STK14C88-W35I, STK14C88-W35, STK14C88-W25I Datasheet
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July 1999 5-21
PIN CONFIGUR ATIONS
V
CAP
A
14
A
12
A
7
A
6
A
5
A
4
A
3
NC
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
V
CCX
HSB
A
13
A
8
A
9
A
11
G
NC
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32 - 300 SOIC
32 - 600 PDIP
PIN NAMES
A0 - A
14
Address Inputs
DQ
0
-DQ7Data In/Out
E
Chip Enable
W
Write Enable
G
Output Enable
HSB
Hardware Store Busy (I/O)
V
CCX
Power (+ 5V)
V
CAP
Capacitor
V
SS
Ground
STK14C88
32K x 8 AutoStore™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• 20ns, 25ns, 35ns and 45ns Access Times
•“Hands-off” Automatic STORE with External
68µF Capacitor on Power Down
• STORE to EEPROM Initiated by Hardware,
Software or AutoStore™ on Power Down
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA T ypical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• Single 5V +
10% Operation
• Not Sensitive to Power On/Off Ramp Rates
• No Data Loss from Undershoot
• Commercial and Industrial Temperatures
• 32-Pin SOIC and DIP Packages
DESCRIPTION
The Simtek STK14C88 is a fast static RAM with a
nonvolatile, electrically erasable
PROM element
incorporated in each static memory cell. The
SRAM
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation) can take place
automatically on power down. A 68µF or larger
capacitor tied from V
CAP
to ground guarantees the
STORE operation, regardless of power-down slew
rate or loss of power from “hot swapping”. Transfers
from the
EEPROM to the SRAM (the RECALL opera-
tion) take place automatically on restoration of
power. Initiation of
STORE and RECALL cycles can
also be software controlled by entering specific read
sequences. A hardware
STORE may be initiated with
the HSB
pin.
BLOCK DIAGRAM
A0 A1 A2 A3 A4 A
10
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
512 x 512
ROW DECODER
INPUT BUFFERS
EEPROM ARRAY
512 x 512
STORE/
RECALL
CONTROL
STORE
RECALL
POWER
CONTROL
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
SOFTWARE
DETECT
G
E
W
HSB
V
CCXVCAP
A0 - A
13
STK14C88
July 1999 5-22
ABSOLUTE MAXIMUM RATINGS
a
Volt age on Input Relati ve to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V)
Volt age on DQ
0-7
or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sec tions of thi s
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
b, f
Note b: The STK14C88-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
CC
1
and I
CC
3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note d: I
CC
2
and I
CC
4
are the average currents required for the duration of the respective STORE cycles (t
STORE
).
Note e: E
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Note f: V
CC
reference levels throughout this datasheet refer to V
CCX
if that is where the power supply connection is made, or V
CAP
if V
CCX
is con-
nected to ground.
SYMBOL PARAMETER
COMMERCIAL INDUSTRIAL
UNITS NOTES
MIN MAX MIN MAX
I
CC
1
c
Average VCC Current 110
97
80
70
N/A
100
85
70
mA
mA
mA
mA
t
AVAV
= 20ns
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
I
CC
2
d
Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max
I
CC
3
c
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
10 10 mA
W
≥ (V
CC
– 0.2V)
All Others Cycling, CMOS Levels
I
CC
4
d
Average V
CAP
Current during
AutoStore™ Cycle
22mA
All Inputs Don’t Care
I
SB
1
e
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
35
30
25
22
N/A
31
26
23
mA
mA
mA
mA
t
AVAV
= 20ns, E ≥ V
IH
t
AVAV
= 25ns, E ≥ V
IH
t
AVAV
= 35ns, E ≥ V
IH
t
AVAV
= 45ns, E ≥ V
IH
I
SB
2
e
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
1.5 1.5 mA
E
≥ (VCC – 0.2V)
All Others V
IN
≤ 0.2V or ≥ (VCC – 0.2V)
I
ILK
Input Leakage Current
±1 ±1 µA
V
CC
= max
V
IN
= VSS to V
CC
I
OLK
Off-State Output Leakage Current
±5 ±5 µA
V
CC
= max
V
IN
= VSS to VCC, E or G ≥ VIH
V
IH
Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
V
IL
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
V
OH
Output Logic “1” Voltage 2.4 2.4 V I
OUT
= – 4mA except HSB
V
OL
Output Logic “0” Voltage 0.4 0.4 V I
OUT
= 8mA except HSB
V
BL
Logic “0” Voltage on HSB Output 0.4 0.4 V I
OUT
= 3mA
T
A
Operating Temperature 0 70 –40 85 °C
AC TEST CONDITIONS
CAPACIT ANCE
g
(TA = 25°C, f = 1.0MHz)
Note g: These parameters are guaranteed but not tested.
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
Input Capacitance 5 pF ∆V = 0 to 3V
C
OUT
Output Capacitance 7 pF ∆V = 0 to 3V
Figure 1: AC Output Loading
480 Ohms
30 pF
255 Ohms
5.0V
INCLUDING
SCOPE AND
OUTPUT
FIXTURE
STK14C88
July 1999 5-23
SRAM READ CYCLES #1 & #2 (VCC = 5.0V ±± 10%)
b,f
Note h: W and HSB must be high during SRAM READ cycles.
Note i: Device is continuously selected with E
and G both low.
Note j: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledh,
i
SRAM READ CYCLE #2: E Controlled
h
NO.
SYMBOLS
PARAMETER
STK14C88-20 STK14C88-25 STK14C88-35 STK14C88-45
UNITS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1t
ELQV
t
ACS
Chip Enable Access Time 20 25 35 45 ns
2t
AVAV
h
t
RC
Read Cycle Time 20 25 35 45 ns
3t
AVQV
i
t
AA
Address Access Time 22 25 35 45 ns
4t
GLQV
t
OE
Output Enable to Data Valid 8 10 15 20 n s
5t
AXQX
i
t
OH
Output Hold after Address Change 5 5 5 5 ns
6t
ELQX
t
LZ
Chip Enable to Output Active 5 5 5 5 ns
7t
EHQZ
j
t
HZ
Chip Disable to Output Inactive 7 10 13 15 ns
8t
GLQX
t
OLZ
Output Enable to Output Active 0 0 0 0 ns
9t
GHQZ
j
t
OHZ
Output Disable to Output Inactive 7 10 13 15 n s
10 t
ELICCH
g
t
PA
Chip Enable to Power Active 0 0 0 0 ns
11 t
EHICCL
g
t
PS
Chip Disable to Power Standby 25 25 35 45 ns
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
6
t
ELQX
STANDBY
DATA VALID
4
t
GLQV
DQ (DATA OUT)
E
ADDRESS
2
t
AVAV
G
I
CC
ACTIVE
10
t
ELICCH
11
t
EHICCL
7
t
EHQZ
8
t
GLQX
1
t
ELQV
9
t
GHQZ
STK14C88
July 1999 5-24
SRAM WRITE CYC LES #1 & #2 (VCC = 5.0V ± 10%)b,
f
Note k: If W is low when E goes low, the outputs remain in the high-impedance state.
Note l: E
or W must be ≥ V
IH
during address transitions.
Note m: HSB
must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlled
l, m
SRAM WRITE CYCLE #2: E Controlled
l, m
NO.
SYMBOLS
PARAMETER
STK14C88-20 STK14C88-25 STK14C88-35 STK14C88-45
UNITS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
12 t
AVAV
t
AVAV
t
WC
Write Cycle Time 20 25 35 45 n s
13 t
WLWH
t
WLEH
t
WP
Write Pulse Width 15202530 ns
14 t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write 15 20 25 30 ns
15 t
DVWH
t
DVEH
t
DW
Data Set-up to End of Write 8 10 12 15 ns
16 t
WHDX
t
EHDX
t
DH
Data Hold after End of Write 0 0 0 0 ns
17 t
AVWH
t
AVEH
t
AW
Address Set-up to End of Write 15 20 25 30 ns
18 t
AVWL
t
AVEL
t
AS
Address Set-up to Start of Write 0 0 0 0 ns
19 t
WHAX
t
EHAX
t
WR
Address Hold after End of Wr ite 0 0 0 0 ns
20 t
WLQZ
j, k
t
WZ
Write Enable to Output Disable 7 10 13 15 ns
21 t
WHQX
t
OW
Output Active after End of Write 5 5 5 5 ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
t
AVAV
W
16
t
WHDX
DATA IN
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVWH
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
DATA IN
12
t
AVAV
16
t
EHDX
13
t
WLEH
19
t
EHAX
18
t
AVEL
17
t
AVEH
DATA VALID
15
t
DVEH
HIGH IMPEDANCE
14
t
ELEH
DATA OUT
E
ADDRESS
W
DATA IN
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