SIMTEK STK14C88-5L45M, STK14C88-5K45M, STK14C88-5L35M, STK14C88-5K35M, STK14C88-5C45M Datasheet
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STK14C88-M
32K x 8
FEATURES
• Nonvolatile Storage without Battery Problems
• 35ns and 45ns Access Times
STORE
• “Hands-off” Automatic
68µF Capacitor on Power Down
STORE
•
•
to EEPROM Initiated by Hardware,
Software or
RECALL
AutoStore
™ on Power Down
to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
at 200ns Cycle Time
CC
• Unlimited READ, WRITE and
STORE
• 100,000
Cycles to EEPROM
• 10-Year Data Retention in EEPROM
• Single 5V
+ 10% Operation
• Not Sensitive to Power On/Off Ramp Rates
• No Data Loss from Undershoot
• 32-Pad LCC and 32-Pin 300 mil CDIP Packages
with External
RECALL
Cycles
AutoStore
QuantumTrap
™ nvSRAM
™ CMOS
Nonvolatile Static RAM
MIL-STD-883
DESCRIPTION
The Simtek STK14C88-M is a fast static RAM with a
nonvolatile, electrically erasable
incorporated in each static memory cell. The
can be read and written an unlimited number of
times, while independent nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the
STORE
operation) cantake place automatically on power down. A 68µF or larger capacitor
tied from V
to ground guarantees the
CAP
operation, regardless of power-down slew rate or
loss of power from “hot swapping”. Transfers from
the
EEPROM to the SRAM (the
take place automatically on restoration of power. Initiation of
STORE
and
RECALL
software controlled by entering specific read
sequences. A hardware
the
HSB pin.
STORE
PROM element
SRAM
STORE
RECALL
operation)
cycles can also be
may be initiated with
BLOCK DIAGRAM
V
CCXVCAP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
EEPROM ARRAY
ARRAY
512 x 512
STORE
RECALL
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
0
1
2
3
4
5
6
7
STATIC RAM
ROW DECODER
COLUMN I/O
COLUMN DEC
A0A1 A2 A3 A4 A
INPUT BUFFERS
512 x 512
POWER
CONTROL
STORE/
RECALL
CONTROL
April 1999 5-43
SOFTWARE
DETECT
HSB
A0- A
G
E
W
PIN CONFIGURATIONS
V
V
CAP
A
14
A
12
A
A
A
A
A
NC
A
A
A
DQ
DQ
V
SS
PIN NAMES
13
A0 - A
DQ
E Chip Enable
W Write Enable
G Output Enable
HSB Hardware Store Busy (I/O)
V
V
V
32
1
HSB
31
2
30
W
3
29
4
7
6
5
4
3
2
1
0
0
1
2
0
CCX
CAP
SS
A
5
A
28
6
27
A
7
A
26
G
8
25
9
24
NC
A
10
23
11
E
22
21
32 300 mil DIP
20DQ
19
18
17
14
DQ
DQ
DQ
DQ
DQ
Address Inputs
12
13
14
15
16
-DQ7Data In/Out
Power (+ 5V)
Capacitor
Ground
CCX
7
ADQ
4
13
5
A
6
8
6
A
5
9
7
A
4
11
8
A
9
NC
10
A
2
10
11
A
1
12
A
0
7
13
DQ
0
14
6
5
4
3
14
12
A
A
3
2
32
LCC
15
16
2
1303
SS
V
DQ
CCX
CAP
V
W
V
HSB
32
31
1
29
A
13
28
A
8
27
A
9
26
A
113
25
G
24
NC
23
A
10
22
E
21
DQ
7
18
20
17
19
4
6
5
DQ
DQ
DQ
DQ
STK14C88-M
ABSOLUTE MAXIMUM RATINGS
Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V)
Voltage on DQ
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)
0-7
a
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
SYMBOL PARAMETER
b
I
I
I
I
I
I
I
I
V
V
V
V
V
T
Note b: I
Note c: I
Note d:
Note e: V
Average VCC Current 90
CC
1
c
Average VCC Current during
CC
2
b
Average VCCCurrent at t
CC
3
c
Average V
CC
4
Cycle
d
Average VCCCurrent
SB
1
(Standby, Cycling TTL Input Levels)
d
VCCStandby Current
SB
2
(Standby, Stable CMOS Input Levels)
Input Leakage Current
ILK
Off-State Output Leakage Current
OLK
Input Logic “1” Voltage 2.2 VCC + .5 V All Inputs
IH
Input Logic “0” Voltage VSS – .5 0.8 V All Inputs
IL
Output Logic “1” Voltage 2.4 V I
OH
Output Logic “0” Voltage 0.4 V I
OL
Logic “0” Voltage onHSB Output 0.4 V I
BL
Operating Temperature –55 125 °C
A
and I
CC
1
and I
CC
2
E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
reference levels throughout this datasheet refer to V
CC
nected to ground.
Current during
CAP
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
are the average currents required for the duration of the respective
CC
4
AVAV
STORE
= 200ns
AutoStore
™
MILITARY
MIN MAX
85
15 mA
30
28
±1 µA
±5 µA
if that is where the power supply connection is made, or V
CCX
UNITS NOTES
mA
mA
6 mA All Inputs Don’t Care, VCC= max
4mA
mA
mA
3mA
t
= 35ns
AVAV
t
= 45ns
AVAV
W ≥ (VCC– 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
t
= 35ns, E ≥ V
AVAV
t
= 45ns, E ≥ V
AVAV
E ≥ (VCC– 0.2V)
All Others V
VCC= max
V
= VSS to V
IN
VCC= max
V
= VSS to VCC, E or G ≥ V
IN
=– 4mA except HSB
OUT
= 8mA except HSB
OUT
= 3mA
OUT
STORE
cycles (t
STORE
IH
IH
≤ 0.2V or ≥ (VCC – 0.2V)
IN
CC
IH
).
CAP
if V
CCX
is con-
e
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . . .1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCE
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
f
(TA = 25°C, f = 1.0MHz)
Input Capacitance 5 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V
Note f: These parameters are guaranteed but not tested.
April 1999 5-44
OUTPUT
5.0V
480 Ohms
30 pF
255 Ohms
INCLUDING
SCOPE
AND FIXTURE
Figure 1: AC Output Loading
STK14C88-M
SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)
NO.
1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with
Note i: Measured ± 200mV from steady state output voltage.
SYMBOLS
#1, #2 Alt. MIN MAX MIN MAX
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
t
g
h
h
i
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time 35 45 ns
Read Cycle Time 35 45 ns
Address Access Time 35 45 ns
Output Enable to Data Valid 15 20 ns
Output Hold after Address Change 3 3 ns
Chip Enable to Output Active 5 5 ns
Chip Disable to Output Inactive 13 15 ns
Output Enable to Output Active 0 0 ns
Output Disable to Output Inactive 13 15 ns
Chip Enable to Power Active 0 0 ns
Chip Disable to Power Standby 35 45 ns
PARAMETER
E and G both low.
SRAM READ CYCLE #1: Address Controlled
2
t
t
AVQV
AVAV
3
ADDRESS
DQ (DATA OUT)
t
AXQX
5
g, h
STK14C88-35M STK14C88-45M
DATA VALID
UNITS
e
t
g
AVAV
t
ELQV
2
1
SRAM READ CYCLE #2: E Controlled
ADDRESS
E
t
ELQX
6
G
4
t
GLQV
8
t
GLQX
DQ (DATA OUT)
10
t
ELICCH
I
CC
STANDBY
ACTIVE
April 1999 5-45
DATA VALID
t
GHQZ
11
t
EHICCL
7
t
EHQZ
9
STK14C88-M
SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V ± 10%)
NO.
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be ≥ VIHduring address transitions.
Note k:
HSB must be high during SRAM WRITE cycles.
Note l:
SRAM WRITE CYCLE #1: W Controlled
ADDRESS
DATA IN
DATA OUT
SRAM WRITE CYCLE #2: E Controlled
ADDRESS
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX
AVAV
WLWH
ELWH
DVWH
WHDX
AVWH
AVWL
WHAX
WLQZ
WHQX
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
i, j
t
Write Cycle Time 35 45 ns
WC
t
Write Pulse Width 25 30 ns
WP
t
Chip Enable to End of Write 25 30 ns
CW
t
Data Set-up to End of Write 12 15 ns
DW
t
Data Hold after End of Write 0 0 ns
DH
t
Address Set-up to End of Write 25 30 ns
AW
t
Address Set-up to Start of Write 0 0 ns
AS
t
Address Hold after End of Write 0 0 ns
WR
t
Write Enable to Output Disable 13 15 ns
WZ
t
Output Active after End of Write 5 5 ns
OW
PARAMETER
k, l
12
t
AVAV
14
t
t
AVWH
ELWH
17
13
t
WLWH
t
DVWH
HIGH IMPEDANCE
E
18
t
AVWL
W
20
t
WLQZ
PREVIOUS DATA
k, l
12
t
AVAV
t
AVEL
18
t
14
ELEH
E
15
STK14C88-35M STK14C88-45M
19
t
WHAX
16
t
DATA VALID
WHDX
t
19
EHAX
21
t
WHQX
UNITS
e
17
t
AVEH
W
t
WLEH
13
DATA IN
DATA OUT
HIGH IMPEDANCE
April 1999 5-46
t
DVEH
15
DATA VALID
t
EHDX
16
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