SIMTEK STK14C88-5L45M, STK14C88-5K45M, STK14C88-5L35M, STK14C88-5K35M, STK14C88-5C45M Datasheet
...
STK14C88-M
32K x 8
FEATURES
• Nonvolatile Storage without Battery Problems
• 35ns and 45ns Access Times
STORE
• “Hands-off” Automatic
68µF Capacitor on Power Down
STORE
•
•
to EEPROM Initiated by Hardware,
Software or
RECALL
AutoStore
™ on Power Down
to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
at 200ns Cycle Time
CC
• Unlimited READ, WRITE and
STORE
• 100,000
Cycles to EEPROM
• 10-Year Data Retention in EEPROM
• Single 5V
+ 10% Operation
• Not Sensitive to Power On/Off Ramp Rates
• No Data Loss from Undershoot
• 32-Pad LCC and 32-Pin 300 mil CDIP Packages
with External
RECALL
Cycles
AutoStore
QuantumTrap
™ nvSRAM
™ CMOS
Nonvolatile Static RAM
MIL-STD-883
DESCRIPTION
The Simtek STK14C88-M is a fast static RAM with a
nonvolatile, electrically erasable
incorporated in each static memory cell. The
can be read and written an unlimited number of
times, while independent nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the
STORE
operation) cantake place automatically on power down. A 68µF or larger capacitor
tied from V
to ground guarantees the
CAP
operation, regardless of power-down slew rate or
loss of power from “hot swapping”. Transfers from
the
EEPROM to the SRAM (the
take place automatically on restoration of power. Initiation of
STORE
and
RECALL
software controlled by entering specific read
sequences. A hardware
the
HSB pin.
STORE
PROM element
SRAM
STORE
RECALL
operation)
cycles can also be
may be initiated with
BLOCK DIAGRAM
V
CCXVCAP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
EEPROM ARRAY
ARRAY
512 x 512
STORE
RECALL
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
0
1
2
3
4
5
6
7
STATIC RAM
ROW DECODER
COLUMN I/O
COLUMN DEC
A0A1 A2 A3 A4 A
INPUT BUFFERS
512 x 512
POWER
CONTROL
STORE/
RECALL
CONTROL
April 1999 5-43
SOFTWARE
DETECT
HSB
A0- A
G
E
W
PIN CONFIGURATIONS
V
V
CAP
A
14
A
12
A
A
A
A
A
NC
A
A
A
DQ
DQ
V
SS
PIN NAMES
13
A0 - A
DQ
E Chip Enable
W Write Enable
G Output Enable
HSB Hardware Store Busy (I/O)
V
V
V
32
1
HSB
31
2
30
W
3
29
4
7
6
5
4
3
2
1
0
0
1
2
0
CCX
CAP
SS
A
5
A
28
6
27
A
7
A
26
G
8
25
9
24
NC
A
10
23
11
E
22
21
32 300 mil DIP
20DQ
19
18
17
14
DQ
DQ
DQ
DQ
DQ
Address Inputs
12
13
14
15
16
-DQ7Data In/Out
Power (+ 5V)
Capacitor
Ground
CCX
7
ADQ
4
13
5
A
6
8
6
A
5
9
7
A
4
11
8
A
9
NC
10
A
2
10
11
A
1
12
A
0
7
13
DQ
0
14
6
5
4
3
14
12
A
A
3
2
32
LCC
15
16
2
1303
SS
V
DQ
CCX
CAP
V
W
V
HSB
32
31
1
29
A
13
28
A
8
27
A
9
26
A
113
25
G
24
NC
23
A
10
22
E
21
DQ
7
18
20
17
19
4
6
5
DQ
DQ
DQ
DQ
STK14C88-M
ABSOLUTE MAXIMUM RATINGS
Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V)
Voltage on DQ
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)
0-7
a
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
SYMBOL PARAMETER
b
I
I
I
I
I
I
I
I
V
V
V
V
V
T
Note b: I
Note c: I
Note d:
Note e: V
Average VCC Current 90
CC
1
c
Average VCC Current during
CC
2
b
Average VCCCurrent at t
CC
3
c
Average V
CC
4
Cycle
d
Average VCCCurrent
SB
1
(Standby, Cycling TTL Input Levels)
d
VCCStandby Current
SB
2
(Standby, Stable CMOS Input Levels)
Input Leakage Current
ILK
Off-State Output Leakage Current
OLK
Input Logic “1” Voltage 2.2 VCC + .5 V All Inputs
IH
Input Logic “0” Voltage VSS – .5 0.8 V All Inputs
IL
Output Logic “1” Voltage 2.4 V I
OH
Output Logic “0” Voltage 0.4 V I
OL
Logic “0” Voltage onHSB Output 0.4 V I
BL
Operating Temperature –55 125 °C
A
and I
CC
1
and I
CC
2
E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
reference levels throughout this datasheet refer to V
CC
nected to ground.
Current during
CAP
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
are the average currents required for the duration of the respective
CC
4
AVAV
STORE
= 200ns
AutoStore
™
MILITARY
MIN MAX
85
15 mA
30
28
±1 µA
±5 µA
if that is where the power supply connection is made, or V
CCX
UNITS NOTES
mA
mA
6 mA All Inputs Don’t Care, VCC= max
4mA
mA
mA
3mA
t
= 35ns
AVAV
t
= 45ns
AVAV
W ≥ (VCC– 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
t
= 35ns, E ≥ V
AVAV
t
= 45ns, E ≥ V
AVAV
E ≥ (VCC– 0.2V)
All Others V
VCC= max
V
= VSS to V
IN
VCC= max
V
= VSS to VCC, E or G ≥ V
IN
=– 4mA except HSB
OUT
= 8mA except HSB
OUT
= 3mA
OUT
STORE
cycles (t
STORE
IH
IH
≤ 0.2V or ≥ (VCC – 0.2V)
IN
CC
IH
).
CAP
if V
CCX
is con-
e
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . . .1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCE
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
f
(TA = 25°C, f = 1.0MHz)
Input Capacitance 5 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V
Note f: These parameters are guaranteed but not tested.
April 1999 5-44
OUTPUT
5.0V
480 Ohms
30 pF
255 Ohms
INCLUDING
SCOPE
AND FIXTURE
Figure 1: AC Output Loading
STK14C88-M
SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)
NO.
1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with
Note i: Measured ± 200mV from steady state output voltage.
SYMBOLS
#1, #2 Alt. MIN MAX MIN MAX
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
t
g
h
h
i
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time 35 45 ns
Read Cycle Time 35 45 ns
Address Access Time 35 45 ns
Output Enable to Data Valid 15 20 ns
Output Hold after Address Change 3 3 ns
Chip Enable to Output Active 5 5 ns
Chip Disable to Output Inactive 13 15 ns
Output Enable to Output Active 0 0 ns
Output Disable to Output Inactive 13 15 ns
Chip Enable to Power Active 0 0 ns
Chip Disable to Power Standby 35 45 ns
PARAMETER
E and G both low.
SRAM READ CYCLE #1: Address Controlled
2
t
t
AVQV
AVAV
3
ADDRESS
DQ (DATA OUT)
t
AXQX
5
g, h
STK14C88-35M STK14C88-45M
DATA VALID
UNITS
e
t
g
AVAV
t
ELQV
2
1
SRAM READ CYCLE #2: E Controlled
ADDRESS
E
t
ELQX
6
G
4
t
GLQV
8
t
GLQX
DQ (DATA OUT)
10
t
ELICCH
I
CC
STANDBY
ACTIVE
April 1999 5-45
DATA VALID
t
GHQZ
11
t
EHICCL
7
t
EHQZ
9
STK14C88-M
SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V ± 10%)
NO.
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be ≥ VIHduring address transitions.
Note k:
HSB must be high during SRAM WRITE cycles.
Note l:
SRAM WRITE CYCLE #1: W Controlled
ADDRESS
DATA IN
DATA OUT
SRAM WRITE CYCLE #2: E Controlled
ADDRESS
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX
AVAV
WLWH
ELWH
DVWH
WHDX
AVWH
AVWL
WHAX
WLQZ
WHQX
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
i, j
t
Write Cycle Time 35 45 ns
WC
t
Write Pulse Width 25 30 ns
WP
t
Chip Enable to End of Write 25 30 ns
CW
t
Data Set-up to End of Write 12 15 ns
DW
t
Data Hold after End of Write 0 0 ns
DH
t
Address Set-up to End of Write 25 30 ns
AW
t
Address Set-up to Start of Write 0 0 ns
AS
t
Address Hold after End of Write 0 0 ns
WR
t
Write Enable to Output Disable 13 15 ns
WZ
t
Output Active after End of Write 5 5 ns
OW
PARAMETER
k, l
12
t
AVAV
14
t
t
AVWH
ELWH
17
13
t
WLWH
t
DVWH
HIGH IMPEDANCE
E
18
t
AVWL
W
20
t
WLQZ
PREVIOUS DATA
k, l
12
t
AVAV
t
AVEL
18
t
14
ELEH
E
15
STK14C88-35M STK14C88-45M
19
t
WHAX
16
t
DATA VALID
WHDX
t
19
EHAX
21
t
WHQX
UNITS
e
17
t
AVEH
W
t
WLEH
13
DATA IN
DATA OUT
HIGH IMPEDANCE
April 1999 5-46
t
DVEH
15
DATA VALID
t
EHDX
16
STK14C88-M
HARDWARE MODE SELECTION
E W HSB A13 - A0 (hex) MODE I/O POWER NOTES
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active p
L L H X Write SRAM Input Data Active
X X L X Nonvolatile
0E38
31C7
LHH
LHH
Note m: HSB store operation occurs only if an SRAM WRITE has been done since the last nonvolatilecycle. After the store (if any) completes, the part
will go into standby mode, inhibiting all operations until
Note n: The six consecutive addresses must be in order listed.
Note o: While there are 15 addresses on the STK14C88-M, only the lower 14 are used to control software modes.
Note p: I/O state assumes
HARDWARE
NO.
Standard Alternate MIN MAX
22 t
STORE
23 t
DELAY
24 t
RECOVER
25 t
HLHX
26 t
HLBL
Note q: E and G low and W high for output behavior.
Note r: t
RECOVER
G < VIL. Activation of nonvolatile cycles does not depend on state ofG.
STORE
SYMBOLS
t
HLHZ
t
HLQZ
t
HHQX
is only applicable after t
03E0
3C1F
303F
0FC0
0E38
31C7
03E0
3C1F
303F
0C63
Nonvolatile
HSB rises.
W must be high during all six consecutive cycles to enable a nonvolatile cycle.
CYCLE (VCC = 5.0V ± 10%)
STORE
Cycle Duration 10 ms i, q
Time Allowed to Complete SRAM Cycle 1 µs i, q
Hardware
STORE
High to Inhibit Off 700 ns q, r
Hardware
STORE
Pulse Width 20 ns
Hardware
STORE
Low to
is complete.
STORE
STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
RECALL
PARAMETER
STORE
Busy 300 ns
Output High Z l
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
CC
Active
l
CC
Active
STK14C88-M
2
2
UNITS NOTES
m
n, o, p
n, o, p
e
HARDWARE
HSB (IN)
HSB (OUT)
DQ (DATA OUT)
STORE
HIGH IMPEDANCE
CYCLE
25
t
HLHX
DATA VALID
t
HLBL
26
t
DELAY
22
t
STORE
23
April 1999 5-47
24
t
RECOVER
HIGH IMPEDANCE
DATA VALID
STK14C88-M
AutoStore
NO.
27 t
28 t
29 t
30 t
31 V
32 V
Note s: t
Note t:
AutoStore
™/POWER-UP
SYMBOLS
Standard Alternate MIN MAX
RESTORE
STORE
VSBL
DELAY
SWITCH
RESET
starts from the time VCC rises above V
RESTORE
HSB is asserted low for 1µs when V
will be released and no
™/POWER-UP
V
CC
31
V
SWITCH
32
V
RESET
AutoStore
™
t
t
HLHZ
BLQZ
STORE
RECALL
PARAMETER
Power-up
RECALL
Duration 550 µss
STORE
Cycle Duration 10 ms q, t
Low Voltage Trigger (V
Time Allowed to Complete SRAM Cycle 1 µsq
Low Voltage Trigger Level 4.0 4.5 V
Low Voltage Reset Level 3.9 V
SWITCH
drops through V
CAP
will take place.
) to HSB Low 300 ns l
SWITCH
.
. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB
SWITCH
(VCC = 5.0V ± 10%)
STK14C88-M
UNITS NOTES
RECALL
e
POWER-UP
RECALL
HSB
DQ (DATA OUT)
W
27
t
RESTORE
POWER-UP
RECALL
BROWN OUT
NO STORE DUE TO
NO SRAM WRITES
NO
RECALL
(VCC DID NOT GO
BELOW V
RESET
)
April 1999 5-48
29
t
VSBL
30
t
DELAY
BROWN OUT
AutoStore
™
NO
RECALL
(VCC DID NOT GO
BELOW V
RESET
28
t
STORE
BROWN OUT
AutoStore
™
RECALL
WHEN
V
RETURNS
CC
)
ABOVE V
SWITCH
STK14C88-M
SOFTWARE-CONTROLLED
NO.
33 t
34 t
35 t
36 t
37 t
Note u: The software sequence is clocked with E controlled READs.
Note v: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for
SOFTWARE
ADDRESS
DQ (DATA OUT)
SYMBOLS
Standard Alternate MIN MAX MIN MAX
AVAV
AVEL
ELEH
ELAX
RECALL
STORE
a
t
RC
t
AS
t
CW
cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a
STORE/RECALL
34
t
AVEL
E
STORE/RECALL
PARAMETER
STORE/RECALL
Address Set-up Time 0 0 ns u
Clock Pulse Width 25 30 ns u
Address Hold Time 20 25 ns u
RECALL
Initiation Cycle Time 35 45 ns q
Duration 20 20 µs
CYCLE
RECALL
cycle. W must be high during all six consecutive cycles.
CYCLE: E Controlled
33
t
AVAV
35
t
ELEH
36
t
ELAX
DATA VALID
ADDRESS #6ADDRESS #1
v
STK14C88-35M STK14C88-45M
(VCC = 5.0V ± 10%)
v
33
t
AVAV
28 37
t
/ t
STORE
RECALL
DATA VALID
HIGH IMPEDANCE
UNITS NOTES
e
April 1999 5-49
STK14C88-M
DEVICE OPERATION
The STK14C88-M has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static
RAM. In nonvolatile mode, data is transferred
from
SRAM to EEPROM (the
from
EEPROM to SRAM (the
this mode
SRAM functions are disabled.
STORE
RECALL
operation) or
operation). In
NOISE CONSIDERATIONS
The STK14C88-M is a high-speed memory and so
must have a high frequency bypass capacitor of
approximately 0.1µF connected between V
V
, using leads and traces that are as short as pos-
SS
sible. As with all high-speed
CMOS ICs, normal care-
CAP
and
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK14C88-M performs a READ cycle whenever
E and G are low and W and HSB are high. The
address specified on pins A
determines which of
0-14
the 32,768 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of t
#1). If the
be valid at t
READ is initiated by EorG, the outputs will
ELQV
or at t
, whichever is later (READ
GLQV
(READ cycle
AVQV
cycle #2). The data outputs will repeatedly respond
to address changes within the t
access time with-
AVQV
out the need for transitions on any control input pins,
and will remain valid until another address change or
until
EorG is brought high, or WorHSB is brought
low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and
stable prior to entering the
remain stable until either
end of the cycle. The data on the common I/O pins
DQ
before the end of a W controlled WRITE or t
before the end of an E controlled WRITE.
It is recommended that
entire
common I/O lines. If
turn off the output buffers t
HSB is high. The address inputs must be
WRITE cycle and must
EorW goes high at the
will be written into the memory if it is valid t
0-7
G be kept high during the
WRITE cycle to avoid data bus contention on
G is left low, internal circuitry will
after W goes low.
WLQZ
DVWH
DVEH
POWER-UP
RECALL
During power up, or after any low-power condition
(V
CAP<VRESET
latched. When V
voltage of V
be initiated and will take t
If the STK14C88-M is in a
power-up
), an internal
SWITCH
RECALL
RECALL
once again exceeds the sense
CAP
,a
RECALL
cycle will automatically
RESTORE
WRITE state at the end of
request will be
to complete.
, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between
V
or between E and system VCC.
CC
SOFTWARE NONVOLATILE
The STK14C88-M software
by executing sequential
STORE
E controlled READ cycles
W and system
STORE
cycle is initiated
from six specific address locations. During the
STORE
cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the
nonvolatile elements. The program operation copies
the
SRAM data into nonvolatile memory. Once a
STORE
cycle is initiated, further input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific
addresses is used for
tant that no other
STORE
READ or WRITE accesses inter-
initiation, it is impor-
vene in the sequence, or the sequence will be
aborted and no
To initiate the software
READ sequence must be performed:
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0FC0 (hex) Initiate
STORE
or
STORE
RECALL
will take place.
cycle, the following
STORE
cycle
The software sequence must be clocked with E controlled
READs.
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
and not
although it is not necessary that
sequence to be valid. After the t
been fulfilled, the
READ and WRITE operation.
STORE
WRITE cycles be used in the sequence,
cycle will commence and the
READ cycles
G be low for the
cycle time has
SRAM will again be activated for
STORE
April 1999 5-50
STK14C88-M
SOFTWARE NONVOLATILE
A software
of
READ operations in a manner similar to the soft-
ware
the following sequence of
RECALL
STORE
cycle is initiated with a sequence
initiation. To initiate the
E controlled READ opera-
RECALL
RECALL
cycle,
tions must be performed:
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0C63 (hex) Initiate
Internally,
RECALL
is a two-step procedure. First, the
RECALL
cycle
SRAM data is cleared, and second, the nonvolatile
information is transferred into the
the t
ready for
cycle time the SRAM will once again be
RECALL
READ and WRITE operations. The
SRAM cells. After
RECALL
operation in no way alters the data in the EEPROM
cells. The nonvolatile data can be recalled an unlimited number of times.
AutoStore
™ OPERATION
The STK14C88-M can be powered in one of three
modes.
During normal
STK14C88-M will draw current from V
capacitor connected to the V
AutoStore
™ operation, the
to charge a
CCX
pin. This stored
CAP
charge will be used by the chip to perform a single
STORE
operation. After power up, when the voltage
on the V
automatically disconnect the V
initiate a
pin drops below V
CAP
STORE
operation.
SWITCH
pin from V
CAP
, the part will
and
CCX
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68µF and
220µF (± 20%) rated at 6V should be provided.
In system power mode (Figure 3), both V
V
are connected to the + 5V power supply without
CAP
the 100µF capacitor. In this mode the
AutoStore
CCX
and
™
function of the STK14C88-M will operate on the
stored system charge as power goes down. The
user must, however, guarantee that V
drop below 3.6V during the 10ms
STORE
If an automatic
then V
V
CAP
can be tied to ground and + 5V applied to
CCX
(Figure 4). This is the
mode, in which the
on power loss is not required,
AutoStore
STORE
AutoStore
™ function is disabled.
does not
CCX
cycle.
™ Inhibit
If the STK14C88-M is operated in this configuration,
references to V
throughout this data sheet. In this mode,
should be changed to V
CCX
CAP
STORE
operations may be triggered through software control or the
HSB pin. It is not permissable to change
between these three options “on the fly”.
In order to prevent unneeded
automatic
externally driving
least one
most recent
initiated
whether a
STORE
s as well as those initiated by
HSB low will be ignored unless at
WRITE operation has taken place since the
STOREorRECALL
STORE
cycles are performed regardless of
WRITE operation has taken place. An
optional pull-up resistor is shown connected to
STORE
operations,
cycle. Software-
HSB.
This can be used to signal the system that the
AutoStore
™ cycle is in progress.
10kΩ∗
+
68µF
6v, 20%
Figure 2:
0.1µF
Bypass
1
16
AutoStore
32
31
30
17
™ Mode
10kΩ
0.1µF
Figure 3: System Power Mode
1
Bypass
16
*If HSB is not used, it should be left unconnected.
April 1999 5-51
0.1µF
10kΩ∗
32
31
30
17
10kΩ
Bypass
Figure 4:
1
32
31
30
16
17
AutoStore
Inhibit Mode
10kΩ∗
10kΩ
™
STK14C88-M
HSB OPERATION
The STK14C88-M provides the HSB pin for controlling and acknowledging the
HSB pin can be used to request a hardware
cycle. When the HSB pin is driven low, the
STK14C88-M will conditionally initiate a
operation after t
begin if a
last
WRITE to the SRAM took place since the
STOREorRECALL
; an actual
DELAY
an open drain driver that is internally driven low to
indicate a busy condition while the
by any means) is in progress.
SRAM READ and WRITE operations that are in
progress when
HSB is driven low by any means are
given time to complete before the
is initiated. After
will continue
multiple
WRITE is in progress when HSB is pulled low it will
SRAM READ operations may take place. If a
be allowed a time, t
SRAM WRITE cycles requested after HSB goes low
HSB goes low, the STK14C88-M
SRAM operations for t
DELAY
will be inhibited until
HSB pin can be used to synchronize multiple
The
STK14C88-Ms while using a single larger capacitor.
To operate in this mode, the
nected together to the
STK14C88-Ms. An external pull-up resistor to + 5V
is required since
down. The V
HSB acts as an open drain pull
pins from the other STK14C88-M
CAP
parts can be tied together and share a single capacitor. The capacitor size must be scaled by the number of devices connected to it. When any one of the
STK14C88-Ms detects a power loss and asserts
HSB, the common HSB pin will cause all parts to
request a
STORE
cycle (a
those STK14C88-Ms that have been written since
the last nonvolatile cycle).
During any
STORE
operation, regardless of how it
was initiated, the STK14C88-M will continue to drive
the
HSB pin low,releasing it only when the
complete. Upon completion of the
the STK14C88-M will remain disabled until the
pin returns high.
If HSB is not used, it should be left unconnected.
STORE
operations. The
STORE
cycle will only
cycle. The HSB pin acts as
STORE
(initiated
STORE
operation
. During t
DELAY
, to complete. However, any
HSB returns high.
HSB pin should be con-
HSB pins from the other
STORE
will take place in
STORE
STORE
operation
STORE
STORE
DELAY
HSB
PREVENTING STORES
The
STORE
holding
30mA at a V
function can be disabled on the fly by
HSB high with a driver capable of sourcing
of at least 2.2V,as it will haveto over-
OH
power the internal pull-down device that drives
low for 20µs at the onset of a
STK14C88-M is connected for
tion (system V
capacitor on V
connected to V
CC
) and VCCcrosses V
CAP
STORE
AutoStore
CCX
waydown, the STK14C88-M will attempt to pull
low; if
HSB doesn’t actually get below VIL, the part
will stop trying to pull
HSB low and abort the
attempt.
HARDWARE PROTECT
The STK14C88-M offers hardware protection
against inadvertent
,
WRITEs during low-voltage conditions. When V
V
, all externally initiated
SWITCH
SRAM WRITEs are inhibited.
AutoStore
V
CCX
AutoStore
™ can be completely disabled by tying
to ground and applying + 5V to V
™ Inhibit mode;
STORE
operation and SRAM
STORE
operations and
STORE
s are only initiated
by explicit request using either the software
sequence or the
HSB pin in this mode.
LOW AVERAGE ACTIVE POWER
The STK14C88-M will draw significantly less current
when it is cycled at times longer than 50ns. Figure 5
shows the relationship between I
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
perature range, V
= 5.5V, 100% duty cycle on chip
CC
enable). Figure 6 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled.
The overall average current drawn by the
STK14C88-M depends on the following items:
1)
is
CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of
temperature; 6) the V
READstoWRITEs; 5) the operating
level; and 7) I/O loading.
CC
and READ cycle
CC
HSB
. When the
™ opera-
and a 68µF
on the
SWITCH
HSB
STORE
CAP
. This is the
CAP
<
April 1999 5-52
STK14C88-M
100
80
60
40
20
Average Active Current (mA)
0
Figure 5: ICC (max) Reads
TTL
CMOS
50 100 150 200
Cycle Time (ns)
100
80
60
40
20
Average Active Current (mA)
0
50 100 150 200
Cycle Time (ns)
Figure 6: ICC (max) Writes
TTL
CMOS
April 1999 5-53
STK14C88-M
ORDERING INFORMATION
STK14C88 - 5 L 45 M
Temperature Range
M =Military (–55 to 125˚C)
Access Time
35 = 35ns
45 = 45ns
Package
L = 32-Pad LCC
C = Ceramic 32-Pin 300 mil CDIP
K = Ceramic 32-Pin 300 mil CDIP
with solder DIP finish
April 1999 5-54
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