SIMTEK STK14C88-3 Technical data
STK14C88-3
32K x 8 AutoStore™nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• 35ns, 45ns and 55ns Access Times
• “Hands-off” Automatic STORE with External
68µF Capacitor on Power Down
• STORE to nonvolatile elements Initiated by
Hardware, Software or AutoStore™
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
at 200ns Cycle Time
CC
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to nonvolatile elements (Commercial/Industrial)
• 100-Year Data Retention in nonvolatile elements (Commercial/Industrial)
• Single 3.3V +
0.3V Operation
• Commercial and Industrial Temperatures
• 32-Pin SOIC and DIP Packages
BLOCK DIAGRAM
V
CCXVCAP
Quantum Trap
STATIC RAM
ARRAY
512 x 512
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A
512 x 512
STORE
RECALL
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
ROW DECODER
INPUT BUFFERS
POWER
CONTROL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
A0 - A
HSB
G
E
W
DESCRIPTION
The Simtek STK14C88-3 is a fast static RAM with a
nonvolatile element incorporated in each static
memory cell. The
SRAM can be read and written an
unlimited number of times, while independent, nonvolatile data resides in nonvolatile elements. Data
transfers from the
STORE operation) can take place automatically
(the
SRAM to the nonvolatile elements
on power down. A 68µF or larger capacitor tied from
V
to ground guarantees the STORE operation,
CAP
regardless of power-down slew rate or loss of power
from “hot swapping”. Transfers from the nonvolatile
elements to the
SRAM (the RECALL operation) take
place automatically on restoration of power. Initia-
STORE and RECALL cycles can also be soft-
tion of
ware controlled by entering specific read
sequences. A hardware
STORE may be initiated with
the HSB pin.
PIN CONFIGURATIONS
V
V
1
CAP
A
2
14
A
3
12
A
4
7
A
5
6
A
6
5
A
7
DQ
DQ
DQ
V
NC
4
A
8
3
9
A
10
2
A
11
1
A
12
0
13
0
14
1
15
2
16
SS
13
32
CCX
HSB
31
30
W
29
A
13
28
A
8
A
27
9
A
26
11
25
G
24
NC
A
23
10
E
22
DQ
21
7
20
DQ
6
19
DQ
5
18
DQ
4
DQ
17
3
PIN NAMES
A0 - A14DQ0 -DQ7E W G HSB V
Address
Inputs
Data In/Out Chip
Enable
Write
Enable
Output
Enable
Hardware
Store
Busy (I/O)
CCX
Power
(+ 3.3V)
32 - DIP
32 - SOIC
V
CAP
Capacitor Ground
V
SS
48 - SSOP
(not to scale)
November 2003 1 Document Control # ML0015 rev 0.3
STK14C88-3
ABSOLUTE MAXIMUM RATINGS
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 4.5V
Voltage on Input Relative to V
Voltage on DQ
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
or HSB . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
0-7
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
. . . . . . . . . . –0.6V to (VCC + 0.5V)
SS
a
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
DC CHARACTERISTICS (VCC = 3.0V-3.6V)
SYMBOL PARAMETER
b
I
CC
I
CC
I
CC
I
CC
I
SB
I
SB
I
ILK
I
OLK
V
V
V
V
V
T
Note b: I
Note c: I
Note d: E
Note e: V
Average VCC Current 50
1
c
Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max
2
b
Average V
3
5V, 25°C, Typical
c
Average V
4
AutoStore™ Cycle
d
Average V
1
(Standby, Cycling TTL Input Levels)
d
V
CC
2
(Standby, Stable CMOS Input Levels)
Current at t
CC
Current during
CAP
Current
CC
Standby Current
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
IH
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
IL
Output Logic “1” Voltage 2.4 2.4 V I
OH
Output Logic “0” Voltage 0.4 0.4 V I
OL
Logic “0” Voltage on HSB Output 0.4 0.4 V I
BL
Operating Temperature 0 70 – 40 85 °C
A
and I
CC
CC
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
CC
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
1
3
and I
are the average currents required for the duration of the respective STORE cycles (t
CC
2
4
reference levels throughout this datasheet refer to V
AVAV
= 200ns
COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX
52
42
37
44
39
99mA
22mA
18
16
15
19
17
16
11mA
±1 ±1 µA
±1 ±1 µA
.
CCX
UNITS NOTES
mA
t
= 35ns
mA
mA
AVAV
t
= 45ns
AVAV
t
= 55ns
AVAV
W ≥ (V
– 0.2V)
CC
All Others Cycling, CMOS Levels
All Inputs Don’t Care
mA
t
= 35ns, E ≥ V
mA
mA
AVAV
t
= 45ns, E ≥ V
AVAV
t
= 55ns, E ≥ V
AVAV
IH
IH
IH
E ≥ (VCC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
V
= max
CC
STORE
VIN = VSS to V
V
CC
V
IN
OUT
OUT
OUT
).
CC
= max
= VSS to VCC, E or G ≥ VIH
= – 4mA except HSB
= 8mA except HSB
= 3mA
e
AC TEST CONDITIONS
3.3V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
f
CAPACITANCE
(TA = 25°C, f = 1.0MHz)
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
Input Capacitance 5 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V
Note f: These parameters are guaranteed but not tested.
OUTPUT
351 Ohms
Figure 1: AC Output Loading
317 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
November 2003 2 Document Control # ML0015 rev 0.3
STK14C88-3
SRAM READ CYCLES #1 & #2 (VCC = 3.0V-3.6V)
NO.
1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
Note g: W and HSB must be high during SRAM READ cycles.
Note h: I/O state asumes E
Note i: Measured ± 200mV from steady state output voltage.
SYMBOLS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX
ELQV
AVAV
AVQ V
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
t
g
t
h
t
t
h
t
t
i
t
t
i
t
f
t
f
t
Chip Enable Access Time 35 45 55 ns
ACS
Read Cycle Time 35 45 55 ns
RC
Address Access Time 35 45 55 ns
AA
Output Enable to Data Valid 15 20 25 ns
OE
Output Hold after Address Change 5 5 5 ns
OH
Chip Enable to Output Active 5 5 5 ns
LZ
Chip Disable to Output Inactive 13 15 20 ns
HZ
Output Enable to Output Active 0 0 0 ns
OLZ
Output Disable to Output Inactive 13 15 20 ns
OHZ
Chip Enable to Power Active 0 0 0 ns
PA
Chip Disable to Power Standby 35 45 55 ns
PS
and G < V
and W > VIH; device is continuously selected.
IL
PARAMETER
SRAM READ CYCLE #1: Address Controlledg,
2
t
t
AVQ V
AVAV
3
ADDRESS
DQ (DATA OUT)
t
AXQX
5
STK14C88-3-35 STK14C88-3-45 STK14C88-3-55
h
DATA VALID
UNITS
e
t
GLQV
g
2
t
AVAV
1
t
ELQV
4
ACTIVE
t
DATA VALID
9
GHQZ
t
EHQZ
t
7
11
EHICCL
SRAM READ CYCLE #2: E Controlled
ADDRESS
STANDBY
t
ELQX
10
t
ELICCH
6
t
GLQX
8
DQ (DATA OUT)
I
E
G
CC
November 2003 3 Document Control # ML0015 rev 0.3
STK14C88-3
SRAM WRITE CYCLES #1 & #2 (VCC = 3.0V-3.6V)
NO.
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E
Note l: HSB
SRAM WRITE CYCLE #1: W Controlled
ADDRESS
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX
AVAV
WLWH
ELWH
DVWH
WHDX
AVW H
AVW L
WHAX
WLQZ
WHQX
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVE H
t
AVE L
t
EHAX
i, j
or W must be ≥ V
must be high during SRAM WRITE cycles.
t
Write Cycle Time 35 45 55 ns
WC
t
Write Pulse Width 25 30 40 ns
WP
t
Chip Enable to End of Write 25 30 40 ns
CW
t
Data Set-up to End of Write 12 15 25 ns
DW
t
Data Hold after End of Write 0 0 0 ns
DH
t
Address Set-up to End of Write 25 30 40 ns
AW
t
Address Set-up to Start of Write 0 0 0 ns
AS
t
Address Hold after End of Write 0 0 0 ns
WR
t
Write Enable to Output Disable 13 15 20 ns
WZ
t
Output Active after End of Write 5 5 5 ns
OW
during address transitions.
IH
PARAMETER
k, l
12
t
AVAV
14
t
ELWH
E
17
t
t
WLQZ
AVW H
13
t
WLWH
20
DATA IN
DATA IN
DATA OUT
18
t
AVWL
W
PREVIOUS DATA
STK14C88-3-35 STK14C88-3-45 STK14C88-3-55
19
t
WHAX
15
t
DVWH
DATA VALID
HIGH IMPEDANCE
16
t
WHDX
21
t
WHQX
UNITS
e
SRAM WRITE CYCLE #2: E Controlled
ADDRESS
t
AVEL
18
k, l
t
ELEH
12
t
AVAV
14
t
EHAX
19
E
17
t
AVE H
W
DATA IN
DATA OUT
13
t
WLEH
HIGH IMPEDANCE
t
DVEH
15
DATA VALID
16
t
EHDX
November 2003 4 Document Control # ML0015 rev 0.3
STK14C88-3
HARDWARE MODE SELECTION
E W HSB A13 - A0 (hex) MODE I/O POWER NOTES
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active t
L L H X Write SRAM Input Data Active
X X L X Nonvolatile STORE Output High Z l
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,
the part will go into standby mode, inhibiting all operations until HSB
rises.
CC
2
HARDWARE STORE CYCLE (VCC = 3.0V-3.6V)
NO.
22 t
23 t
24 t
25 t
26 t
Note n: E and G low and W high for output behavior.
Note o: t
RECOVER
SYMBOLS
Standard Alternate MIN MAX
STORE
DELAY
RECOVER
HLHX
HLBL
t
HLHZ
t
HLQZ
t
HHQX
is only applicable after t
STORE Cycle Duration 10 ms i, n
Time Allowed to Complete SRAM Cycle 1 µsi, n
Hardware STORE High to Inhibit Off 700 ns n, o
Hardware STORE Pulse Width 15 ns
Hardware STORE Low to STORE Busy 300 ns
is complete.
STORE
PARAMETER
STK14C88-3
HARDWARE STORE CYCLE
25
t
HSB (IN)
HLHX
22
t
STORE
24
t
RECOVER
m
UNITS NOTES
e
26
t
DATA VALID
HLBL
t
23
DELAY
HIGH IMPEDANCE
DATA VALID
HSB (OUT)
DQ (DATA OUT)
HIGH IMPEDANCE
November 2003 5 Document Control # ML0015 rev 0.3
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