SIMTEK STK12C68-P45I, STK12C68-P35I, STK12C68-P35, STK12C68-P25, STK12C68-W35I Datasheet

X

STK12C68

FEATURES

• 25ns, 35ns, 45ns and 55ns Access Times

STORE

• “Hands-off” Automatic

68µF Capacitor on Power Down

•

STORE

Software or

•

RECALL

to EEPROM Initiated by Hardware,

AutoStore

™ on Power Down

to SRAM Initiated by Software or

Power Restore

• 10mA Typical I

at 200ns Cycle Time

CC

• Unlimited READ, WRITE and

• 1,000,000

STORE

Cycles to EEPROM

• 100-Year Data Retention in EEPROM

• Single 5V

+ 10% Operation

• Not Sensitive to Power On/Off Ramp Rates

• No Data Loss from Undershoot

• Commercial and Industrial Temperatures

• 28-Pin SOIC and DIP Packages

with External

RECALL

Cycles

8K x 8

Nonvolatile Static RAM

DESCRIPTION

The Simtek STK12C68 is a fast static RAM with a
nonvolatile, electrically erasable
incorporated in each static memory cell. The
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in

EEPROM. Data transfers from the SRAM to the
EEPROM (the

matically on power down. A 68µF or larger capacitor
tied from V
operation, regardless of power-down slew rate or
loss of power from “hot swapping”. Transfers from
the
take place automatically on restoration of power. Ini­tiation of
software controlled by entering specific read
sequences. A hardware
the

AutoStore

™ nvSRAM

QuantumTrap

STORE

operation) can take place auto-

to ground guarantees the

CAP

EEPROM to the SRAM (the

STORE

HSB pin.

and

RECALL

STORE

™ CMOS

PROM element

SRAM

STORE

RECALL

cycles can also be

may be initiated with

operation)

BLOCK DIAGRAM

V

CCXVCAP

POWER

CONTROL

STORE/
RECALL

CONTROL

SOFTWARE

DQ
DQ
DQ
DQ

DQ
DQ

DQ
DQ

EEPROM ARRAY

ARRAY

2

A3A

128 x 512

A

A

4

STORE

RECALL

10

A

5

A

6

A

7

A

8

A

9

A

11

A

12

0
1
2
3

4
5

6
7

STATIC RAM

ROW DECODER

COLUMN I/O

COLUMN DEC

A0A

INPUT BUFFERS

128 x 512

1

March 2000 4-41

DETECT

PIN CONFIGURATIONS

1

HSB

A0-A

V

CAP

A

12

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

DQ

0

DQ

1

DQ

2

V

SS

12

28

V

2
3
4
5
6
7
8
9
10
11
12
13
14

CC

27

W

26

HSB

25

A

8

A

24

9

A

23

11

22

G

21

A

10

20

E

19

DQ

7

18
17
16
15

28 - 300 PDIP

DQ

6

DQ

28 - 600 PDIP

5

DQ

4

28 - 350 SOIC

DQ

3

28 - 300 CDIP

PIN NAMES

A0 - A
DQ
E Chip Enable
W Write Enable

G

E
W

G Output Enable
HSB Hardware Store Busy (I/O)
V

CCX

V

CAP

V

SS

Address Inputs

12

-DQ7Data In/Out

0

Power (+ 5V)
Capacitor
Ground

ABSOLUTE MAXIMUM RATINGS

a

Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V)

Voltage on DQ

Temperature under Bias. . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)

0-7

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA

Note a: Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con­ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat­ing conditions for extended periods may affect reliability.

DC CHARACTERISTICS (VCC = 5.0V ± 10%)

SYMBOL PARAMETER

c

I

I
I

I

I

I

I

I

V
V
V
V
V
T

Note b: Note c: I Note d: I Note e: Note f: V

Average VCC Current 90

CC

1

d

Average VCC Current during

CC

2

c

Average VCCCurrent at t

CC

3

5V, 25˚C, Typical

d

Average V

CC

4

AutoStore

e

Average VCCCurrent

SB

1

(Standby, Cycling TTL Input Levels)

e

VCCStandby Current

SB

2

(Standby, Stable CMOS Input Levels)
Input Leakage Current

ILK

Off-State Output Leakage Current

OLK

Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs

IH

Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs

IL

Output Logic “1” Voltage 2.4 2.4 V I

OH

Output Logic “0” Voltage 0.4 0.4 V I

OL

Logic “0” Voltage onHSB Output 0.4 0.4 V I

BL

Operating Temperature 0 70 –40 85 °C

A

and I

CC

1

and I

CC

2

E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.

reference levels throughout this datasheet refer to V

CC

nected to ground.

Current during

CAP

™ Cycle

are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

CC

3

are the average currents required for the duration of the respective

CC

4

AVAV

STORE

= 200ns

COMMERCIAL INDUSTRIAL

MIN MAX MIN MAX

90
75
65
55

75

65

55

3 3 mA All Inputs Don’t Care, VCC = max

10 10 mA

22mA

27
23
20
19

28

24

21

20

1.5 1.5 mA

±1 ±1 µA

±5 ±5 µA

STORE

if that is where the power supply connection is made, or V

CCX

UNITS NOTES

t

mA
mA
mA
mA

= 25ns

AVAV

t

= 35ns

AVAV

t

= 45ns

AVAV

t

= 55ns

AVAV

W ≥ (VCC– 0.2V)
All Others Cycling, CMOS Levels

All Inputs Don’t Care

t

mA
mA
mA
mA

cycles (t

STORE

= 25ns, E ≥ V

AVAV

t

= 35ns, E ≥ V

AVAV

t

= 45ns, E ≥ V

AVAV

t

= 55ns, E ≥ V

AVAV

E ≥ (VCC – 0.2V)
All Others V

VCC= max
V

= VSS to V

IN

VCC= max
V

= VSS to VCC, E or G ≥ V

IN

=– 4mA except HSB

OUT

= 8mA except HSB

OUT

= 3mA

OUT

).

IH
IH
IH
IH

≤ 0.2V or ≥ (VCC – 0.2V)

IN

CC

IH

if V

CCX

is con-

CAP

f

AC TEST CONDITIONS

Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V

Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns

Input and Output Timing Reference Levels. . . . . . . . . . . . . . . .1.5V

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

g

CAPACITANCE

(TA = 25°C, f = 1.0MHz)

SYMBOL PARAMETER MAX UNITS CONDITIONS

C

IN

C

OUT

Input Capacitance 8 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V

Note g: These parameters are guaranteed but not tested.

March 2000 4-42

OUTPUT

5.0V

480 Ohms

255 Ohms

30 pF

INCLUDING
SCOPE AND
FIXTURE

Figure 1: AC Output Loading

SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)

NO.

1t
2t
3t
4t
5t
6t
7t
8t

9t
10 t
11 t

Note h: W and HSB must be high during SRAM READ cycles.
Note i: Device is continuously selected with
Note j: Measured ± 200mV from steady state output voltage.

SYMBOLS

#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX

ELQV

AVAV

AVQV

GLQV

AXQX

ELQX

EHQZ

GLQX

GHQZ

ELICCH

EHICCL

t

ACS

h

t

RC

i

t

AA

t

OE

i

t

OH

t

LZ

j

t

HZ

t

OLZ

j

t

OHZ

g

t

PA

g

t

PS

PARAMETER

Chip Enable Access Time 25 35 45 55 ns
Read Cycle Time 25 35 45 55 ns
Address Access Time 22 35 45 55 ns
Output Enable to Data Valid 10 15 20 25 ns
Output Hold after Address Change 5 5 5 5 ns
Chip Enable to Output Active 5 5 5 5 ns
Chip Disable to Output Inactive 10 13 15 17 ns
Output Enable to Output Active 0 0 0 0 ns
Output Disable to Output Inactive 10 13 15 17 ns
Chip Enable to Power Active 0 0 0 0 ns
Chip Disable to Power Standby 25 35 45 55 ns

E and G both low.

SRAM READ CYCLE #1: Address Controlled

ADDRESS

5

t

DQ (DATA OUT)

AXQX

STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55

h, i

2

t

AVAV

3

t

AVQV

DATA VALID

UNITS

f

SRAM READ CYCLE #2: E Controlled

ADDRESS

E

t

ELQX

6

h

t

AVAV

2

t

ELQV

1

G

4

t

GLQV

8

t

GLQX

DQ (DATA OUT)

10

t

ELICCH

I

CC

STANDBY

ACTIVE

March 2000 4-43

DATA VALID

t

GHQZ

9

t

EHQZ

7

11

t

EHICCL

SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V ± 10%)

NO.

12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t

Note k: If W is low when E goes low, the outputs remain in the high-impedance state.
Note l:
Note m:

SYMBOLS

#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX

AVAV

WLWH

ELWH

DVWH

WHDX

AVWH

AVWL

WHAX

WLQZ

WHQX

E or W must be ≥ VIHduring address transitions.
HSB must be high during SRAM WRITE cycles.

t

AVAV

t

WLEH

t

ELEH

t

DVEH

t

EHDX

t

AVEH

t

AVEL

t

EHAX

j, k

t

WC

t

WP

t

CW

t

DW

t

DH

t

AW

tASAddress Set-up to Start of Write 0000ns

t

WR

t

WZ

t

OW

PARAMETER

Write Cycle Time 25 35 45 55 ns
Write Pulse Width 20 25 30 35 ns
Chip Enable to End of Write 20 25 30 35 ns
Data Set-up to End of Write 10 12 15 17 ns
Data Hold after End of Write 0000ns
Address Set-up to End of Write 20 25 30 35 ns

Address Hold after End of Write 0000ns
Write Enable to Output Disable 10 13 15 17 ns
Output Active after End of Write 5555ns

SRAM WRITE CYCLE #1: W Controlled

ADDRESS

t

t

AVWH

17

13

t

WLWH

ELWH

DATA IN

DATA OUT

E

18

t

AVWL

W

20

t

WLQZ

PREVIOUS DATA

STK12C68-25 STK12C68-45 STK12C68-35 STK12C68-55

l, m

12

t

AVAV

14

15

t

DVWH

DATA VALID

HIGH IMPEDANCE

t

16

t

WHDX

19

WHAX

21

t

WHQX

UNITS

f

SRAM WRITE CYCLE #2: E Controlled

ADDRESS

18

t

E

W

AVEL

t

AVEH

17

l, m

t

AVAV

12

14

t

ELEH

t

WLEH

DATA IN

DATA OUT

HIGH IMPEDANCE

March 2000 4-44

19

t

EHAX

13

15

t

DVEH

DATA VALID

t

EHDX

16