SIMTEK STK12C68-P45, STK12C68-P25I, STK12C68-C45, STK12C68-C35I, STK12C68-C35 Datasheet

STK12C68

8K x 8 AutoStore™ nvSRAM

QuantumTrap™ CMOS

Nonvolatile Static RAM

FEATURES

• 20ns, 25ns, 35ns and 45ns Access Times

•“Hands-off” Automatic STORE with External

68µF Capacitor on Power Down

• STORE to EEPROM Initiated by Hardware,
Software or AutoStore™ on Power Down

• RECALL to SRAM Initiated by Software or
Power Restore

• 10mA Typical I

at 200ns Cycle Time

CC

• Unlimited READ, WRITE and RECALL Cycles

• 1,000,000 STORE Cycles to EEPROM

• 100-Year Data Retention in EEPROM

• Single 5V +

10% Operation

• Not Sensitive to Power On/Off Ramp Rates

• No Data Loss from Undershoot

• Commercial and Industrial Temperatures

• 28-Pin SOIC and DIP Packages

BLOCK DIAGRAM

V

CCXVCAP

POWER

CONTROL

STORE/

RECALL

CONTROL

DQ
DQ
DQ
DQ

DQ
DQ

DQ
DQ

EEPROM ARRAY

128 x 512

A

5

A

6

A

7

A

8

A

9

A

11

A

12

0
1
2
3

4
5

6
7

INPUT BUFFERS

ROW DECODER

STATIC RAM

ARRAY

128 x 512

COLUMN I/O

COLUMN DEC

A0A

2

1

A3A

STORE

RECALL

A

A

10

4

DESCRIPTION

The Simtek STK12C68 is a fast static RAM with a
nonvolatile, electrically erasable

PROM element

incorporated in each static memory cell. The
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in

EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation) can take place

automatically on power down. A 68µF or larger
capacitor tied from V

STORE operation, regardless of power-down slew

to ground guarantees the

CAP

rate or loss of power from “hot swapping”. Transfers
from the

EEPROM to the SRAM (the RECALL opera-

tion) take place automatically on restoration of
power. Initiation of

STORE and RECALL cycles can

also be software controlled by entering specific read
sequences. A hardware
the HSB

pin.

STORE may be initiated with

PIN CONFIGUR ATIONS

28

V

CCX

27

W

26

HSB

25

A

8

A

24

9

A

23

11

22

G

21

A

10

20

E

19

DQ

7

18
17
16
15

Address Inputs

Chip Enable
Write Enable
Output Enable
Hardware Store Busy (I/O)
Power (+ 5V)
Capacitor
Ground

28 - 300 PDIP

DQ

6

DQ

28 - 600 PDIP

5

DQ

4

28 - 350 SOIC

DQ

3

28 - 300 CDIP

SOFTWARE

DETECT

V

1

CAP

A

2

12

3

A

7

A

4

6

A

5

5

A

6

4

A

7

3

A

8

2

A

9

DQ
DQ
DQ

V

1

A

10

0

11

0

12

1

13

2

14

SS

HSB

A0 - A

12

PIN NAMES

A0 - A

12

-DQ7Data In/Out

DQ

0

E
W

G

E
W

G
HSB
V

CCX

V

CAP

V

SS

SRAM

July 1999 4-41

STK12C68

ABSOLUTE MAXIMUM RATINGS

Volt age on Input Rel ative to VSS . . . . . . . . . .– 0.6V to (VCC + 0.5V)

Volt age on DQ

Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA

or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)

0-7

a

Note a: Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con­ditions above those indicated in the operational sec tions of this
specification is not implied. Exposure to absolute maximum rat­ing conditions for extended periods may affect reliability.

DC CHARACTERISTICS (VCC = 5.0V ± 10%)

SYMBOL PARAMETER

c

I

I
I

I

I

I

I

I

V
V
V
V
V
T

CC

CC

CC

CC

SB

SB

ILK

OLK

IH

IL

OH

OL

BL

A

Average VCC Current 100

1

d

Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max

2

c

Average V

3

5V, 25°C, Typical

d

Average V

4

AutoStore™ Cycle

e

Average V

1

(Standby, Cycling TTL Input Levels)

e

V

2

CC

(Standby, Stable CMOS Input Levels)

Current at t

CC

Current during

CAP

Current

CC

Standby Current

AVAV

= 200ns

Input Leakage Current

Off-State Output Leakage Current

Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Logic “0” Voltage on HSB Output 0.4 0.4 V I
Operating Temperature 0 70 –40 85 °C

Note b: The STK12C68-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
Note d: I
Note e: E
Note f: V

and I

CC

1

and I

CC

2

≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.

reference levels throughout this datasheet refer to V

CC

nected to ground.

are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

CC

3

are the average currents required for the duration of the respective STORE cycles (t

CC

4

COMMERCIAL INDUSTRIAL

MIN MAX MIN MAX

N/A
90
75
65

90
75
65

10 10 mA

22mA

32
27
23
20

N/A

28
24
21

1.5 1.5 mA

±1 ±1 µA

±5 ±5 µA

if that is where the power supply connection is made, or V

CCX

UNITS NOTES

mA
mA
mA
mA

t

= 20ns

AVAV

t

= 25ns

AVAV

t

= 35ns

AVAV

t

= 45ns

AVAV

W

≥ (V

– 0.2V)

CC

All Others Cycling, CMOS Levels
All Inputs Don’t Care

STORE

t

= 20ns, E ≥ V

AVAV

t

= 25ns, E ≥ V

AVAV

t

= 35ns, E ≥ V

AVAV

t

= 45ns, E ≥ V

AVAV

E

≥ (VCC – 0.2V)

All Others V
V

= max

CC

V

= VSS to V

IN

V

= max

CC

V

= VSS to VCC, E or G ≥ VIH

IN

= – 4mA except HSB

OUT

= 8mA except HSB

OUT

= 3mA

OUT

IH
IH
IH
IH

≤ 0.2V or ≥ (VCC – 0.2V)

IN

CC

).

CAP

mA
mA
mA
mA

if V

CCX

is con-

b, f

AC TEST CONDITIONS

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V

Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns

Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

g

CAPACITANCE

(TA = 25°C, f = 1.0MHz)

SYMBOL PARAMETER MAX UNITS CONDITIONS

C

IN

C

OUT

Input Capacitance 8 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V

Note g: These parameters are guaranteed but not tested.

July 1999 4-42

OUTPUT

5.0V

480 Ohms

255 Ohms

30 pF

INCLUDING
SCOPE AND
FIXTURE

Figure 1: AC Output Loading

STK12C68

SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)

NO.

1t
2t
3t
4t
5t
6t
7t
8t

9t
10 t
11 t

SYMBOLS

#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX

ELQV

AVAV

AVQV

GLQV

AXQX

ELQX

EHQZ

GLQX

GHQZ

ELICCH

EHICCL

t

h

i

i

j

j

ACS

t

RC

t

AA

t

OE

t

OH

t

LZ

t

HZ

t

OLZ

t

OHZ

g

t

PA

g

t

PS

Chip Enable Access Time 20 25 35 45 ns
Read Cycle Time 20 25 35 45 ns
Address Access Time 22 25 35 45 ns
Output Enable to Data Valid 8 10 15 20 n s
Output Hold after Address Change 5 5 5 5 ns
Chip Enable to Output Active 5 5 5 5 ns
Chip Disable to Output Inactive 7 10 13 15 ns
Output Enable to Output Active 0 0 0 0 ns
Output Disable to Output Inactive 7 10 13 15 n s
Chip Enable to Power Active 0 0 0 0 ns
Chip Disable to Power Standby 25 25 35 45 ns

PARAMETER

Note h: W and HSB must be high during SRAM READ cycles.
Note i: Device is continuously selected with E

and G both low.

Note j: Measured ± 200mV from steady state output voltage.

SRAM READ CYCLE #1: Address Controlledh,

ADDRESS

5

t

DQ (DATA OUT)

AXQX

STK12C68-20 STK12C68-25 STK12C68-35 STK12C68-45

i

2

t

AVAV

3

t

AVQV

DATA V A LID

UNITS

b, f

SRAM READ CYCLE #2: E Controlled

ADDRESS

t

ELQX

10

t

ELICCH

6

t

GLQX

4

t

GLQV

8

DQ (DATA OUT)

I

CC

E

G

STANDBY

h

t

AVAV

2

1

t

ELQV

ACTIVE

DATA VALID

9

t

GHQZ

t

EHQZ

t

7

11

EHICCL

July 1999 4-43

STK12C68

SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V ± 10%)b,

NO.

12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t

WLWH

ELWH

DVWH

WHDX

AVWH

AVWL

WHAX

WLQZ

WHQX

Note k: If W is low when E goes low, the outputs remain in the high-impedance state.
Note l: E

or W must be ≥ V

Note m: HSB

SRAM WRITE CYCLE #1: W Controlled

SYMBOLS

#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX

AVAV

j, k

t

AVAV

t

WLEH

t

ELEH

t

DVEH

t

EHDX

t

AVEH

t

AVEL

t

EHAX

must be high during SRAM WRITE cycles.

t

Write Cycle Time 20 25 35 45 n s

WC

t

Write Pulse Width 15202530 ns

WP

t

Chip Enable to End of Write 15 20 25 30 ns

CW

t

Data Set-up to End of Write 8 10 12 15 ns

DW

t

Data Hold after End of Write 0 0 0 0 ns

DH

t

Address Set-up to End of Write 15 20 25 30 ns

AW

t

Address Se t-up to Start of Write 0 0 0 0 ns

AS

t

Address Ho l d after End of Write 0 0 0 0 ns

WR

t

Write Enable to Output Disable 7 10 13 15 ns

WZ

t

Output Active after End of Write 5 5 5 5 ns

OW

during address transitions.

IH

PARAMETER

l, m

t

ADDRESS

14

t

ELWH

E

STK12C68-20 STK12C68-25 STK12C68-35 STK12C68-45

12

AVAV

19

t

WHAX

UNITS

f

17

t

20

t

WLQZ

AVWH

13

t

WLWH

W

DATA IN

DA TA OUT

18

t

AVWL

PREVIOUS DATA

SRAM WRITE CYCLE #2: E Controlled

ADDRESS

18

t

E

W

DATA IN

AVEL

t

AVEH

17

l, m

12

t

AVAV

14

t

ELEH

t

13

WLEH

15

t

DVWH

DATA V A LID

HIGH IMPEDANCE

15

t

DVEH

DATA V A LID

16

t

WHDX

19

t

EHAX

16

t

EHDX

21

t

WHQX

DA TA OUT

HIGH IMPEDANCE

July 1999 4-44