Datasheet STK12C68-P45I, STK12C68-P35I, STK12C68-P35, STK12C68-P25, STK12C68-W35I Datasheet (SIMTEK)
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STK12C68
FEATURES
• 25ns, 35ns, 45ns and 55ns Access Times
STORE
• “Hands-off” Automatic
68µF Capacitor on Power Down
•
STORE
Software or
•
RECALL
to EEPROM Initiated by Hardware,
AutoStore
™ on Power Down
to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
at 200ns Cycle Time
CC
• Unlimited READ, WRITE and
• 1,000,000
STORE
Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• Single 5V
+ 10% Operation
• Not Sensitive to Power On/Off Ramp Rates
• No Data Loss from Undershoot
• Commercial and Industrial Temperatures
• 28-Pin SOIC and DIP Packages
with External
RECALL
Cycles
8K x 8
Nonvolatile Static RAM
DESCRIPTION
The Simtek STK12C68 is a fast static RAM with a
nonvolatile, electrically erasable
incorporated in each static memory cell. The
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the
matically on power down. A 68µF or larger capacitor
tied from V
operation, regardless of power-down slew rate or
loss of power from “hot swapping”. Transfers from
the
take place automatically on restoration of power. Initiation of
software controlled by entering specific read
sequences. A hardware
the
AutoStore
™ nvSRAM
QuantumTrap
STORE
operation) can take place auto-
to ground guarantees the
CAP
EEPROM to the SRAM (the
STORE
HSB pin.
and
RECALL
STORE
™ CMOS
PROM element
SRAM
STORE
RECALL
cycles can also be
may be initiated with
operation)
BLOCK DIAGRAM
V
CCXVCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
SOFTWARE
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
EEPROM ARRAY
ARRAY
2
A3A
128 x 512
A
A
4
STORE
RECALL
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
0
1
2
3
4
5
6
7
STATIC RAM
ROW DECODER
COLUMN I/O
COLUMN DEC
A0A
INPUT BUFFERS
128 x 512
1
March 2000 4-41
DETECT
PIN CONFIGURATIONS
1
HSB
A0-A
V
CAP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
12
28
V
2
3
4
5
6
7
8
9
10
11
12
13
14
CC
27
W
26
HSB
25
A
8
A
24
9
A
23
11
22
G
21
A
10
20
E
19
DQ
7
18
17
16
15
28 - 300 PDIP
DQ
6
DQ
28 - 600 PDIP
5
DQ
4
28 - 350 SOIC
DQ
3
28 - 300 CDIP
PIN NAMES
A0 - A
DQ
E Chip Enable
W Write Enable
G
E
W
G Output Enable
HSB Hardware Store Busy (I/O)
V
CCX
V
CAP
V
SS
Address Inputs
12
-DQ7Data In/Out
0
Power (+ 5V)
Capacitor
Ground
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V)
Voltage on DQ
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)
0-7
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
SYMBOL PARAMETER
c
I
I
I
I
I
I
I
I
V
V
V
V
V
T
Note b: Note c: I Note d: I Note e: Note f: V
Average VCC Current 90
CC
1
d
Average VCC Current during
CC
2
c
Average VCCCurrent at t
CC
3
5V, 25˚C, Typical
d
Average V
CC
4
AutoStore
e
Average VCCCurrent
SB
1
(Standby, Cycling TTL Input Levels)
e
VCCStandby Current
SB
2
(Standby, Stable CMOS Input Levels)
Input Leakage Current
ILK
Off-State Output Leakage Current
OLK
Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
IH
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
IL
Output Logic “1” Voltage 2.4 2.4 V I
OH
Output Logic “0” Voltage 0.4 0.4 V I
OL
Logic “0” Voltage onHSB Output 0.4 0.4 V I
BL
Operating Temperature 0 70 –40 85 °C
A
and I
CC
1
and I
CC
2
E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
reference levels throughout this datasheet refer to V
CC
nected to ground.
Current during
CAP
™ Cycle
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
are the average currents required for the duration of the respective
CC
4
AVAV
STORE
= 200ns
COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX
90
75
65
55
75
65
55
3 3 mA All Inputs Don’t Care, VCC = max
10 10 mA
22mA
27
23
20
19
28
24
21
20
1.5 1.5 mA
±1 ±1 µA
±5 ±5 µA
STORE
if that is where the power supply connection is made, or V
CCX
UNITS NOTES
t
mA
mA
mA
mA
= 25ns
AVAV
t
= 35ns
AVAV
t
= 45ns
AVAV
t
= 55ns
AVAV
W ≥ (VCC– 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
t
mA
mA
mA
mA
cycles (t
STORE
= 25ns, E ≥ V
AVAV
t
= 35ns, E ≥ V
AVAV
t
= 45ns, E ≥ V
AVAV
t
= 55ns, E ≥ V
AVAV
E ≥ (VCC – 0.2V)
All Others V
VCC= max
V
= VSS to V
IN
VCC= max
V
= VSS to VCC, E or G ≥ V
IN
=– 4mA except HSB
OUT
= 8mA except HSB
OUT
= 3mA
OUT
).
IH
IH
IH
IH
≤ 0.2V or ≥ (VCC – 0.2V)
IN
CC
IH
if V
CCX
is con-
CAP
f
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . . .1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
g
CAPACITANCE
(TA = 25°C, f = 1.0MHz)
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
Input Capacitance 8 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V
Note g: These parameters are guaranteed but not tested.
March 2000 4-42
OUTPUT
5.0V
480 Ohms
255 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)
NO.
1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
Note h: W and HSB must be high during SRAM READ cycles.
Note i: Device is continuously selected with
Note j: Measured ± 200mV from steady state output voltage.
SYMBOLS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
t
ACS
h
t
RC
i
t
AA
t
OE
i
t
OH
t
LZ
j
t
HZ
t
OLZ
j
t
OHZ
g
t
PA
g
t
PS
PARAMETER
Chip Enable Access Time 25 35 45 55 ns
Read Cycle Time 25 35 45 55 ns
Address Access Time 22 35 45 55 ns
Output Enable to Data Valid 10 15 20 25 ns
Output Hold after Address Change 5 5 5 5 ns
Chip Enable to Output Active 5 5 5 5 ns
Chip Disable to Output Inactive 10 13 15 17 ns
Output Enable to Output Active 0 0 0 0 ns
Output Disable to Output Inactive 10 13 15 17 ns
Chip Enable to Power Active 0 0 0 0 ns
Chip Disable to Power Standby 25 35 45 55 ns
E and G both low.
SRAM READ CYCLE #1: Address Controlled
ADDRESS
5
t
DQ (DATA OUT)
AXQX
STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55
h, i
2
t
AVAV
3
t
AVQV
DATA VALID
UNITS
f
SRAM READ CYCLE #2: E Controlled
ADDRESS
E
t
ELQX
6
h
t
AVAV
2
t
ELQV
1
G
4
t
GLQV
8
t
GLQX
DQ (DATA OUT)
10
t
ELICCH
I
CC
STANDBY
ACTIVE
March 2000 4-43
DATA VALID
t
GHQZ
9
t
EHQZ
7
11
t
EHICCL
SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V ± 10%)
NO.
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
Note k: If W is low when E goes low, the outputs remain in the high-impedance state.
Note l:
Note m:
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
AVAV
WLWH
ELWH
DVWH
WHDX
AVWH
AVWL
WHAX
WLQZ
WHQX
E or W must be ≥ VIHduring address transitions.
HSB must be high during SRAM WRITE cycles.
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
j, k
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
tASAddress Set-up to Start of Write 0000ns
t
WR
t
WZ
t
OW
PARAMETER
Write Cycle Time 25 35 45 55 ns
Write Pulse Width 20 25 30 35 ns
Chip Enable to End of Write 20 25 30 35 ns
Data Set-up to End of Write 10 12 15 17 ns
Data Hold after End of Write 0000ns
Address Set-up to End of Write 20 25 30 35 ns
Address Hold after End of Write 0000ns
Write Enable to Output Disable 10 13 15 17 ns
Output Active after End of Write 5555ns
SRAM WRITE CYCLE #1: W Controlled
ADDRESS
t
t
AVWH
17
13
t
WLWH
ELWH
DATA IN
DATA OUT
E
18
t
AVWL
W
20
t
WLQZ
PREVIOUS DATA
STK12C68-25 STK12C68-45 STK12C68-35 STK12C68-55
l, m
12
t
AVAV
14
15
t
DVWH
DATA VALID
HIGH IMPEDANCE
t
16
t
WHDX
19
WHAX
21
t
WHQX
UNITS
f
SRAM WRITE CYCLE #2: E Controlled
ADDRESS
18
t
E
W
AVEL
t
AVEH
17
l, m
t
AVAV
12
14
t
ELEH
t
WLEH
DATA IN
DATA OUT
HIGH IMPEDANCE
March 2000 4-44
19
t
EHAX
13
15
t
DVEH
DATA VALID
t
EHDX
16
HARDWARE MODE SELECTION
E W HSB A12 - A0 (hex) MODE I/O POWER NOTES
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active p
L L H X Write SRAM Input Data Active
X X L X Nonvolatile
0000
1555
LHH
LHH
Note n: HSB
Note o: The six consecutive addresses must be in the order listed.
Note p: I/O state assumes
HARDWARE
NO.
22 t
23 t
24 t
25 t
26 t
Note q: E and G low for output behavior.
Note r:
Note s: t
HARDWARE
STORE
the part will go into standby mode, inhibiting all operations until
operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the
G < VIL. Activation of nonvolatile cycles does not depend on state ofG.
STORE
SYMBOLS
Standard Alternate MIN MAX
STORE
DELAY
RECOVER
HLHX
HLBL
E and G low and W high for output behavior.
is only applicable after t
RECOVER
t
HLHZ
t
HLQZ
t
HHQX
STORE
HSB (IN)
0AAA
1FFF
10F0
0F0F
0000
1555
0AAA
1FFF
10F0
0F0E
CYCLE (VCC = 5.0V ± 10%)
STORE
Cycle Duration 10 ms j, q
Time Allowed to Complete SRAM Cycle 1 µs j, r
Hardware
STORE
High to Inhibit Off 700 ns q, s
Hardware
STORE
Pulse Width 15 ns
Hardware
STORE
Low to Store Busy 300 ns
is complete.
STORE
CYCLE
25
t
HLHX
Nonvolatile
STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
STORE
Nonvolatile
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
RECALL
HSB rises.
W must be high during all six consecutive cycles to enable a nonvolatile cycle.
PARAMETER
22
t
STORE
Output High Z l
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
STORE
STK12C68
24
t
RECOVER
CC
2
Active
l
CC
2
Active
(if any) completes,
UNITS NOTES
n
o, p
o, p
f
26
t
DATA VALID
HLBL
23
t
DELAY
HSB (OUT)
DQ (DATA OUT)
HIGH IMPEDANCE
March 2000 4-45
HIGH IMPEDANCE
DATA VALID
AutoStore
NO.
27 t
28 t
29 t
30 t
31 V
32 V
Note t: t
Note u:
™/POWER-UP
SYMBOLS
Standard Alternate MIN MAX
RESTORE
STORE
VSBL
DELAY
SWITCH
RESET
starts from the time VCC rises above V
RESTORE
HSB is asserted low for 1µs when V
will be released and no
t
HLHZ
t
BLQZ
STORE
RECALL
PARAMETER
Power-up
RECALL
Duration 550 µst
STORE
Cycle Duration 10 ms q, r, u
Low Voltage Trigger (V
Time Allowed to Complete SRAM Cycle 1 µsq
Low Voltage Trigger Level 4.0 4.5 V
Low Voltage Reset Level 3.9 V
SWITCH
drops through V
CAP
will take place.
) to HSB Low 300 ns m
SWITCH
.
. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB
SWITCH
(VCC = 5.0V ± 10%)
STK12C68
UNITS NOTES
f
AutoStore
31
V
SWITCH
32
V
RESET
AutoStore
POWER-UP
RECALL
DQ (DATA OUT)
™/POWER-UP
V
CC
TM
27
t
HSB
W
RESTORE
RECALL
t
VSBL
29
30
t
DELAY
28
t
STORE
POWER-UP
RECALL
BROWN OUT
NO
STORE
(NO SRAM WRITES)
NO
RECALL
(VCC DID NOT GO
BELOW V
RESET
)
March 2000 4-46
BROWN OUT
AutoStore
™
NO
RECALL
(VCC DID NOT GO
BELOW V
RESET
BROWN OUT
AutoStore
RECALL
V
CC
)
ABOVE V
™
WHEN
RETURNS
SWITCH
SOFTWARE-CONTROLLED
NO.
33 t
34 t
35 t
36 t
37 t
Note v: The software sequence is clocked with E controlled READs.
Note w: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table:(0000, 1555, 0AAA, 1FFF,10F0, 0F0F) for a
SOFTWARE
SYMBOLS
Standard Alternate MIN MAX MIN MAX MIN MAX MIN MAX
AVAV
AVEL
ELEH
ELAX
RECALL
STORE
t
t
t
cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a
STORE/RECALL
RC
Address Set-up Time 0 0 0 0 ns v
AS
Clock Pulse Width 20 25 30 35 ns v
CW
Address Hold Time 20 20 20 20 ns v
RECALL
STORE/RECALL
ADDRESS
STORE/RECALL
PARAMETER
Initiation Cycle Time 25 35 45 55 ns q
Duration 20 20 20 20 µs
CYCLE
STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55
RECALL
cycle. W must be high during all six consecutive cycles.
CYCLE: E Controlled
33
t
AVAV
w
(VCC = 5.0V ± 10%)
UNITS NOTES
w
33
t
AVAV
ADDRESS #6ADDRESS #1
f
DQ (DATA OUT)
34
t
E
AVEL
35
t
ELEH
36
t
ELAX
DATA VALID
DATA VALID
28 37
t
/ t
STORE
HIGH IMPEDANCE
RECALL
March 2000 4-47
DEVICE OPERATION
The STK12C68 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static
RAM. In nonvolatile mode, data is transferred
from
SRAM to EEPROM (the
from
EEPROM to SRAM (the
this mode
SRAM functions are disabled.
STORE
RECALL
operation) or
operation). In
NOISE CONSIDERATIONS
The STK12C68 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between V
V
, using leads and traces that are as short as pos-
SS
sible. As with all high-speed
CMOS ICs, normal care-
CAP
and
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK12C68 performs a READ cycle whenever E
and
G are low and W and HSB are high. The
address specified on pins A
determines which of
0-12
the 8,192 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of t
#1). If the
be valid at t
READ is initiated by EorG, the outputs will
ELQV
or at t
, whichever is later (READ
GLQV
(READ cycle
AVQV
cycle #2). The data outputs will repeatedly respond
to address changes within the t
access time with-
AVQV
out the need for transitions on any control input pins,
and will remain valid until another address change or
until
EorG is brought high, or WorHSB is brought
low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and
stable prior to entering the
remain stable until either
end of the cycle. The data on the common I/O pins
DQ
before the end of a W controlled WRITE or t
before the end of an E controlled WRITE.
It is recommended that
entire
common I/O lines. If
will turn off the output buffers t
HSB is high. The address inputs must be
WRITE cycle and must
EorW goes high at the
will be written into the memory if it is valid t
0-7
G be kept high during the
WRITE cycle to avoid data bus contention on
G is left low, internal circuitry
after W goes low.
WLQZ
DVWH
DVEH
POWER-UP
RECALL
During power up, or after any low-power condition
(V
CAP<VRESET
latched. When V
voltage of V
be initiated and will take t
If the STK12C68 is in a
power-up
), an internal
CAP
SWITCH
RECALL
RECALL
request will be
once again exceeds the sense
,a
RECALL
cycle will automatically
to complete.
RESTORE
WRITE state at the end of
, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between
V
or between E and system VCC.
CC
SOFTWARE NONVOLATILE
The STK12C68 software
executing sequential
six specific address locations. During the
STORE
E controlled READ cycles from
W and system
STORE
cycle is initiated by
STORE
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile elements. The program operation copies the
SRAM data into nonvolatile memory. Once a
STORE
cycle is initiated, further input and output are disabled until the cycle is completed.
Because a sequence of READs from specific
addresses is used for
tant that no other
STORE
initiation, it is impor-
READ or WRITE accesses inter-
vene in the sequence, or the sequence will be
aborted and no
To initiate the software
READ sequence must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0F (hex) Initiate
STORE
or
STORE
RECALL
will take place.
cycle, the following
STORE
cycle
The software sequence must be clocked with E controlled
READs.
Once the sixth address in the sequence has been
entered, the
chip will be disabled. It is important that
and not
although it is not necessary that
sequence to be valid. After the t
been fulfilled, the
READ and WRITE operation.
STORE
cycle will commence and the
READ cycles
WRITE cycles be used in the sequence,
Gbelowforthe
cycle time has
SRAM will again be activated for
STORE
March 2000 4-48
SOFTWARE NONVOLATILE
A software
of
READ operations in a manner similar to the soft-
ware
the following sequence of
RECALL
STORE
initiation. To initiate the
cycle is initiated with a sequence
E controlled READ opera-
RECALL
RECALL
cycle,
tions must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0E (hex) Initiate
Internally,
RECALL
is a two-step procedure. First, the
RECALL
cycle
SRAM data is cleared, and second, the nonvolatile
information is transferred into the
the t
ready for
cycle time the SRAM will once again be
RECALL
READ and WRITE operations. The
SRAM cells. After
RECALL
operation in no way alters the data in the EEPROM
cells. The nonvolatile data can be recalled an unlimited number of times.
AutoStore
™ OPERATION
The STK12C68 can be powered in one of three
modes.
During normal
STK12C68 will draw current from V
capacitor connected to the V
AutoStore
™ operation, the
to charge a
CCX
pin. This stored
CAP
charge will be used by the chip to perform a single
STORE
operation. After power up, when the voltage
on the V
automatically disconnect the V
initiate a
pin drops below V
CAP
STORE
operation.
SWITCH
pin from V
CAP
, the part will
and
CCX
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68µF and
220µF (± 20%) rated at 6V should be provided.
In system power mode (Figure 3), both V
V
are connected to the + 5V power supply without
CAP
the 68µF capacitor. In this mode the
AutoStore
CCX
and
™
function of the STK12C68 will operate on the stored
system charge as power goes down. The user must,
however, guarantee that V
3.6V during the 10ms
If an automatic
then V
V
CAP
can be tied to ground and + 5V applied to
CCX
(Figure 4). This is the
mode, in which the
STORE
STORE
on power loss is not required,
AutoStore
does not drop below
CCX
cycle.
AutoStore
™ Inhibit
™ function is disabled.
If the STK12C68 is operated in this configuration,
references to V
throughout this data sheet. In this mode,
should be changed to V
CCX
CAP
STORE
operations may be triggered through software control or the
HSB pin. It is not permissable to change
between these three options “on the fly”.
In order to prevent unneeded
automatic
externally driving
least one
most recent
initiated
whether a
STORE
s as well as those initiated by
HSB low will be ignored unless at
WRITE operation has taken place since the
STOREorRECALL
STORE
cycles are performed regardless of
WRITE operation has taken place. An
optional pull-up resistor is shown connected to
STORE
operations,
cycle. Software-
HSB.
This can be used to signal the system that the
AutoStore
™ cycle is in progress.
1
Bypass
14
+
68µF
6v, 20%
Figure 2:
0.1µF
Bypass
1
14
AutoStore
28
27
26
15
™ Mode
10kΩ
10kΩ∗
0.1µF
Figure 3: System Power Mode
*If HSB is not used, it should be left unconnected.
March 2000 4-49
0.1µF
0.1µF
Bypass
10kΩ
28
27
26
15
10kΩ∗
Bypass
Figure 4:
Figure 4:
1
1
28
28
27
27
26
26
14
14
15
15
AutoStore
AutoStore
Inhibit Mode
Inhibit Mode
10kΩ
10kΩ
10kΩ∗
10kΩ∗
™
™
HSB OPERATION
The STK12C68 provides the HSB pin for controlling
and acknowledging the
pin is used to request a hardware
When the
HSB pin is driven low, the STK12C68 will
conditionally initiate a
an actual
the
RECALL
STORE
SRAM took place since the last
cycle. The HSB pin acts as an open drain
driver that is internally driven low to indicate a busy
condition while the
is in progress.
SRAM READ and WRITE operations that are in
progress when
HSB is driven low by any means are
given time to complete before the
is initiated. After
continue
multiple
WRITE is in progress when HSB is pulled low it will
SRAM operations for t
SRAM READ operations may take place. If a
be allowed a time, t
SRAM WRITE cycles requested after HSB goes low
will be inhibited until
HSB pin can be used to synchronize multiple
The
STK12C68s while using a single larger capacitor. To
operate in this mode the
nected together to the
STK12C68s. An external pull-up resistor to + 5V is
required since
The V
CAP
HSB acts as an open drain pull down.
pins from the other STK12C68 parts can
be tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
STK12C68s detects a power loss and asserts
the common
a
STORE
HSB pin will cause all parts to request
cycle (a
STK12C68s that have been written since the last
nonvolatile cycle).
During any
STORE
was initiated, the STK12C68 will continue to drive
the
HSB pin low,releasing it only when the
complete. Upon completion of the
the STK12C68 will remain disabled until the
pin returns high.
If HSB is not used, it should be left unconnected.
STORE
operations. The HSB
STORE
STORE
operation after t
cycle.
DELAY
cycle will only begin if a WRITE to
STORE
STORE
(initiated by any means)
STORE
operation
HSB goes low, the STK12C68 will
. During t
DELAY
, to complete. However, any
DELAY
DELAY
HSB returns high.
HSB pin should be con-
HSB pins from the other
HSB,
STORE
will take place in those
operation, regardless of how it
STORE
STORE
operation
HSB
or
PREVENTING STORES
The
STORE
holding
30mA at a V
function can be disabled on the fly by
HSB high with a driver capable of sourcing
of at least 2.2V, as it will have to over-
OH
power the internal pull-down device that drives
low for 20µs at the onset of a
;
STK12C68 is connected for
(system V
on V
connected to V
CC
) and VCCcrosses V
CAP
the STK12C68 will attempt to pull
doesn’t actually get below V
ing to pull
HSB low and abort the
STORE
AutoStore
anda68µF capacitor
CCX
on the way down,
SWITCH
HSB low; if HSB
, the part will stop try-
IL
STORE
HARDWARE PROTECT
The STK12C68 offers hardware protection against
inadvertent
ing low-voltage conditions. When V
,
externally initiated
WRITEs are inhibited.
AutoStore
V
CCX
AutoStore
STORE
operation and SRAM WRITEs dur-
STORE
CAP<VSWITCH
operations and SRAM
™ can be completely disabled by tying
to ground and applying + 5V to V
™ Inhibit mode; in this mode,
only initiated by explicit request using either the software sequence or the
HSB pin.
LOW AVERAGE ACTIVE POWER
The STK12C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 5
shows the relationship between I
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
perature range, V
= 5.5V, 100% duty cycle on chip
CC
enable). Figure 6 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK12C68 depends on the following items:
1)
CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of
is
temperature; 6) the V
READstoWRITEs; 5) the operating
level; and 7) I/O loading.
cc
and READ cycle
CC
. When the
™ operation
attempt.
. This is the
CAP
STORE
HSB
, all
s are
March 2000 4-50
100
100
80
60
40
20
Average Active Current (mA)
0
TTL
CMOS
50 100 150 200
Cycle Time (ns)
Figure 5: Icc (max) Reads
80
60
40
20
Average Active Current (mA)
0
Figure 6: Icc (max) Writes
TTL
CMOS
50 100 150 200
Cycle Time (ns)
March 2000 4-51
ORDERING INFORMATION
STK12C68 - P 45 I
Temperature Range
Blank = Commercial (0 to 70˚C)
I = Industrial (-40 to 85˚C)
Access Time
25 = 25ns (Commercial only)
45 = 35ns
45 = 45ns
55 = 55ns
Package
P = Plastic 28-pin 300 mil DIP
W = Plastic 28-pin 600 mil DIP
S = Plastic 28-pin 350 mil SOIC
C = Ceramic 28-pin 300 mil DIP
March 2000 4-52
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