SIMTEK STK12C68-C35IM, STK12C68-C25IM, STK12C68-L45IM, STK12C68-L25IM, STK12C68-L35IM Datasheet

STK12C68-IM

A
A
A
A
A
A

A

A
A
A

A

A

DQ

DQ

DQDQDQ

DQ
DQ

G

A
E

DQ

Vss

V

W

HSB

7

12

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1
0
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TOP VIEW

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32128 27

26
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1716151413

V

CAP

CCX

STK12C68-IM

CMOS nvSRAM

Industrial Temperature/Military Screen

FEATURES

• Industrial Temperature with Military Screening

• 25, 35 and 45ns Access Times

• 15 mA I

• Automatic

• Hardware or Software initiated

EEPROM

• Automatic

• 100,000

• 10 year data retention in EEPROM

• Automatic

• Software initiated

• Unlimited

• Single 5V±10% Operation

• Commercial and Industrial Temperatures

• Available in multiple standard packages

at 200ns Access Speed

CC

STORE

STORE

STORE

RECALL

RECALL

to EEPROM on Power Down

Timing

cycles to EEPROM

on Power Up

RECALL

from EEPROM

cycles from EEPROM

STORE

to

8K x 8

AutoStore™

Nonvolatile Static RAM

DESCRIPTION

The Simtek STK12C68-IM is a fast static RAM (25, 35
and 45ns), with a nonvolatile EEPROM element incor­porated in each static memory cell. The SRAM can be
read and written an unlimited number of times, while
independent nonvolatile data resides in EEPROM. Data
transfers from the SRAM to the EEPROM (the

operation) take place automatically upon power down

using charge stored in an external 100 µF capacitor.
Transfers from the EEPROM to the SRAM (the
operation) take place automatically on power up. Soft­ware sequences may also be used to initiate both

STORE

and

RECALL

operations. A

STORE

initiated via a single pin.
The STK12C68-IM is available in the following

packages: a 28-pin 300 mil ceramic DIP and a 28-pad
LCC. MIL-STD-883 and Standard Military Drawing
(SMD 5962-94599) devices are also available.

STORE

RECALL

can also be

LOGIC BLOCK DIAGRAM

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

12

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

ROW DECODER

INPUT BUFFERS

EEPROM ARRAY

256 x 256

STORE

STATIC RAM

ARRAY

256 x 256

COLUMN I/O

COLUMN DECODER

AAAAA

1210

011

RECALL

AA

0

12

STORE/
RECALL

CONTROL

41

HSB

PIN CONFIGURATIONS

1

V

CAP

2

A

12

3

A

7

4

A

6

5

A

5

6

A

4

7

A

3

8

A

2

9

A

1

10

A

0

11

DQ

0

12

DQ

1

13

DQ

2

14

V

SS

V

28

CCX

W

27
26

HSB

25

A

8

24

A

9

23

A

11

22

G

21

A

10

20

E

19

DQ

7

18

DQ

6

17

DQ

5

16

DQ

4

15

DQ

3

28 - LCC 28 - 300 CDIP

PIN NAMES

A0 - A
W Write Enable
DQ0 - DQ7Data In/Out
E Chip Enable

G

E
W

G Output Enable
V

CCX

V

SS

V

CAP

HSB Hardware Store/Busy

12

Address Inputs

Power (+5V)
Ground
Capacitor

STK12C68-IM

ABSOLUTE MAXIMUM RATINGS

Voltage on typical input relative to VSS. . . . . . . . . . . . . –0.6V to 7.0V

Voltage on DQ

Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W

DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA

and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V)

0-7

a

Note a: Stresses greater than those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

(One output at a time, one second duration)
DC CHARACTERISTICS (VCC = 5.0V ± 10%)

SYMBOL PARAMETER UNITS NOTES

b

I

I

I

I

I

I

I

I

V
V
V
V
T

CC

CC

CC

CC

SB

SB

ILK

OLK

A

Average VCC Current 95 mA t

1

Average VCC Current During

2

b

Average VCC Current 15 mA E ≤ 0.2V, W ≥ (VCC – 0.2V)

IH
IL
OH
OL

3

4

c

1

c

2

3

= 200ns others ≤ 0.2V or ≥ (VCC – 0.2V)

at t

AVAV

Average V

Average VCC Current 39 mA t
(Standby, Cycling TTL Input Levels) 35 mA t

Average VCC Current 3 mA E ≥ (VCC – 0.2V)
(Standby, Stable CMOS Input Levels) all others V
Input Leakage Current (Any Input) ±1 µAVCC = max

Off State Output Leakage Current ±5 µAVCC = max

Input Logic "1" Voltage 2.2 VCC+.5 V All Inputs
Input Logic "0" Voltage VSS–.5 0.8 V All Inputs
Output Logic "1" Voltage 2.4 V I
Output Logic "0" Voltage 0.4 V I
Operating Temperature -40 85 °C

current during AutoStore™ Cycle 4 mA All inputs ≤ 0.2V or ≥ (VCC - 0.2V)

CC

STORE

INDUSTRIAL

MIN MAX

85 mA t
80 mA t

7 mA All inputs ≤ 0.2V or ≥ (VCC - 0.2V)

32 mA t

= 25ns

AVAV

= 35ns

AVAV

= 45ns

AVAV

= 25ns

AVAV

= 35ns

AVAV

= 45ns

AVAV

; all others cycling

E ≥ V

IH

≤ 0.2V or ≥ (VCC – 0.2V)

IN

= VSS to V

V

IN

= VSS to V

V

OUT

= –4mA except HSB

OUT

= 8mA except HSB

OUT

CC

CC

d

Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: VCC reference levels throughout this datasheet refer to V

AC TEST CONDITIONS

3

1

if that is where the power supply connection is made, or V

CCX

CAP

if V

is connected to ground.

CCX

5.0V

Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V

Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V

Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

CAPACITANCEe (T

SYMBOL PARAMETER MAX UNITS CONDITIONS

C

IN

C

OUT

Note e: These parameters are guaranteed but not tested.

Input Capacitance 8 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V

=25°C, f=1.0MHz)

A

Output

255 Ohms

Figure 1: AC Output Loading

480 Ohms

30pF

INCLUDING

SCOPE

AND FIXTURE

42

SRAM MEMORY OPERATION

STK12C68-IM

READ CYCLES #1 & #2

(VCC = 5.0V ± 10%)

SYMBOLS STK12C68-25-IM STK12C68-35-IM STK12C68-45-IM

NO. PARAMETER UNITS

1t
2t
3t
4t
5t
6t
7t
8t

9t
10 t
11 t

Note c: Bringing E ≥ V

#1, #2 Alt. MIN MAX MIN MAX MIN MAX

ELQV

AVAV

AVQV

GLQV

AXQX

ELQX

EHQZ

GLQX

GHQZ

ELICCH

EHICCL

t

ACS

t

RC

g

t

AA

t

OE

t

OH

t

LZ

h

t

HZ

t

OLZ

h

t

OHZ

e

t

PA

c,e

t

PS

will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.

IH

Chip Enable Access Time 25 35 45 ns
Read Cycle Time 25 35 45 ns
Address Access Time 25 35 45 ns
Output Enable to Data Valid 10 20 25 ns
Output Hold After Address Change 5 5 5 ns
Chip Enable to Output Active 5 5 5 ns
Chip Disable to Output Inactive 10 17 20 ns
Output Enable to Output Active 0 0 0 ns
Output Disable to Output Inactive 10 17 20 ns
Chip Enable to Power Active 0 0 0 ns
Chip Disable to Power Standby 25 35 45 ns

Note e: Parameter guaranteed but not tested.
Note f: For READ CYCLE #1 and #2, W is high for entire cycle.
Note g: Device is continuously selected with E low and G low.
Note h: Measured ± 200mV from steady state output voltage.

d

READ CYCLE #1

ADDRESS

DQ (Data Out)

READ CYCLE #2

ADDRESS

E

G

DQ (Data Out)

ACTIVE

I

CC

STANDBY

f,g

f

10

t

ELICCH

t

AXQX

5

t

ELQX

2

t

AVAV

3

t

AVQV

DATA VALID

2

t

AVAV

1

t

t

GLQX

8

t

GLQV

ELQV

4

t

GHQZ

DATA VALID

9

6

t

EHQZ

7

11

t

EHICCL

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