SIMTEK STK12C68-P45, STK12C68-P25I, STK12C68-C45, STK12C68-C35I, STK12C68-C35 Datasheet
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STK12C68
8K x 8 AutoStore™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• 20ns, 25ns, 35ns and 45ns Access Times
•“Hands-off” Automatic STORE with External
68µF Capacitor on Power Down
• STORE to EEPROM Initiated by Hardware,
Software or AutoStore™ on Power Down
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
at 200ns Cycle Time
CC
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• Single 5V +
10% Operation
• Not Sensitive to Power On/Off Ramp Rates
• No Data Loss from Undershoot
• Commercial and Industrial Temperatures
• 28-Pin SOIC and DIP Packages
BLOCK DIAGRAM
V
CCXVCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
EEPROM ARRAY
128 x 512
A
5
A
6
A
7
A
8
A
9
A
11
A
12
0
1
2
3
4
5
6
7
INPUT BUFFERS
ROW DECODER
STATIC RAM
ARRAY
128 x 512
COLUMN I/O
COLUMN DEC
A0A
2
1
A3A
STORE
RECALL
A
A
10
4
DESCRIPTION
The Simtek STK12C68 is a fast static RAM with a
nonvolatile, electrically erasable
PROM element
incorporated in each static memory cell. The
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation) can take place
automatically on power down. A 68µF or larger
capacitor tied from V
STORE operation, regardless of power-down slew
to ground guarantees the
CAP
rate or loss of power from “hot swapping”. Transfers
from the
EEPROM to the SRAM (the RECALL opera-
tion) take place automatically on restoration of
power. Initiation of
STORE and RECALL cycles can
also be software controlled by entering specific read
sequences. A hardware
the HSB
pin.
STORE may be initiated with
PIN CONFIGUR ATIONS
28
V
CCX
27
W
26
HSB
25
A
8
A
24
9
A
23
11
22
G
21
A
10
20
E
19
DQ
7
18
17
16
15
Address Inputs
Chip Enable
Write Enable
Output Enable
Hardware Store Busy (I/O)
Power (+ 5V)
Capacitor
Ground
28 - 300 PDIP
DQ
6
DQ
28 - 600 PDIP
5
DQ
4
28 - 350 SOIC
DQ
3
28 - 300 CDIP
SOFTWARE
DETECT
V
1
CAP
A
2
12
3
A
7
A
4
6
A
5
5
A
6
4
A
7
3
A
8
2
A
9
DQ
DQ
DQ
V
1
A
10
0
11
0
12
1
13
2
14
SS
HSB
A0 - A
12
PIN NAMES
A0 - A
12
-DQ7Data In/Out
DQ
0
E
W
G
E
W
G
HSB
V
CCX
V
CAP
V
SS
SRAM
July 1999 4-41
STK12C68
ABSOLUTE MAXIMUM RATINGS
Volt age on Input Rel ative to VSS . . . . . . . . . .– 0.6V to (VCC + 0.5V)
Volt age on DQ
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)
0-7
a
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sec tions of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
SYMBOL PARAMETER
c
I
I
I
I
I
I
I
I
V
V
V
V
V
T
CC
CC
CC
CC
SB
SB
ILK
OLK
IH
IL
OH
OL
BL
A
Average VCC Current 100
1
d
Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max
2
c
Average V
3
5V, 25°C, Typical
d
Average V
4
AutoStore™ Cycle
e
Average V
1
(Standby, Cycling TTL Input Levels)
e
V
2
CC
(Standby, Stable CMOS Input Levels)
Current at t
CC
Current during
CAP
Current
CC
Standby Current
AVAV
= 200ns
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Logic “0” Voltage on HSB Output 0.4 0.4 V I
Operating Temperature 0 70 –40 85 °C
Note b: The STK12C68-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
Note d: I
Note e: E
Note f: V
and I
CC
1
and I
CC
2
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
reference levels throughout this datasheet refer to V
CC
nected to ground.
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
are the average currents required for the duration of the respective STORE cycles (t
CC
4
COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX
N/A
90
75
65
90
75
65
10 10 mA
22mA
32
27
23
20
N/A
28
24
21
1.5 1.5 mA
±1 ±1 µA
±5 ±5 µA
if that is where the power supply connection is made, or V
CCX
UNITS NOTES
mA
mA
mA
mA
t
= 20ns
AVAV
t
= 25ns
AVAV
t
= 35ns
AVAV
t
= 45ns
AVAV
W
≥ (V
– 0.2V)
CC
All Others Cycling, CMOS Levels
All Inputs Don’t Care
STORE
t
= 20ns, E ≥ V
AVAV
t
= 25ns, E ≥ V
AVAV
t
= 35ns, E ≥ V
AVAV
t
= 45ns, E ≥ V
AVAV
E
≥ (VCC – 0.2V)
All Others V
V
= max
CC
V
= VSS to V
IN
V
= max
CC
V
= VSS to VCC, E or G ≥ VIH
IN
= – 4mA except HSB
OUT
= 8mA except HSB
OUT
= 3mA
OUT
IH
IH
IH
IH
≤ 0.2V or ≥ (VCC – 0.2V)
IN
CC
).
CAP
mA
mA
mA
mA
if V
CCX
is con-
b, f
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
g
CAPACITANCE
(TA = 25°C, f = 1.0MHz)
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
Input Capacitance 8 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V
Note g: These parameters are guaranteed but not tested.
July 1999 4-42
OUTPUT
5.0V
480 Ohms
255 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
STK12C68
SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)
NO.
1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
SYMBOLS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
t
h
i
i
j
j
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
g
t
PA
g
t
PS
Chip Enable Access Time 20 25 35 45 ns
Read Cycle Time 20 25 35 45 ns
Address Access Time 22 25 35 45 ns
Output Enable to Data Valid 8 10 15 20 n s
Output Hold after Address Change 5 5 5 5 ns
Chip Enable to Output Active 5 5 5 5 ns
Chip Disable to Output Inactive 7 10 13 15 ns
Output Enable to Output Active 0 0 0 0 ns
Output Disable to Output Inactive 7 10 13 15 n s
Chip Enable to Power Active 0 0 0 0 ns
Chip Disable to Power Standby 25 25 35 45 ns
PARAMETER
Note h: W and HSB must be high during SRAM READ cycles.
Note i: Device is continuously selected with E
and G both low.
Note j: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledh,
ADDRESS
5
t
DQ (DATA OUT)
AXQX
STK12C68-20 STK12C68-25 STK12C68-35 STK12C68-45
i
2
t
AVAV
3
t
AVQV
DATA V A LID
UNITS
b, f
SRAM READ CYCLE #2: E Controlled
ADDRESS
t
ELQX
10
t
ELICCH
6
t
GLQX
4
t
GLQV
8
DQ (DATA OUT)
I
CC
E
G
STANDBY
h
t
AVAV
2
1
t
ELQV
ACTIVE
DATA VALID
9
t
GHQZ
t
EHQZ
t
7
11
EHICCL
July 1999 4-43
STK12C68
SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V ± 10%)b,
NO.
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
WLWH
ELWH
DVWH
WHDX
AVWH
AVWL
WHAX
WLQZ
WHQX
Note k: If W is low when E goes low, the outputs remain in the high-impedance state.
Note l: E
or W must be ≥ V
Note m: HSB
SRAM WRITE CYCLE #1: W Controlled
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
AVAV
j, k
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
must be high during SRAM WRITE cycles.
t
Write Cycle Time 20 25 35 45 n s
WC
t
Write Pulse Width 15202530 ns
WP
t
Chip Enable to End of Write 15 20 25 30 ns
CW
t
Data Set-up to End of Write 8 10 12 15 ns
DW
t
Data Hold after End of Write 0 0 0 0 ns
DH
t
Address Set-up to End of Write 15 20 25 30 ns
AW
t
Address Se t-up to Start of Write 0 0 0 0 ns
AS
t
Address Ho l d after End of Write 0 0 0 0 ns
WR
t
Write Enable to Output Disable 7 10 13 15 ns
WZ
t
Output Active after End of Write 5 5 5 5 ns
OW
during address transitions.
IH
PARAMETER
l, m
t
ADDRESS
14
t
ELWH
E
STK12C68-20 STK12C68-25 STK12C68-35 STK12C68-45
12
AVAV
19
t
WHAX
UNITS
f
17
t
20
t
WLQZ
AVWH
13
t
WLWH
W
DATA IN
DA TA OUT
18
t
AVWL
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlled
ADDRESS
18
t
E
W
DATA IN
AVEL
t
AVEH
17
l, m
12
t
AVAV
14
t
ELEH
t
13
WLEH
15
t
DVWH
DATA V A LID
HIGH IMPEDANCE
15
t
DVEH
DATA V A LID
16
t
WHDX
19
t
EHAX
16
t
EHDX
21
t
WHQX
DA TA OUT
HIGH IMPEDANCE
July 1999 4-44
STK12C68
HARDWARE MODE SELECTION
E W HSB A12 - A0 (hex) MODE I/O POWER NOTES
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active p
L L H X Write SRAM Input Data Active
X X L X Nonvolatile STORE Output High Z l
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
LHH
LHH
0000
1555
0AAA
1FFF
10F0
0F0F
0000
1555
0AAA
1FFF
10F0
0F0E
CC
Active
l
CC
Active
2
2
n
o, p
o, p
Note n: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,
Note o: The six consecutive addresses must be in the order listed. W
the part will go into standby mode, inhibiting all operations until HSB
Note p: I/O state assumes G
< VIL. Activation of nonvolatile cycles does not depend on state of G.
rises.
must be high during all six consecutive cycles to enable a nonvolatile cycle.
HARDWARE STORE CYCLE (VCC = 5.0V ± 10%)b,
NO.
22 t
23 t
24 t
25 t
26 t
SYMBOLS
Standard Alternate MIN MAX
STORE
DELAY
RECOVER
HLHX
HLBL
t
HLHZ
t
HLQZ
t
HHQX
Note q: E and G low for output behavior.
Note r: E
Note s: t
and G low and W high for output behavior.
RECOVER
is only applicable after t
PARAMETER
STORE Cycle Duration 10 ms j, q
Time Allowed to Complete SRAM Cycle 1 µsj, r
Hardware STORE High to Inhibit Off 700 ns q, s
Hardware STORE Pulse Width 15 ns
Hardware STORE Low to Store Busy 300 ns
is complete.
STORE
STK12C68
UNITS NOTES
HARDWARE STORE CYCLE
25
t
HLHX
HSB (IN)
24
t
RECOVER
22
t
STORE
f
26
t
HSB (OUT)
DQ (DATA OUT)
HIGH IMPEDANCE
HLBL
DATA VALID
23
t
DELAY
July 1999 4-45
HIGH IMPEDANCE
DATA VALID
STK12C68
AutoStore™/POWER-UP RECALL (VCC = 5.0V ± 10%)b,
NO.
27 t
28 t
29 t
30 t
31 V
32 V
Note t: t
Note u: HSB
RESTORE
will be released and no STORE will take place.
SYMBOLS
Standard Alternate MIN MAX
RESTORE
STORE
VSBL
DELAY
SWITCH
RESET
t
HLHZ
t
BLQZ
starts from the time VCC rises above V
is asserted low for 1µs when V
Power-up RECALL Duration 550 µst
STORE Cycle Duration 10 ms q, r, u
Low Voltage Trigger (V
Time Allowed to Complete SRAM Cycle 1 µsq
Low Voltage Trigger Level 4.0 4.5 V
Low Voltage Reset Level 3.9 V
SWITCH
drops through V
CAP
PARAMETER
) to HSB Low 300 ns m
SWITCH
.
. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB
SWITCH
STK12C68
UNITS NOTES
AutoStore™/POWER-UP RECALL
V
CC
31
V
SWITCH
32
V
RESET
f
AutoStore
POWER-UP RECALL
HSB
DQ (DATA OUT)
TM
27
t
RESTORE
W
POWER-UP
RECALL
BROWN OUT
NO STORE
29
t
VSBL
30
t
DELAY
BROWN OUT
AutoStore™
28
t
STORE
BROWN OUT
AutoStore™
(NO SRAM WRITES)
NO RECALL
(V
DID NOT GO
CC
BELOW V
RESET
)
NO RECALL
(V
DID NOT GO
CC
BELOW V
RESET
RECALL WHEN
V
RETURNS
CC
)
ABOVE V
SWITCH
July 1999 4-46
STK12C68
SOFTW ARE-CONTROLLED STORE/RECALL CYCLE
NO.
33 t
34 t
35 t
36 t
37 t
SYMBOLS
Standard Alternate MIN MAX MIN MAX MIN MAX MIN MAX
AVAV
AVEL
ELEH
ELAX
RECALL
t
RC
t
AS
t
CW
STORE/RECALL In itiation Cycle
Time
Address Set-up Time 0 0 0 0 ns v
Clock Pulse Width 15202530nsv
Address Hold Time 15 20 20 20 ns v
RECALL Duration 20 20 20 20 µs
PARAMETER
STK12C68-20 STK12C68-25 STK12C68-35 STK12C68-45
20 25 35 45 ns q
w
(VCC = 5.0V ± 10%)b,
UNITS NOTES
Note v: The software sequence is clocked with E controlled READs.
Note w: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for
a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W
SOFTWARE STORE/RECALL CYCLE: E Controlled
33
t
AVAV
ADDRESS
34
t
AVEL
E
35
t
ELEH
must be high during all six consecutive cycles.
w
33
t
AVAV
ADDRESS #6ADDRESS #1
f
DQ (DATA OUT)
36
t
ELAX
DATA VALID
DATA V A LID
28 37
t
/ t
STORE
HIGH IMPEDANCE
RECALL
July 1999 4-47
STK12C68
DEVICE OPERATION
The STK12C68 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static
RAM. In nonvolatile mode, data is transferred
from
SRAM to EEPROM (the STORE operation) or
from
EEPROM to SRAM (the RECALL operation). In
this mode
SRAM functions are disabled.
NOISE CONSIDERATIONS
The STK12C68 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between V
V
, using leads and traces that are as short as pos-
SS
sible. As with all high-speed
CMOS ICs, normal care-
CAP
and
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK12C68 performs a READ cycle whenever E
and G are low and W and HSB are high. The
address specified on pins A
determines which of
0-12
the 8,192 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of t
#1). If the
will be valid at t
(
READ cycle #2). The data outputs will repeatedly
READ is initiated by E or G, the outputs
ELQV
or at t
, whichever is later
GLQV
respond to address changes within the t
(READ cycle
AVQV
AVQV
access
time without the need for transitions on any control
input pins, and will remain valid until another address
change or until E
or G is brought high, or W or HSB is
brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB
stable prior to entering the
remain stable until either E
end of the cycle. The data on the common I/O pins
DQ
will be written into the memory if it is valid t
0-7
before the end of a W controlled WRITE or t
before the end of an E controlled WRITE.
It is recommended that G
entire
WRITE cycle to avoid data bus contention on
common I/O lines. If G
will turn off the output buffers t
is high. The address inputs must be
WRITE cycle and must
or W goes high at the
DVWH
DVEH
be kept high during the
is left low, internal circuitry
after W goes low.
WLQZ
POWER-UP RECALL
During power up, or after any low-power condition
(V
< V
CAP
latched. When V
voltage of V
be initiated and will take t
If the STK12C68 is in a
power-up
), an internal RECALL request will be
RESET
once again exceeds the sense
CAP
, a RECALL cycle will automatically
SWITCH
RESTORE
RECALL, the SRAM data will be corrupted.
to complete.
WRITE state at the end of
To help avoid this situation, a 10K Ohm resistor
should be connected either between W
V
or between E and system VCC.
CC
and system
SOFTWARE NONVOLATILE STORE
The STK12C68 software STORE cycle is initiated by
executing sequential
six specific address locations. During the
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile elements. The program operation copies the
SRAM data into nonvolatile memory. Once a STORE
cycle is initiated, further input and output are disabled until the cycle is completed.
Because a sequence of READs from specific
addresses is used for
tant that no other
vene in the sequence, or the sequence will be
aborted and no
To initiate the software
READ sequence must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Vali d REA D
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0F (hex) Initiate STORE cycle
The software sequence must be clocked with E controlled
READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that
and not
WRITE cycles be used in the sequence,
although it is not necessary that G
sequence to be valid. After the t
been fulfilled, the
READ and WRITE operation.
E controlled R EAD cycles from
STORE
STORE initiation, it is impor-
READ or WRITE accesses inter-
STORE or RECALL will take place.
STORE cycle, the following
READ cycles
be low for the
cycle time has
STORE
SRAM will again be activated for
July 1999 4-48
STK12C68
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of
READ operations in a manner similar to the soft-
ware
STORE initiation. To initiate the RECALL cycle,
the following sequence of
E controlled READ opera-
tions must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) V ali d READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0E (hex) Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the
the t
ready for
cycle time the SRAM will once again be
RECALL
READ and WRITE operations. The RECALL
SRAM cells. After
operation in no way alters the data in the EEPROM
cells. The nonvolatile data can be recalled an unlimited number of times.
AutoStore™ OPERATION
The STK12C68 can be powered in one of three
modes.
During normal AutoStore™ operation, the
STK12C68 will draw current from V
capacitor connected to the V
CAP
charge will be used by the chip to perform a single
STORE operation. After power up, when the voltage
on the V
automatically disconnect the V
initiate a
pin drops below V
CAP
STORE operation.
SWITCH
CAP
to charge a
CCX
pin. This stored
, the part will
pin from V
CCX
and
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68µF and
220µF (± 20%) rated at 6V should be provided.
In system power mode (Figure 3), both V
V
are connected to the + 5V power supply without
CAP
CCX
and
the 68µF capacitor. In this mode the AutoStore™
function of the STK12C68 will operate on the stored
system charge as power goes down. The user must,
however, guarantee that V
3.6V during the 10ms
If an automatic
then V
V
CCX
(Figure 4). This is the AutoStore™ Inhibit
CAP
STORE on power loss is not required,
can be tied to ground and + 5V applied to
STORE cycle.
does not drop below
CCX
mode, in which the AutoStore™ function is disabled.
If the STK12C68 is operated in this configuration,
references to V
should be changed to V
CCX
CAP
throughout this data sheet. In this mode, STORE
operations may be triggered through software control or the HSB
pin. It is not permissable to change
between these three options “on the fly”.
In order to prevent unneeded
automatic
externally driving HSB
least one
most recent
initiated
whether a
STOREs as well as those initiated by
low will be ignored unless at
WRITE operation has taken place since the
STORE or RECALL cycle. Software-
STORE cycles are performed regardless of
WRITE operation has taken place. An
STORE operations,
optional pull-up resistor is shown connected to HSB
This can be used to signal the system that the
AutoStore™ cycle is in progress.
.
1
+
68µF
0.1µF
Bypass
6v, ±20%
14
28
27
26
15
Figure 2: AutoStore™ Mode
10kΩ
10kΩ∗
0.1µF
Bypass
Figure 3: System Power Mode
1
14
*If HSB is not used, it should be left unconnected.
July 1999 4-49
0.1µF
0.1µF
Bypass
28
27
26
15
10kΩ
10kΩ∗
Bypass
1
1
14
14
Figure 4: AutoStore™
Figure 4: AutoStore™
Inhibit Mode
Inhibit Mode
28
28
27
27
26
26
15
15
10kΩ
10kΩ
10kΩ∗
10kΩ∗
STK12C68
HSB OPERATION
The STK12C68 provides the HSB pin for controlling
and acknowledging the
pin is used to request a hardware STORE cycle.
When the HSB
pin is driven low, the STK12C68 will
conditionally initiate a
an actual
the
RECALL cycle. The HSB pin acts as an open drain
STORE cycle will only begin if a WRITE to
SRAM took place since the last STORE or
driver that is internally driven low to indicate a busy
condition while the
is in progress.
SRAM READ and WRITE operations that are in
progress when HSB
given time to complete before the
is initiated. After HSB
continue
multiple
WRITE is in progress when HSB is pulled low it will
SRAM operations for t
SRAM READ operations may take place. If a
be allowed a time, t
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB
The HSB
pin can be used to synchronize multiple
STK12C68s while using a single larger capacitor.
To operate in this mode the HSB
nected together to the HSB
STK12C68s. An external pull-up resistor to + 5V is
required since HSB
The V
pins from the other STK12C68 parts can
CAP
be tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
STK12C68s detects a power loss and asserts HSB
the common HSB
a
STORE cycle (a STORE will take place in those
STK12C68s that have been written since the last
nonvolatile cycle).
During any
STORE operation, regardless of how it
was initiated, the STK12C68 will continue to drive
the HSB
pin low, releasing it only when the STORE is
complete. Upon completion of the
the STK12C68 will remain disabled until the HSB
pin returns high.
STORE operations. T he HSB
STORE operation after t
STORE (initiated by any means)
DELAY
is driven low by any means are
STORE operation
goes low, the STK12C68 will
. During t
DELAY
, to complete. However, any
DELAY
DELAY
returns high.
pin should be con-
pins from the other
acts as an open drain pull down.
pin will cause all parts to request
STORE operation
PREVENTING STORES
The STORE function can be disabled on the fly by
holding HSB
30mA at a V
high with a driver capable of sourcing
of at least 2.2V, as it will have to
OH
overpower the internal pull-down device that drives
HSB
;
low for 20µs at the onset of a STORE. When
the STK12C68 is connected for AutoStore™ operation (system V
capacitor on V
connected to V
CC
) and VCC crosses V
CAP
and a 68µF
CCX
SWITCH
way down, the STK12C68 will attempt to pull HSB
low; if HSB doesn’t actually get below VIL, the part
will stop trying to pull HSB
low and abort the STORE
attempt.
HARDWARE PROTECT
The STK12C68 offers hardware protection against
inadvertent
,
during low-voltage conditions. When V
all externally initiated
WRITEs are inhibited.
STORE operation and SRAM WRITEs
CAP
STORE operations and SRAM
AutoStore™ can be completely disabled by tying
V
to ground and applying + 5V to V
CCX
AutoStore™
Inhibit mode; in this mode, STOREs are
CAP
only initiated by explicit request using either the software sequence or the HSB
pin.
LOW AVERAGE ACTIVE POWER
The STK12C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 5
shows the relationship between I
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
perature range, V
,
= 5.5V, 100% duty cycle on chip
CC
enable). Figure 6 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK12C68 depends on the following items:
1)
CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of
temperature; 6) the V
READs to WRITEs; 5) the operating
level; and 7) I/O loading.
cc
and READ cycle
CC
on the
< V
SWITCH
. This is the
,
If HSB
is not used, it should be left unconnected.
July 1999 4-50
STK12C68
100
Average Active Current (mA)
80
60
40
20
100
80
60
40
TTL
20
Average Active Current (mA)
CMOS
0
50 100 150 200
Cycle Time (ns)
Figure 5: Icc (max) Reads
0
50 100 150 200
Cycle Time (ns)
Figure 6: Icc (max) Writes
TTL
CMOS
July 1999 4-51
STK12C68
ORDERING INFOR M ATION
STK12C68 - P 45 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (-40 to 85°C)
Access Time
20 = 20ns (Commercial only)
25 = 25ns
35 = 35ns
45 = 45ns
Package
P = Plastic 28-pin 300 mil DIP
W = Plastic 28-pin 600 mil DIP
S = Plastic 28-pin 350 mil SOIC
C = Ceramic 28-pin 300 mil DIP
July 1999 4-52
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