SIMTEK STK12C68-5L55M, STK12C68-5L45M, STK12C68-5L40M, STK12C68-5K55M, STK12C68-5K45M Datasheet

STK12C68-M

STK12C68-M

CMOS nvSRAM

MIL-STD-883 / SMD # 5962-94599

FEATURES

• 40, 45 and 55ns Access Times

• 15 mA I

• Automatic

• Hardware or Software initiated

EEPROM

• Automatic

• 100,000

• 10 year data retention in EEPROM

• Automatic

• Software initiated

• Unlimited

• Single 5V±10% Operation

• Available in multiple standard packages

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

12

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

at 200ns Access Speed

CC

STORE

to EEPROM on Power Down

STORE

Timing

STORE

cycles to EEPROM

RECALL

RECALL

on Power Up

RECALL

from EEPROM

cycles from EEPROM

EEPROM ARRAY

STATIC RAM

ARRAY

ROW DECODER

INPUT BUFFERS

256 x 256

COLUMN I/O

COLUMN DECODER

AAAAA

011

1210

STORE

256 x 256

STORE

RECALL

to

8K x 8

AutoStore™

Nonvolatile Static RAM

DESCRIPTION

The Simtek STK12C68-M is a fast static RAM (40, 45
and 55ns), with a nonvolatile EEPROM element incor­porated in each static memory cell. The SRAM can be
read and written an unlimited number of times, while
independent nonvolatile data resides in EEPROM.
Data transfers from the SRAM to the EEPROM (the

STORE

down using charge stored in an external 100 µF
capacitor. Transfers from the EEPROM to the SRAM
(the
power up. Software sequences may also be used to
initiate both

STORE

The STK12C68-M is available in the following pack­ages: a 28-pin 300 mil ceramic DIP and 28-pad LCC.

AA

0

12

STORE/
RECALL

CONTROL

operation) take place automatically upon power

RECALL

operation) take place automatically on

STORE

and

RECALL

operations. A

can also be initiated via a single pin.

PIN CONFIGURATIONSLOGIC BLOCK DIAGRAM

1

V

HSB

A
A
A
G
A
E
DQ
DQ

8
9
11

10

DQ

7
6

DQ
DQ

V

CAP

2

A

12

3

A

7

4

A

6

5

A

5

6

A

4

7

A

3

8

A

2

9

A

1

10

A

0

11

0

12

1

13

2

14

SS

28 - 300 C-DIP

HSB

A
A
A
A
A
A

A
DQ
DQ

4

6

5

5

6

4

7

3

8

2

9

1

10

0

11

0

12

1

7

12

CAP

A

A

V

32128 27

TOP VIEW

234

Vss

DQDQDQ

28 - LCC

CCX

W

V

26
25
24
23
22
21
20
19
18

1716151413

5

DQ

PIN NAMES

A0 - A
W Write Enable

DQ0 - DQ7Data In/Out
E Chip Enable

G

E
W

G Output Enable
V

CCX

V

SS

V

CAP

HSB

Address Inputs

12

Power (+5V)
Ground
Capacitor
Hardware Store/Busy

V

28

CCX

W

27
26

HSB

25

A

8

24

A

9

23

A

11

22

G

21

A

10

20

E

19

DQ

7

18

DQ

6

17

DQ

5

16

DQ

4

15

DQ

3

4-53

STK12C68-M

ABSOLUTE MAXIMUM RATINGS

Voltage on typical input relative to V
Voltage on DQ

Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V)

0-7

Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W

DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA

. . . . . . . . . . . . . –0.6V to 7.0V

SS

a

Note a: Stresses greater than those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

(One output at a time, one second duration)
DC CHARACTERISTICS (VCC = 5.0V ± 10%)

SYMBOL PARAMETER MIN MAX UNITS NOTES

b

I

I

I

I

I

I

I

I

V
V
V
V
T

CC

CC

CC

CC

SB

CC

ILK

OLK

IH
IL
OH
OL
A

Average VCC Current 85 mA t

1

Average VCC Current During

2

b

Average VCC Current 15 mA E ≤ 0.2V, W ≥ (VCC – 0.2V)

3

at t

= 200ns others ≤ 0.2V or ≥ (VCC – 0.2V)

AVAV

Average VCC current during AutoStore™ cycle 4 mA All inputs ≤ 0.2V or ≥ (VCC - 0.2V)

4

c

Average VCC Current 35 mA t

1

(Standby, Cycling TTL Input Levels) 32 mA t

b

Average VCC Current 4 mA E ≥ (VCC – 0.2V)

2

(Standby, Stable CMOS Input Levels)
Input Leakage Current (Any Input) ±1 µAVCC = max

Off State Output Leakage Current ±5 µAVCC = max

Input Logic "1" Voltage 2.2 VCC+.5 V All Inputs
Input Logic "0" Voltage VSS–.5 0.8 V All Inputs
Output Logic "1" Voltage 2.4 V I
Output Logic "0" Voltage 0.4 V I
Operating Temperature –55 125 °C

STORE

80 mA t
75 mA t

8 mA All inputs ≤ 0.2V or ≥ (VCC – 0.2V)

28 mA t

= 40ns

AVAV

= 45ns

AVAV

= 55ns

AVAV

= 40ns

AVAV

= 45ns

AVAV

= 55ns

AVAV

E ≥ VIH; all others cycling

VIN = VSS to V

V

= VSS to V

OUT

= –4mA except HSB

OUT

= 8mA except HSB

OUT

CC

CC

d

Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: VCC reference levels throughout this datasheet refer to V

1

3

if that is where the power supply connection is made, or V

CCX

CAP

if V

is connected to ground.

CCX

AC TEST CONDITIONS

Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V

Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V

Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

CAPACITANCE (T

SYMBOL PARAMETER MAX UNITS CONDITIONS

C
C

Input Capacitance 8 pF ∆V = 0 to 3V

IN

Output Capacitance 7 pF ∆V = 0 to 3V

OUT

=25°C, f=1.0MHz)

A

Output

255 Ohms

Figure 1: AC Output Loading

5.0V

480 Ohms

INCLUDING

AND FIXTURE

30pF

SCOPE

4-54

SRAM MEMORY OPERATION

STK12C68-M

READ CYCLES #1 & #2

NO. PARAMETER UNITS

1t
2t
3t
4t
5t
6t
7t
8t

9t
10 t
11 t

SYMBOLS STK12C68-40M STK12C68-45M STK12C68-55M

#1, #2 Alt. MIN MAX MIN MAX MIN MAX

t

ELQV

AVAV

AVQV

GLQV

AXQX

ELQX

EHQZ

GLQX

GHQZ

ELICCH

EHICCL

g

h

h

e

c,e

Chip Enable Access Time 40 45 55 ns

ACS

t

Read Cycle Time 40 45 55 ns

RC

t

Address Access Time 40 45 55 ns

AA

t

Output Enable to Data Valid 20 25 35 ns

OE

t

Output Hold After Address Change 5 5 5 ns

OH

t

Chip Enable to Output Active 5 5 5 ns

LZ

t

Chip Disable to Output Inactive 17 20 25 ns

HZ

t

Output Enable to Output Active 0 0 0 ns

OLZ

t

Output Disable to Output Inactive 17 20 25 ns

OHZ

t

Chip Enable to Power Active 0 0 0 ns

PA

t

Chip Disable to Power Standby 35 45 55 ns

PS

(VCC = 5.0V ± 10%)

Note c: Bringing E ≥VIH will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note f: For READ CYCLE #1 and #2, W is high for entire cycle.
Note g: Device is continuously selected with E low and G low.
Note h: Measured ± 200mV from steady state output voltage.

READ CYCLE #1

f,g

t

AVAV

2

d

ADDRESS

DQ (Data Out)

READ CYCLE #2

ADDRESS

E

G

DQ (Data Out)

I

CC

ACTIVE
STANDBY

3

t

t

AXQX

5

AVQV

DATA VALID

f

2

t

AVAV

1

10

t

ELICCH

t

ELQX

t

t

GLQX

8

t

GLQV

ELQV

4

t

GHQZ

DATA VALID

9

6

t

EHQZ

11

t

EHICCL

7

4-55