STK12C68 (SMD5962-94599)
8Kx8 AutoStore nvSRAM
FEATURES
• 25, 35, 45, 55 ns Read Access & Write Cycle Time
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Loss
• Non-V olatile ST ORE Under Hardware or Sof tware
Control
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 1 Million STORE Cycles
• 100-Year Non-volatile Data Retention
• Single 5V ± 10% Power Supply
• Commercial, Industrial, Military Temperatures
• 28-pin 330-mil SOIC, 300-mil PDIP, and 600-mil
PDIP Packages (RoHS-Compliant)
• 28-Pin CDIP and LCC Military Packages
DESCRIPTION
The Simtek STK12C68 is a 64Kb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
Data transfers automatically to the non-volatile stor-
age cells when power loss is detected (the STORE
operation). On power up, data is automatically
restored to the SRAM (the RECALL operation). Both
STORE and RECALL operations are also available
under software control.
The Simtek nvSRAM is the first monolithic non-volatile memory to offer unlimited writes and reads. It is
the highest performance, most reliable non-volatile
memory available.
Block Diagram
A
5
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
ROW DECODER
A0 A1 A2 A3 A4 A
INPUT BUFFERS
QUANTUM TRAP
STATIC RAM
ARRAY
128 X 512
COLUMN I/O
COLUMN DEC
128 x 512
STORE
RECALL
10
V
CCX
POWER
CONTROL
STORE/
RECALL
CONTROL
V
CAP
SOFTWARE
DETECT
A0 – A
12
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1
G
E
W
Document Control #ML0008
February 2007
Rev 0.7
STK12C68 (SMD5962-94599)
Packages
VCAP
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-pin SOIC
28-pin DIP
28
27
26
16
15
25
24
23
22
21
20
19
18
17
VCCX
W
HSB
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
28-pin LCC
Pin Descriptions
Pin Name I/O Description
A12-A
0
DQ7-DQ
0
E Input Chip Enable: The active low E input selects the device
W Input Write Enable: The active low W enables data on the DQ pins to be written to the address
G Input Output Enable: The active low G input enables the data output buffers during read cycles.
V
CCX
HSB I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
V
CAP
V
SS
Input Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array
I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM
location latched by the falling edge of E
De-asserting G
Power Supply Power: 5.0V, +10%, -10%
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
Power Supply Ground
high caused the DQ pins to tri-state.
Document Control #ML0008
February 2007
Rev 0.7
2
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ
or HSB . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
0-7
Temperature under Bias . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . .15mA
STK12C68 (SMD5962-94599)
Note a: Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
SYMBOL PARAMETER
b
I
CC
I
CC
I
CC
I
CC
I
SB
I
SB
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
V
BL
T
A
Note b: I
Note c: I
Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Average VCC Current 85
1
c
Average V
2
b
Average V
3
5V, 25°C, Typical
c
Average V
4
Cycle
d
Average V
1
(Standby, Cycling TTL Input Levels)
d
V
2
CC
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Logic “0” Voltage on HSB Output 0.4 0.4 V I
Operating Temperature 0 70 –40/-55 85/125 °C
and I
CC
1
and I
CC
2
Current during STORE 3 3 mA All Inputs Don’t Care, V
CC
Current at t
CC
Current during AutoStore
CAP
Current
CC
Standby Current
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
are the average currents required for the duration of the respective STORE cycles (t
CC
4
AVAV
= 200ns
Note e: VCC reference levels throughout this datasheet refer to V
COMMERCIAL
MIN MAX MIN MAX
75
65
--
10 10 mA
2 2 mA
27
24
20
--
1.5 2.5 mA
±1 ±1 μA
±5 ±5 μA
if that is where the power supply connection is made, or V
CCX
INDUSTRIAL
MILITARY
85
75
65
55
27
24
20
19
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
t
= 25ns
AVAV
t
= 35ns
AVAV
t
= 45ns
AVAV
t
= 55ns
AVAV
W ≥ (V
All Others Cycling, CMOS Levels
All Inputs Don’t Care
t
t
t
t
E ≥ (VCC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
V
VIN = VSS to V
V
V
) .
STORE
– 0.2V)
CC
= 25ns, E ≥ V
AVAV
= 35ns, E ≥ V
AVAV
= 45ns, E ≥ V
AVAV
= 55ns, E ≥ V
AVAV
= max
CC
= max
CC
= VSS to VCC, E or G ≥ VIH
IN
= – 4mA except HSB
OUT
= 8mA except HSB
OUT
= 3mA
OUT
CC
CAP
IH
IH
IH
IH
if V
= max
CC
is connected to ground.
CCX
e
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCE
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
Note f: These parameters are guaranteed but not tested.
Document Control #ML0008
Input Capacitance 8 pF ΔV = 0 to 3V
Output Capacitance 7 pF ΔV = 0 to 3V
February 2007
f
(TA = 25°C, f = 1.0MHz)
Rev 0.7
3
OUTPUT
5.0V
480 Ohms
255 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1. AC Output Loading
STK12C68 (SMD5962-94599)
SRAM READ CYCLES #1 & #2 (V
NO.
1 t
2 t
3 t
4 t
5 t
6 t
7 t
8 t
9 t
10 t
11 t
SYMBOLS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
ELQV
AVAV
AVQ V
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
t
g
h
h
i
i
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
f
t
PA
f
t
PS
Chip Enable Access Time 25 35 45 55 ns
Read Cycle Time 25 35 45 55 ns
Address Access Time 25 35 45 55 ns
Output Enable to Data Valid 10 15 20 35 ns
Output Hold after Address Change 5 5 5 5 ns
Chip Enable to Output Active 5 5 5 5 ns
Chip Disable to Output Inactive 10 10 12 12 ns
Output Enable to Output Active 0 0 0 0 ns
Output Disable to Output Inactive 10 10 12 12 ns
Chip Enable to Power Active 0 0 0 0 ns
Chip Disable to Power Standby 25 35 45 55 ns
PARAMETER
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
ADDRESS
5
t
DQ (DATA OUT)
AXQX
STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55
,
g
h
2
t
AVAV
3
t
AVQ V
DATA VALID
= 5.0V ± 10%)
CC
e
UNITS
SRAM READ CYCLE #2: E Controlled
ADDRESS
t
ELQX
10
t
ELICCH
6
t
GLQX
4
t
GLQV
8
DQ (DATA OUT)
I
CC
E
G
STANDBY
g
t
AVAV
2
1
t
ELQV
ACTIVE
DATA VALID
t
GHQZ
9
t
EHQZ
t
EHICCL
7
11
Document Control #ML0008
February 2007
Rev 0.7
4
STK12C68 (SMD5962-94599)
SRAM WRITE CYCLES #1 & #2 (V
NO.
12 t
13 t
WLWH
14 t
15 t
16 t
DVWH
WHDX
17 t
18 t
19 t
20 t
21 t
WHAX
WLQZ
WHQX
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ V
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlled
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
AVAV
ELWH
AVW H
AVW L
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
i, j
t
Write Cycle Time 25 35 45 55 ns
WC
t
Write Pulse Width 20 25 30 45 ns
WP
t
Chip Enable to End of Write 20 25 30 45 ns
CW
t
Data Set-up to End of Write 10 12 15 25 ns
DW
t
Data Hold after End of Write 0 0 0 0 ns
DH
t
Address Set-up to End of Write 20 25 30 45 ns
AW
t
Address Set-up to Start of Write 0 0 0 0 ns
AS
t
Address Hold after End of Write 0 0 0 0 ns
WR
t
Write Enable to Output Disable 10 13 14 15 ns
WZ
t
Output Active after End of Write 5 5 5 5 ns
OW
during address transitions.
IH
PARAMETER
k, l
t
AVAV
ADDRESS
14
t
ELWH
E
STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55
12
19
t
WHAX
= 5.0V ± 10%)
CC
e
UNITS
17
t
20
t
WLQZ
AVW H
13
t
WLWH
W
DATA IN
DATA OUT
t
AVW L
18
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlled
ADDRESS
18
t
E
W
DATA IN
AVEL
t
AVEH
17
k, l
12
t
AVAV
t
ELEH
14
13
t
WLEH
15
t
DVWH
DATA VALID
HIGH IMPEDANCE
15
t
DVEH
DATA VALID
16
t
WHDX
19
t
EHAX
16
t
EHDX
21
t
WHQX
DATA OUT
Document Control #ML0008
February 2007
Rev 0.7
HIGH IMPEDANCE
5
STK12C68 (SMD5962-94599)
HARDWARE MODE SELECTION
E W HSB A12 - A0 (hex) MODE I/O POWER NOTES
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active o
L L H X Write SRAM Input Data Active
X X L X Nonvolatile STORE Output High Z l
0000
1555
L H H
L H H
0AAA
1FFF
10F0
0F0F
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
CC
Active
l
CC
Active
2
2
m
n, o
n, o
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the
part will go into standby mode, inhibiting all operations until
HSB rises.
Note n: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note o: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
HARDWARE STORE CYCLE (V
NO.
22 t
23 t
24 t
25 t
26 t
SYMBOLS
Standard Alternate MIN MAX
STORE
DELAY
RECOVER
HLHX
HLBL
t
HLHZ
t
HLQZ
t
HHQX
STORE Cycle Duration 10 ms i, p
Time Allowed to Complete SRAM Cycle 1 μs i, q
Hardware STORE High to Inhibit Off 700 ns p, r
Hardware STORE Pulse Width 15 ns
Hardware STORE Low to Store Busy 300 ns
PARAMETER
= 5.0V ± 10%)
CC
STK12C68
UNITS NOTES
e
Note p: E and G low for output behavior.
Note q: E and G low and W high for output behavior.
Note r: t
RECOVER
is only applicable after t
STORE
is complete.
HARDWARE STORE CYCLE
25
t
HLHX
HSB (IN)
24
t
RECOVER
22
t
STORE
HSB (OUT)
DQ (DATA OUT)
HIGH IMPEDANCE
Document Control #ML0008
February 2007
t
HLBL
DATA VALID
Rev 0.7
26
t
DELAY
HIGH IMPEDANCE
23
DATA VALID
6
STK12C68 (SMD5962-94599)
AutoStor e / PO WER-UP RECALL (V
NO.
27 t
28 t
29 t
30 t
31 V
32 V
Note s: t
Note t: HSB is asserted low for 1μs when V
RESTORE
will be released and no STORE will take place.
AutoStor e / PO WER-UP RECALL
SYMBOLS
Standard Alternate MIN MAX
RESTORE
STORE
VSBL
DELAY
SWITCH
RESET
t
HLHZ
t
BLQZ
starts from the time VCC rises above V
V
CC
31
V
SWITCH
32
V
RESET
Power-up RECALL Duration 550 μs s
STORE Cycle Duration 10 ms p, q, t
Low Voltage Trigger (V
Time Allowed to Complete SRAM Cycle 1 μs p
Low Voltage Trigger Level 4.0 4.5 V
Low Voltage Reset Level 3.9 V
drops through V
CAP
SWITCH
PARAMETER
) to HSB Low 300 ns l
SWITCH
.
. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB
SWITCH
= 5.0V ± 10%)
CC
STK12C68
UNITS NOTES
e
AutoStore
POWER-UP RECALL
HSB
DQ (DATA OUT)
TM
27
t
RESTORE
W
POWER-UP
RECALL
BROWN OUT
NO STORE
29
t
VSBL
30
t
DELAY
BROWN OUT
AutoStore
28
t
STORE
BROWN OUT
AutoStore
(NO SRAM WRITES)
NO RECALL
(V
DID NOT GO
CC
BELOW V
RESET
)
NO RECALL
(V
DID NOT GO
CC
BELOW V
RESET
RECALL WHEN
V
RETURNS
CC
)
ABOVE V
SWITCH
Document Control #ML0008
February 2007
Rev 0.7
7
STK12C68 (SMD5962-94599)
SOFTW ARE-CONTROLLED STORE/RECALL CYCLE
v
(VCC = 5.0V ± 10%)
e
NO.
33 t
34 t
35 t
36 t
37 t
SYMBOLS
Standard Alternate MIN MAX MIN MAX MIN MAX MIN MAX
AVAV
AVEL
ELEH
ELAX
RECALL
t
RC
t
AS
t
CW
STORE/RECALL Initiation Cycle
Time
Address Set-up Time 0 0 0 0 ns u
Clock Pulse Width 20 25 30 30 ns u
Address Hold Time 20 20 20 20 ns u
RECALL Duration 20 20 20 20 μs
PARAMETER
STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55
25 35 45 55 ns p
UNITS NOTES
Note u: The software sequence is clocked with E controlled READs.
Note v: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a
STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle.
SOFTWARE STORE/RECALL CYCLE: E Controlled
33
t
AVAV
ADDRESS
34
t
AVEL
E
t
ELEH
35
t
ELAX
36
W must be high during all six consecutive cycles.
v
33
t
AVAV
ADDRESS #6ADDRESS #1
DQ (DATA OUT)
DATA VA LID
DATA VALID
28 37
t
/ t
STORE
HIGH IMPEDANCE
RECALL
Document Control #ML0008
February 2007
Rev 0.7
8
STK12C68 (SMD5962-94599)
DEVICE OPERATION
The STK12C68 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast static
RAM. In nonvolatile mode, data is transferred from
SRAM to Nonvolatile Elements (the STORE opera-
tion) or from Nonvolatile Elements to
RECALL operation). In this mode SRAM functions are
SRAM (the
disabled.
NOISE CONSIDERATIONS
The STK12C68 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1μF connected between V
V
, using leads and traces that are as short as pos-
SS
sible. As with all high-speed
CMOS ICs, normal care-
CAP
and
ful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK12C68 performs a READ cycle whenever E
and G are low and W and HSB are high. The
address specified on pins A
determines which of
0-12
the 8,192 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of t
#1). If the
be valid at t
READ is initiated by E or G, the outputs will
ELQV
or at t
, whichever is later (READ
GLQV
(READ cycle
AVQ V
cycle #2). The data outputs will repeatedly respond to
address changes within the t
access time without
AVQ V
the need for transitions on any control input pins, and
will remain valid until another address change or until
E
or G is brought high, or W or HSB is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB
stable prior to entering the
remain stable until either E
end of the cycle. The data on the common I/O pins
DQ
will be written into the memory if it is valid t
0-7
before the end of a W controlled WRITE or t
before the end of an E controlled WRITE.
It is recommended that G
entire
WRITE cycle to avoid data bus contention on
common I/O lines. If G
will turn off the output buffers t
is high. The address inputs must be
WRITE cycle and must
or W goes high at the
DVWH
DVEH
be kept high during the
is left low, internal circuitry
after W goes low.
WLQZ
POWER-UP RECALL
During power up, or after any low-power condition
(V
< V
CAP
latched. When V
voltage of V
be initiated and will take t
If the STK12C68 is in a
power-up
), an internal RECALL request will be
RESET
once again exceeds the sense
CAP
, a RECALL cycle will automatically
SWITCH
RESTORE
RECALL, the SRAM data will be corrupted.
to complete.
WRITE state at the end of
To help avoid this situation, a 10K Ohm resistor
should be connected either between W
V
or between E and system VCC.
CC
and system
SOFTWARE NONVOLATILE STORE
The STK12C68 software STORE cycle is initiated by
executing sequential
six specific address locations. During the
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile elements. The program operation copies the
SRAM data into nonvolatile memory. Once a STORE
cycle is initiated, further input and output are disabled until the cycle is completed.
Because a sequence of READs from specific
addresses is used for
that no other
READ or WRITE accesses intervene in
the sequence, or the sequence will be aborted and
no
STORE or RECALL will take place.
To initiate the software
READ sequence must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0F (hex) Initiate STORE cycle
The software sequence must be clocked with E controlled
READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that
and not
WRITE cycles be used in the sequence,
although it is not necessary that G
sequence to be valid. After the t
been fulfilled, the
READ and WRITE operation.
E controlled READ cycles from
STORE
STORE initiation, it is important
STORE cycle, the following
READ cycles
be low for the
cycle time has
STORE
SRAM will again be activated for
Document Control #ML0008
February 2007
Rev 0.7
9
STK12C68 (SMD5962-94599)
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of
READ operations in a manner similar to the soft-
ware
STORE initiation. To initiate the RECALL cycle,
the following sequence of
E controlled READ opera-
tions must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0E (hex) Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the
the t
ready for
cycle time the SRAM will once again be
RECALL
READ and WRITE operations. The RECALL
SRAM cells. After
operation in no way alters the data in the Nonvolatile
Elements. The nonvolatile data can be recalled an
unlimited number of times.
AutoSto re OPERATION
The STK12C68 can be powered in one of three
modes.
During normal AutoStore operation, the STK12C68
will draw current from V
connected to the V
pin. This stored charge will be
CAP
used by the chip to perform a single
tion. After power up, when the voltage on the V
pin drops below V
disconnect the V
STORE operation.
SWITCH
pin from V
CAP
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
to charge a capacitor
CCX
STORE opera-
CAP
, the part will automatically
and initiate a
CCX
capacitor having a capacity of between 68μF and
220μF (± 20%) rated at 6V should be provided.
In system power mode (Figure 3), both V
CCX
and V
CAP
are connected to the + 5V power supply without the
68μF capacitor. In this mode the AutoStore function
of the STK12C68 will operate on the stored system
charge as power goes down. The user must, however, guarantee that V
during the 10ms
If an automatic
then V
V
CAP
can be tied to ground and + 5V applied to
CCX
(Figure 4). This is the AutoStore Inhibit mode, in
STORE cycle.
STORE on power loss is not required,
does not drop below 3.6V
CCX
which the AutoStore function is disabled. If the
STK12C68 is operated in this configuration, references to V
this data sheet. In this mode,
be triggered through software control or the HSB
should be changed to V
CCX
STORE operations may
throughout
CAP
pin.
It is not permissible to change between these three
options “on the fly.”
In order to prevent unneeded
automatic
externally driving HSB
least one
most recent
ated
whether a
STOREs as well as those initiated by
low will be ignored unless at
WRITE operation has taken place since the
STORE or RECALL cycle. Software initi-
STORE cycles are performed regardless of
WRITE operation has taken place. An
optional pull-up resistor is shown connected to HSB
STORE operations,
.
This can be used to signal the system that the
AutoStore cycle is in progress.
If the power supply drops faster than 20 μs/volt
before V
should be inserted between V
reaches V
CCX
, then a 2.2 ohm resistor
SWITCH
and the system
CCX
supply to avoid momentary excess of current
between Vccx and Vcap.
1
27
+
68μF
6V ±20%
0.1μF
14
15
Figure 2. AutoStore Mode
Document Control #ML0008
February 2007
28
26
Rev 0.7
28
14
1
27
26
15
10K O
10K O*
0.1 μF Bypass
Figure 3. System Power Mode
10
10K O
10K O*
0.1 μF Bypass
14
1
28
27
26
15
Figure 4. AutoStore Inhibit Mode
10K O
10K O*
STK12C68 (SMD5962-94599)
HSB OPERATION
The STK12C68 provides the HSB pin for controlling
and acknowledging the
pin is used to request a hardware STORE cycle.
When the HSB
pin is driven low, the STK12C68 will
conditionally initiate a
an actual
the
RECALL cycle. The HSB pin acts as an open drain
STORE cycle will only begin if a WRITE to
SRAM took place since the last STORE or
driver that is internally driven low to indicate a busy
condition while the
is in progress.
SRAM READ and WRITE operations that are in
progress when HSB
given time to complete before the
is initiated. After HSB
continue
multiple
WRITE is in progress when HSB is pulled low it will
SRAM operations for t
SRAM READ operations may take place. If a
be allowed a time, t
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB
The HSB
pin can be used to synchronize multiple
STK12C68s while using a single larger capacitor. To
operate in this mode the HSB
nected together to the HSB
STK12C68s. An external pull-up resistor to + 5V is
required since HSB
The V
pins from the other STK12C68 parts can
CAP
be tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
STK12C68s detects a power loss and asserts HSB
the common HSB
a
STORE cycle (a STORE will take place in those
STK12C68s that have been written since the last
nonvolatile cycle).
During any
STORE operation, regardless of how it
was initiated, the STK12C68 will continue to drive
the HSB
pin low, releasing it only when the STORE is
complete. Upon completion of the
the STK12C68 will remain disabled until the HSB
pin returns high.
STORE operations. The HSB
STORE operation after t
STORE (initiated by any means)
DELAY
is driven low by any means are
STORE operation
goes low, the STK12C68 will
. During t
DELAY
, to complete. However, any
DELAY
DELAY
returns high.
pin should be con-
pins from the other
acts as an open drain pull down.
pin will cause all parts to request
STORE operation
;
,
,
If HSB
is not used, it should be left unconnected.
PREVENTING STORES
The STORE function can be disabled on the fly by
holding HSB
30mA at a V
high with a driver capable of sourcing
of at least 2.2V, as it will have to
OH
overpower the internal pull-down device that drives
HSB
low for 20μs at the onset of a STORE. When
the STK12C68 is connected for AutoStore operation
(system V
on V
CAP
the STK12C68 will attempt to pull HSB
connected to V
CC
) and VCC crosses V
and a 68μF capacitor
CCX
on the way down,
SWITCH
low; if HSB
doesn’t actually get below VIL, the part will stop trying to pull HSB
low and abort the STORE attempt.
HARDWARE PROTECT
The STK12C68 offers hardware protection against
inadvertent
ing low-voltage conditions. When V
externally initiated
WRITEs are inhibited.
AutoStore can be completely disabled by tying V
to ground and applying + 5V to V
AutoStore
STORE operation and SRAM WRITEs dur-
< V
CAP
STORE operations and SRAM
. This is the
CAP
SWITCH
, all
CCX
Inhibit mode; in this mode, STOREs are only
initiated by explicit request using either the software
sequence or the HSB
pin.
LOW AVERAGE ACTIVE POWER
The STK12C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 5
shows the relationship between I
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
perature range, V
= 5.5V, 100% duty cycle on chip
CC
enable). Figure 6 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK12C68 depends on the following items:
1)
CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of
temperature; 6) the V
READs to WRITEs; 5) the operating
level; and 7) I/O loading.
cc
and READ cycle
CC
Document Control #ML0008
February 2007
Rev 0.7
11
STK12C68 (SMD5962-94599)
100
80
60
40
TTL
20
Average Active Current (mA)
CMOS
0
50 100 150 200
Cycle Time (ns)
Figure 5: Icc (max) Reads
Commercial and Industrial Ordering Information
STK12C68 - S F 45 I TR
100
Average Active Current (mA)
80
60
40
20
TTL
CMOS
0
50 100 150 200
Cycle Time (ns)
Figure 6: Icc (max) Writes
Packing Option
Blank = Tube
TR = Tape and Reel
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
F = 100% Sn (Matte Tin)
Package
S = Plastic 28-pin 330 mil SOIC
W = Plastic 28-pin 600 mil DIP
P = Plastic 28-pin 300 mil DIP
C = Ceramic 28-pin 300 mil DIP
L = Ceramic 28-pin LLC
Document Control #ML0008
February 2007
Rev 0.7
12
Military Ordering Information
STK12C68 - 5 C 35 M
STK12C68 (SMD5962-94599)
Temperature Range
M = Military (–55 to 125°C)
Access Time
35 = 35ns
55 = 55ns
Package
C = Ceramic 28-pin 300 mil DIP (gold lead finish)
K = Ceramic 28-pin 300 mil DIP (solder dip finish)
L = Ceramic 28 pin LCC
Retention / Endurance
5 = Military (10 years or 105cycles)
5962 - 94599 01 MX X
Lead Finish
A = Solder DIP lead finish
C = Gold lead DIP finish
X = Lead finish “A” or “C” is acceptable
Case Outline
X = Ceramic 28 pin 300-mil DIP
Y = Ceramic 28 pin LCC
Device Class Indicator - Class M
Device Type
01 = 55ns
03 = 35ns
Document Control #ML0008
February 2007
Rev 0.7
13
STK12C68 (SMD5962-94599)
Ordering Information
Part Number Description Temperature
STK12C68-C35 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Commercial
STK12C68-C45 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Commercial
STK12C68-L35 5V 8Kx8 AutoStore nvSRAM LCC28 Commercial
STK12C68-L45 5V 8Kx8 AutoStore nvSRAM LCC28 Commercial
STK12C68-PF25 5V 8Kx8 AutoStore nvSRAM PDIP28-600 Commercial
STK12C68-PF45 5V 8Kx8 AutoStore nvSRAM PDIP28-600 Commercial
STK12C68-SF25 5V 8Kx8 AutoStore nvSRAM SOP28-330 Commercial
STK12C68-SF25TR 5V 8Kx8 AutoStore nvSRAM SOP28-330 Commercial
STK12C68-SF45 5V 8Kx8 AutoStore nvSRAM SOP28-330 Commercial
STK12C68-SF45TR 5V 8Kx8 AutoStore nvSRAM SOP28-330 Commercial
STK12C68-WF25 5V 8Kx8 AutoStore nvSRAM PDIP28-600 Commercial
STK12C68-WF45 5V 8Kx8 AutoStore nvSRAM PDIP28-600 Commercial
STK12C68-C35I 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Industrial
STK12C68-C45I 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Industrial
STK12C68-L35I 5V 8Kx8 AutoStore nvSRAM LCC28 Industrial
STK12C68-L45I 5V 8Kx8 AutoStore nvSRAM LCC28 Industrial
STK12C68-PF25I 5V 8Kx8 AutoStore nvSRAM PDIP28-600 Industrial
STK12C68-PF45I 5V 8Kx8 AutoStore nvSRAM PDIP28-600 Industrial
STK12C68-SF25I 5V 8Kx8 AutoStore nvSRAM SOP28-330 Industrial
STK12C68-SF25ITR 5V 8Kx8 AutoStore nvSRAM SOP28-330 Industrial
STK12C68-SF45I 5V 8Kx8 AutoStore nvSRAM SOP28-330 Industrial
STK12C68-SF45ITR 5V 8Kx8 AutoStore nvSRAM SOP28-330 Industrial
STK12C68-WF25I 5V 8Kx8 AutoStore nvSRAM PDIP28-600 Industrial
STK12C68-WF45I 5V 8Kx8 AutoStore nvSRAM PDIP28-600 Industrial
SMD5962-9459901MXA 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Military
SMD5962-9459901MXC 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Military
SMD5962-9459901MXX 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Military
SMD5962-9459901MYA 5V 8Kx8 AutoStore nvSRAM LCC28 Military
SMD5962-9459901MYX 5V 8Kx8 AutoStore nvSRAM LCC28 Military
SMD5962-9459903MXA 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Military
SMD5962-9459903MXC 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Military
SMD5962-9459903MXX 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Military
SMD5962-9459903MYA 5V 8Kx8 AutoStore nvSRAM LCC28 Military
SMD5962-9459903MYX 5V 8Kx8 AutoStore nvSRAM LCC28 Military
STK12C68-5C35M 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Military
STK12C68-5C55M 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Military
STK12C68-5K35M 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Military
STK12C68-5K55M 5V 8Kx8 AutoStore nvSRAM CDIP28-300 Military
STK12C68-5L35M 5V 8Kx8 AutoStore nvSRAM LCC28 Military
STK12C68-5L55M 5V 8Kx8 AutoStore nvSRAM LCC28 Military
Document Control #ML0008
February 2007
Rev 0.7
14
Package Diagrams
28-Lead, 330 mil SOIC Gull Wing
STK12C68 (SMD5962-94599)
0.020
0.014
0.508
( )
0.356
0.713
0.733
18.11
( )
18.62
0.050 (1.270)
0.103
0.093
2.616
( )
2.362
0.112
(2.845)
0.004
(0.102)
0.336
0.326
8.534
( )
8.280
0.014
0.008
Pin 1
0.356
( )
0.203
DIM = INCHES
MIN
MAX
0.044
0.028
0.477
( )
0.453
1.117
( )
0.711
12.116
11.506
10°
0°
Document Control #ML0008
February 2007
Rev 0.7
DIM = mm
15
(
MIN
MAX
)
STK12C68 (SMD5962-94599)
28-Lead 300 mil PDIP
Pin 1
Index
.020
0.51
(
)
0.76
.030
.275
()
.295
6.98
7.49
----
----
()
4.57
.180
.030
()
.045
0.76
1.14
1.345
1.385
.014
.022
.300
.325
0o
15
34.16
(
()
o
)
35.18
0.36
0.56
7.62
()
8.26
.045
()
.060
1.14
1.52
.008
()
.015
0.20
0.38
.125 (3.18)
.100
(2.54)
BSC
DIM = INCHES
DIM = mm
(
MIN
MIN
MAX
MIN
MAX
)
.015
----
(
0.38
----
)
Document Control #ML0008
February 2007
Rev 0.7
.300
(7.62)
BSC
----
()
10.92
.430
----
16
28-Lead, 600 mil PDIP
Pin 1
Index
0.040
1.02
( )
1.27
0.050
1.440
1.460
36.58
( )
37.08
STK12C68 (SMD5962-94599)
0.530
13.46
0.550
(
13.97
)
---- ----
(4.57) .180
0
15
0.015 (0.38)
----
0.125 (3.18)
MIN
0.10
(2.54)
0.36
0.014
0.022
15.11
0.595
( )
15.88
0.625
o
o
0.600
0.660
15.24
(
16.76
)
(
0.56
)
0.008
0.015
0.045
0.060
1.14
(
1.52
0.20
( )
0.38
)
BSC
DIM = INCHES
DIM = mm
(
MIN
MAX
MIN
MAX
)
----
Document Control #ML0008
February 2007
Rev 0.7
17
STK12C68 (SMD5962-94599)
28-Lead, 300 mil Side Braze DIL
(
3.15
4.14
)
.124
.162
---
.060
---
( )
1.52
1.386
1.414
35.20
( )
35.92
PIN
14
.125 (3.18)
MIN
.280
.310
.040
.060
7.36
( )
7.87
1.02
( )
1.52
.016
( )
.020
7.37
.290
(
7.87
.310
.300 7.62
( )
.320 8.13
0.41
0.51
)
.009
( )
.012
0.23
0.30
2.29
.090
1.22
.048
( )
1.32
.052
.110
DIM = INCHES
DIM = mm
(
2.79
)
(
MIN
MAX
MIN
MAX
)
Document Control #ML0008
February 2007
Rev 0.7
18
28-Pad, 350 mil Ceramic LCC
STK12C68 (SMD5962-94599)
(1.02) 0.040 REF X 45
3 places
(0.51) 0.020 REF X 45
(0.23) 0.009 REF
28 places
0.542
ο
0.558
13.77
14.17
( )
0.342
0.358
(
8.69
9.09
)
ο
0.075
0.095
0.045
0.055
1.91
( )
2.41
1.14
( )
1.40
(
0.022
0.028
0.56
0.71
---
0.558
)
(
0.006
0.022
0.15
0.56
---
(
14.17
)
)
0.045 1.14
0.055 1.40
(
)
0.070
0.090
Pad 1
Index
1.78
(
2.29
)
0.062
0.078
(
1.57
( )
1.98
0.015
---
0.381
---
)
DIM = INCHES
DIM = mm
(
MIN
MAX
MIN
MAX
)
Document Control #ML0008
February 2007
Rev 0.7
19
STK12C68 (SMD5962-94599)
Document Revision History
Revision
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
SIMTEK STK12C68 Datasheet, February 2007
Copyright 2007, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other
form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be
accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MER
CHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a
license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
Date Summary
December 2002 Combined commercial, industrial and military data sheets. Removed 20 nsec device.
January 2003 Added 35ns SMD to order information
July 2003 Added “28 - SOIC” label to page 1 pinout drawing
September 2003 Added lead-free lead finish
October 2003 Restored “W” 600 mil DIP package to ordering information
March 2006 Removed Commercial 35 ns and leaded lead finish, Removed Military 45ns device
August 2006 Reformat SMD Ordering Information to SDDC Part Number Format
February 2007 Add Fast Power-Down Slew Rate Information
Restore Comm/Ind C & L Package Options
Add Tape Reel Ordering Options
Add Product Ordering Code Listing
Add Package Outline Drawings
Reformat Entire Document
-
Document Control #ML0008
February 2007
Rev 0.7
20
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