SIMTEK STK11C88-W35, STK11C88-W25, STK11C88-W25I, STK11C88-W20, STK11C88-S45I Datasheet
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STK11C88
32K x 8 nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• 20ns, 25ns, 35ns and 45ns Access Times
• STORE to EEPROM Initiated by Software
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA T ypical I
at 200ns Cycle Time
CC
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• Commercial and Industrial Temperatures
• 28-Pin PDIP and SOIC Packages
BLOCK DIAGRAM
EEPROM ARRAY
512 x 512
STORE
STORE/
RECALL
RECALL
A
A3A
A
2
10
4
CONTROL
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
0
1
2
3
4
5
6
7
INPUT BUFFERS
STATIC RAM
ROW DECODER
COLUMN I/O
COLUMN DEC
A0A
ARRAY
512 x 512
1
DESCRIPTION
The Simtek STK11C88 is a fast static RAM with a
nonvolatile, electrically erasable
incorporated in each static memory cell. The
PROM element
SRAM
can be read and written an unlimited number of
times, while independent nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation), or from EEPROM to
SRAM (the RECALL operation), take place using a
software sequence. Transfers from the
the
SRAM (the RECALL operation) also take place
EEPROM to
automatically on restoration of power.
The STK11C88 is pin-compatible with industry-
standard
SRAMs.
PIN CONFIGURATIONS
1
SOFTWARE
DETECT
A0 - A
A
14
A
2
12
3
A
7
A
4
6
A
5
5
A
6
4
A
7
3
8
A
2
9
A
1
10
A
0
11
DQ
0
12
DQ
1
13
DQ
2
V
14
13
SS
V
28
CC
W
27
26
A
13
25
A
8
A
24
9
A
23
11
22
G
21
A
10
20
E
19
DQ
7
18
17
16
15
28 - 300 PDIP
DQ
6
28 - 600 PDIP
DQ
5
DQ
28 - 300 SOIC
4
DQ
3
28 - 350 SOIC
PIN NAMES
A0 - A
14
W Write Enable
G
E
W
DQ0 - DQ
E Chip Enable
G Output Enable
V
CC
V
SS
7
Address Inputs
Data In/Out
Power (+5V)
Ground
July 1999 5-1
STK11C88
ABSOLUTE MAXIMUM RATINGS
Volt age on Input Rel ative to VSS. . . . . . . . . . –0.6V to (VCC + 0.5V)
Volt age on DQ
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
0-7
a
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
SYMBOL PARAMETER
c
I
I
I
I
I
I
I
V
V
V
V
T
CC
CC
CC
SB
SB
ILK
OLK
IH
IL
OH
OL
A
Average VCC Current 110
1
d
Average VCC Current during STORE 33mAAll Inputs Don’t Care, V
2
c
Average VCC Current at t
3
5V, 25°C, Typical
e
Average VCC Current
1
(Standby, Cycling TTL Input Levels)
e
VCC Standby Current
2
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 –40 85 °C
AVAV
= 200ns
Note b: The STK11C88-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
Note d: I
Note e: E
and I
CC
1
is the average current required for the duration of the STORE cycle (t
CC
2
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
3
COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX
N/A
STORE
100
85
70
N/A
31
26
23
).
97
80
70
10 10 mA
35
30
25
22
750 750 µA
±1 ±1 µA
±5 ±5 µA
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
t
= 20ns
AVAV
t
= 25ns
AVAV
t
= 35ns
AVAV
t
= 45ns
AVAV
W
≥ (V
– 0.2V)
CC
All Others Cycling, CMOS Levels
t
= 20ns, E ≥ V
AVAV
t
= 25ns, E ≥ V
AVAV
t
= 35ns, E ≥ V
AVAV
t
= 45ns, E ≥ V
AVAV
E
≥ (VCC - 0.2V)
All Other s V
V
= max
CC
V
= VSS to V
IN
V
= max
CC
V
= VSS to VCC, E or G ≥ VIH
IN
= – 4mA
OUT
= 8mA
OUT
IH
IH
IH
IH
≤ 0.2V or ≥ (VCC – 0.2V)
IN
CC
CC
= max
b
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
CAPACITANCE
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
Input Capacitance 5 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V
f
(TA = 25°C, f = 1.0MHz)
Note f: These parameters are guaranteed but not tested.
July 1999 5-2
OUTPUT
5.0V
480 Ohms
30 pF
255 Ohms
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
STK11C88
SRAM READ CYCLES #1 & #2 (V
NO.
10 t
11 t
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1t
ELQV
2t
AVAV
3t
AVQV
4t
GLQV
5t
AXQX
6t
ELQX
7t
EHQZ
8t
GLQX
9t
GHQZ
ELICCH
EHICCL
SYMBOLS
g
h
h
i
i
f
e, f
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Chip Enable Access Time 20 25 35 45 ns
Read Cycle Time 20 25 35 45 ns
Address Access Time 22 25 35 45 ns
Output Enable to Data Valid 8 10 15 20 ns
Output Hol d after Addres s Change 5 5 5 5 ns
Chip Enable to Output Active 5 5 5 5 n s
Chip Disable to Output Inactive 7 10 13 15 ns
Output Enable to Output Active 0 0 0 0 ns
Output Disa ble to Outp u t Inactive 7 10 13 15 ns
Chip Enable to Power Active 0 0 0 0 ns
Chip Disable to Power Standby 25 25 35 45 ns
PARAMETER
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E
, G < V
Note i: Measured ± 200mV from steady state output voltage.
and W > VIH; device is continuously selected.
IL
SRAM READ CYCLE #1: Address Controlled
ADDRESS
3
t
AVQV
DQ (DATA OUT)
t
AXQX
5
STK11C88-20 STK11C88-25 STK11C88-35 STK11C88-45
g, h
2
t
AVAV
DATA VALID
= 5.0V + 10%)
CC
b
UNITS
SRAM READ CYCLE #2: E Controlledg
t
ADDRESS
t
ELQX
10
t
ELICCH
6
t
GLQX
4
t
GLQV
8
DQ (DATA OUT)
I
CC
E
G
STANDBY
2
AVAV
t
ACTIVE
1
ELQV
DATA VALID
t
GHQZ
9
t
EHQZ
7
11
t
EHICCL
July 1999 5-3
STK11C88
SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V + 10%)
NO.
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
WLWH
DVWH
WHDX
AVWH
WHAX
WLQZ
WHQX
SYMBOLS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
AVAV
ELWH
AVWL
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
i, j
t
Write Cycle Time 20 25 35 45 ns
WC
t
Write Pulse Width 15 20 25 3 0 ns
WP
t
Chip Enable to End of Write 15 20 25 30 ns
CW
t
Data Set-up to End of Write 8 10 12 15 ns
DW
t
Data Hold after End of Write 0 0 0 0 ns
DH
t
Address Set-up to End of Write 15 20 25 30 ns
AW
t
Address Set-up to Start of Write 0 0 0 0 ns
AS
t
Address Hold after End of Write 0 0 0 0 ns
WR
t
Write Enable to Output Disable 7 10 13 15 ns
WZ
t
Output Active after End of Write 5 5 5 5 ns
OW
PARAMETER
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E
or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlled
ADDRESS
t
E
ELWH
STK11C88-20 STK11C88-25 STK11C88-35 STK11C88-45
k
12
t
AVAV
14
19
t
WHAX
UNITS
b
17
t
20
t
WLQZ
AVWH
13
t
WLWH
W
DATA IN
DA TA OUT
18
t
AVWL
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlled
ADDRESS
18
t
E
W
DATA IN
AVEL
17
t
AVEH
15
t
DVWH
DATA VALID
HIGH IMPEDANCE
16
t
WHDX
21
t
WHQX
k
12
t
AVAV
t
ELEH
14
13
t
WLEH
15
t
DVEH
DATA VALID
19
t
EHAX
16
t
EHDX
DA TA OUT
HIGH IMPEDANCE
July 1999 5-4
STK11C88
STORE INHIBIT/POWER-UP RECALL (VCC = 5.0V + 10%)
NO.
22 t
23 t
24 V
25 V
Note l: t
SYMBOLS
Standard MIN MAX
RESTORE
STORE
SWITCH
RESET
starts from the time VCC rises above V
RESTORE
Power-up RECALL Duration 550 µsl
STORE Cycle Duration 10 ms
Low Voltage Trigger Level 4.0 4.5 V
Low Voltage Reset Level 3.9 V
SWITCH
PARAMETER
.
STK11C88
UNITS NOTES
STORE INHIBIT/POWER-UP RECALL
V
CC
5V
24
V
SWITCH
25
V
RESET
STORE INHIBIT
b
OWER-UP RECALL
DQ (DATA OUT)
22
t
RESTORE
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
NO RECALL
(V
DID NOT GO
CC
BELOW V
RESET
BROWN OUT
STORE INHIBIT
NO RECALL
(V
DID NOT GO
CC
)
BELOW V
RESET
)
BROWN OUT
STORE INHIBIT
RECALL WHEN
V
RETURNS
CC
ABOVE V
SWITCH
July 1999 5-5
STK11C88
SOFTW ARE ST ORE/RECALL MODE SELECTION
E W A13 - A0 (hex) MODE I/O NOTES
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
RECALL
LH
LH
0E38
31C7
03E0
3C1F
303F
0FC0
0E38
31C7
03E0
3C1F
303F
0C63
Note m: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note n: While there are 15 addresses on the STK11C88, only the lower 14 are used to control software modes.
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
m, n
m, n
SOFTW ARE ST ORE/RECALL CYCLE
NO. SYMBOLS PARAMETER
26 t
27 t
28 t
29 t
30 t
AVAV
AVEL
ELEH
ELAX
RECALL
o
o
o
STORE/RECALL Initiation Cycle Time 20 25 35 45 ns
Address Set-up Time 0000ns
Clock Pulse Width 15202530 ns
Address Hold Time 15 20 20 20 ns
o
RECALL Dura t i on 20 20 20 20 µs
o, p
STK11C88-20 STK11C88-25 STK11C88-35 STK11C88-45
MIN MAX MIN MAX MIN MAX MIN MAX
(VCC = 5.0V ± 10%)
UNITS
Note o: The software sequence is clocked with E controlled reads.
Note p: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,
303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W
must be high during all six consecutive
cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlled
26
t
AVAV
ADDRESS
27
t
AVEL
E
E
t
ELEH
28
p
26
t
AVAV
ADDRESS #6ADDRESS #1
b
29
t
ELAX
DQ (DATA
DATA VALID
July 1999 5-6
DATA VALID
23 30
t
/ t
STORE
HIGH IMPEDANCE
RECALL
DEVICE OPERATION
STK11C88
The STK11C88 is a versatile memory chip that provides several modes of operation. The STK11C88
can operate as a standard 32K x 8
32K x 8
EEPROM shadow to which the SRAM infor-
mation can be copied or from which the
SRAM. It has a
SRAM can
be updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK11C88 is a high-speed memory
and so must have a high-frequency bypass capacitor of approximately 0.1µF connected between V
cc
and Vss, using leads and traces that are as short as
possible. As with all high-speed
CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK11C88 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A
bytes will be accessed. When the
determines which of the 32,768 data
0-14
READ is initiated
by an address transition, the outputs will be valid
after a delay of
initiated by E
at
t
, whichever is later (READ cycle #2). The data
GLQV
t
(READ cycle #1). If the READ is
AVQV
or G, the outputs will be valid at t
ELQV
or
outputs will repeatedly respond to address changes
within the t
access time without the need for tran-
AVQV
sitions on any control input pins, and will remain valid
until another address change or until E
or G is
brought high.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the
until either E
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W
E
controlled WRITE or t
controlled WRITE.
It is recommended that G
entire
WRITE cycle to avoid data bus contention on
the common I/ O li nes. If G
will turn off the output buffers t
WRITE cycle and must remain stable
or W goes high at the end of the cycle.
will be writ-
0-7
before the end
DVWH
before the end of an
DVEH
be kept high during the
is left low, internal circuitry
after W goes low.
WLQZ
SOFTWARE NONVOLATILE STORE
The STK11C88 software STORE cycle is initiated by
executing sequential
address locations. During the
READ cycles from six specific
STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the
nonvolatile memory. Once a
SRAM data into
STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of
addresses is used for
tant that no other
READ or WRITE accesses inter-
READs from specific
STORE initiation, it is impor-
vene in the sequence or the sequence will be
aborted and no
To initiate the software
READ sequence must be performed:
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0FC0 (hex) Initiate STORE cycle
STORE or RECALL will take place.
STORE cycle, the following
The software sequence must be clocked with E controlled
READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that
and not
WRITE cycles be used in the sequence,
although it is not necessary that G
sequence to be valid. After the t
been fulfilled, the
READ and WRITE operation.
SRAM will again be activated for
STORE
READ cycles
be low for the
cycle time has
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of
READ operations in a manner similar to the soft-
ware
STORE initiation. To initiate the RECALL cycle,
the following sequence of
performed:
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0C63 (hex) Initiate RECALL cycle
READ operations must be
July 1999 5-7
STK11C88
Internally, RECALL is a two-step procedure. First,
the
SRAM data is cleared, and second, the nonvola-
tile information is transferred into the
After the t
be ready for
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled
cycle time the SRAM will once again
RECALL
READ and WRITE operations. The
SRAM cells.
an unlimited number of times.
POWER-UP RECALL
During power up, or after any low-power condition
(V
< V
CC
latched. When V
voltage of V
be initiated and will take t
If the STK11C88 is in a
power-up
To help avoid this situation, a 10K Ohm resistor
should be connected either between W
V
or between E and system VCC.
CC
), an internal RECALL request will be
RESET
once again exceeds the sense
CC
, a RECALL cycle will automatically
SWITCH
RESTORE
WRITE state at the end of
RECALL, the SRAM data will be corrupted.
to complete.
and system
HARDWARE PROTECT
The STK11C88 offers hardware protection against
inadvertent
conditions. When V
STORE operation during low-voltage
CC
< V
, all software STORE
SWITCH
operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C88 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
perature range, V
= 5.5V, 100% duty cycle on
CC
chip enable). Figure 3 shows the same relationship
for
WRITE cycles. If the chip enable duty cycle is
less than 100%, only standby current is drawn
when the chip is disabled. The overall average current drawn by the STK11C88 depends on the following items: 1)
CMOS vs. TTL input levels; 2) the
duty cycle of chip enable; 3) the overall cycle rate
for accesses; 4) the ratio of
and READ cycle
CC
READs to WRITEs; 5)
the operating temperature; 6) the V
O loading.
level; and 7) I/
cc
100
)
100
Average Active Current (mA)
80
60
40
TTL
20
CMOS
0
50 100 150 200
Cycle Time (ns)
July 1999 5-8
ORDERING INFOR M ATION
STK11C88
STK11C88
- W 25 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C
Access Time
20 = 20ns (Commercial only)
25 = 25ns
35 = 35ns
45 = 45ns
Package
W = Plastic 28-pin 600 mil DIP
P = Plastic 28-pin 300 mil DIP
S = Plastic 28-pin 350 mil SOIC
N = Plastic 28-pin 300 mil SOIC
)
July 1999 5-9
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