SIMTEK STK11C88-3W55I, STK11C88-3W55, STK11C88-3W45I, STK11C88-3W45, STK11C88-3S55I Datasheet
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July 1999 5-11
ADVANCE
STK11C88-3
32K x 8 nvSRAM
3.3V QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• Operating VCC Range: 3.0V-3.6V
• 45ns and 55ns Access Times
• STORE to EEPROM Initiated by Software
• RECALL to SRAM Initiated by Software or
Power Restore
• 8mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• Commercial and Industrial Temperatures
• 28-Pin DIP and SOIC Packages
DESCRIPTION
The Simtek STK11C88-3 is a fast static RAM with a
nonvolatile, electrically erasable
PROM element
incorporated in each static memory cell. The
SRAM
can be read and written an unlimited number of
times, while independent nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation), or from EEPROM to
SRAM (the RECALL operation) take place using a
software sequence. Transfers from the
EEPROM to
the
SRAM (the RECALL operation) also take place
automatically on restoration of power.
BLOCK DIAGRAM
EEPROM ARRAY
512 x 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
512 x 512
ROW DECODER
INPUT BUFFERS
STORE/
RECALL
CONTROL
A
6
A
7
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
SOFTWARE
DETECT
A0 - A
13
G
E
W
A
9
A
8
A
10
A3A
2
A0A
1
A
4
A
5
PIN CONFIGURATIONS
PIN NAMES
A0 - A
14
Address Inputs
W Write Enable
DQ0 - DQ
7
Data In/Out
E Chip Enable
G Output Enable
V
CC
Power (+ 3.3V)
V
SS
Ground
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
V
CC
A
13
A
8
A
9
A
11
G
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - 300 PDIP
28 - 600 PDIP
28 - 300 SOIC
28 - 350 SOIC
STK11C88-3
July 1999 5-12
ABSOLUTE MAXIMUM RATINGS
a
Volt age on Input Relati ve to VSS. . . . . . . . . . –0.6V to (VCC + 0.5V)
Volt age on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
DC CHARACTERISTICS (VCC = 3.0V-3.6V)
Note b: I
CC
1
and I
CC
3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: I
CC
2
is the average current required for the duration of the STORE cycle (t
STORE
).
Note d: E
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
CAPACITANCE
e
(TA = 25°C, f = 1.0MHz)
Note e: These parameters are guaranteed but not tested.
SYMBOL PARAMETER
COMMERCIAL INDUSTRIAL
UNITS NOTES
MIN MAX MIN MAX
I
CC
1
b
Average V
CC
Current 35
30
37
32
mA
mA
t
AVAV
= 45ns
t
AVAV
= 55ns
I
CC
2
c
Average V
CC
Current During STORE 33mAAll Inputs Don’t Care, V
CC
= max
I
CC
3
b
Average VCC Current at t
AVAV
= 200ns
3.3V, 25°C, T ypi cal
88mA
W
≥ (V
CC
– 0.2V)
All Others Cycling, CMOS Levels
I
SB
1
d
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
9
8
10
9
mA
mA
t
AVAV
= 45ns, E ≥ V
IH
t
AVAV
= 55ns, E ≥ V
IH
I
SB
2
d
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
11mA
E
≥ (VCC - 0.2V)
All Others V
IN
≤ 0.2V or ≥ (VCC – 0.2V)
I
ILK
Input Leakage Current
±1 ±1 µA
V
CC
= max
V
IN
= VSS to V
CC
I
OLK
Off-State Output Leakage Current
±5 ±5 µA
V
CC
= max
V
IN
= VSS to VCC, E or G ≥ VIH
V
IH
Input Logic “1” Volta ge 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
V
IL
Input Logic “0” Volta ge VSS – .5 0.8 VSS – .5 0.8 V All Inputs
V
OH
Output Logic “1” Voltage 2.4 2.4 V I
OUT
= –1mA
V
OL
Output Logic “0” Voltage 0.4 0.4 V I
OUT
= 2mA
T
A
Operating Temperature 0 70 –40 85 °C
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3.0V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
Input Capacitance 5 pF ∆V = 0 to 3V
C
OUT
Output Capacitance 7 pF ∆V = 0 to 3V
Figure 1: AC Output Loading
1.1KOhms
30 pF
1.55KOhms
3.0V
INCLUDING
OUTPUT
SCOPE AND
FIXTURE
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
STK11C88-3
July 1999 5-13
SRAM READ CYCLES #1 & #2 (VCC = 3.0V-3.6V)
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E
and G < V
IL
and W > VIH; device is continuously selected.
Note h: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
f, g
SRAM READ CYCLE #2: E Controlledf
NO.
SYMBOLS
PARAMETER
STK11C88-3-45 STK11C88-3-55
UNITS
#1, #2 Alt. MIN MAX MIN MAX
1t
ELQV
t
ACS
Chip Enable Access Time 45 55 ns
2t
AVAV
f
t
RC
Read Cycle Time 45 55 ns
3t
AVQV
g
t
AA
Address Access Time 45 55 ns
4t
GLQV
t
OE
Output Enable to Data Valid 20 25 ns
5t
AXQX
g
t
OH
Output Hol d after Address Ch ange 5 3 ns
6t
ELQX
t
LZ
Chip Enable to Output Active 5 5 ns
7t
EHQZ
h
t
HZ
Chip Disable to Output Inactive 15 20 ns
8t
GLQX
t
OLZ
Output Enable to Output Active 0 0 ns
9t
GHQZ
h
t
OHZ
Output Disable to Outpu t Inactive 15 20 ns
10 t
ELICCH
e
t
PA
Chip Enable to Power Active 0 0 ns
11 t
EHICCL
d, e
t
PS
Chip Disable to Power Standby 45 55 ns
DATA VA LID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
6
t
ELQX
STANDBY
DATA VALID
8
t
GLQX
4
t
GLQV
DQ (DATA
E
ADDRESS
2
t
AVAV
G
I
CC
ACTIVE
1
t
ELQV
10
t
ELICCH
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
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