SIMTEK STK11C68-C25I, STK11C68-C20, STK11C68-C25, STK11C68-S45I, STK11C68-S35I Datasheet
...
STK11C68
8K x 8 nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• 20ns, 25ns, 35ns and 45ns Access Times
• STORE to EEPROM Initiated by Software
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
at 200ns Cycle Time
CC
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention over Full Industrial
Temperature Range
• Commercial and Industrial Temperatures
• 28-Pin DIP and SOIC Packages
BLOCK DIAGRAM
EEPROM ARRAY
ARRAY
2
A3A
128 x 512
A
A
4
STORE
RECALL
10
STORE/
RECALL
CONTROL
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
A
5
A
6
A
7
A
8
A
9
A
11
A
12
0
1
2
3
4
5
6
7
STATIC RAM
ROW DECODER
COLUMN I/O
COLUMN DEC
A0A
INPUT BUFFERS
128 x 512
1
DESCRIPTION
The Simtek STK11C68 is a fast static RAM with a
nonvolatile, electrically erasable
PROM element
incorporated in each static memory cell. The
can be read and written an unlimited number of
times, while independent nonvolatile data resides in
the
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation), or from EEPROM to
SRAM (the RECALL operation), take place using a
software sequence. Transfers from the
the
SRAM (the RECALL operation) also take place
EEPROM to
automatically on restoration of power.
The STK11C68 is pin-compatible with industry-
standard
SRAMs. MIL-STD-883 device is also
available (STK11C68-M).
PIN CONFIGURATIONS
1
SOFTWARE
DETECT
A0-A
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
12
V
SS
28
V
2
3
4
5
6
7
8
9
10
11
12
13
14
CC
27
W
26
NC
25
A
8
A
24
9
A
23
11
22
G
21
A
10
20
E
19
DQ
7
18
DQ
6
DQ
5
DQ
4
DQ
3
28 - 300 PDIP
28 - 300 CDIP
28 - 350 SOIC
17
16
15
PIN NAMES
A0 - A
12
W Write Enable
G
E
W
DQ0 - DQ
E Chip Enable
G Output Enable
V
CC
V
SS
7
Address Inputs
Data In/Out
Power (+ 5V)
Ground
SRAM
June 1999 4-21
STK11C68
ABSOLUTE MAXIMUM RATINGS
Voltage on Input Relative to VSS. . . . . . . . . . –0.6Vto (VCC+ 0.5V)
Voltage on DQ
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC Output Current (1 output at a time, 1s duration). . . . . . . .15mA
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
0-7
a
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress ratingonly,and functional operation of thedevice atconditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
SYMBOL PARAMETER
c
I
I
I
I
I
I
I
V
V
V
V
T
Note b: The STK11C68-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
Note d: I
Note e:
Average VCC Current 100
CC
1
d
Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC= max
CC
2
c
Average VCC Current at t
CC
3
5V, 25˚C, Typical
e
AverageVCC Current
SB
1
(Standby, Cycling TTL Input Levels)
e
VCC Standby Current
SB
2
(Standby, Stable CMOS Input Levels)
Input Leakage Current
ILK
Off-State Output Leakage Current
OLK
Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
IH
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
IL
Output Logic “1” Voltage 2.4 2.4 V I
OH
Output Logic “0” Voltage 0.4 0.4 V I
OL
Operating Temperature 0 70 –40 85 °C
A
and I
CC
CC
E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
CC
1
3
is the average current required for the duration of theSTORE cycle (t
2
AVAV
= 200ns
COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX
N/A
STORE
N/A
).
90
75
65
28
24
21
90
75
65
10 10 mA
32
27
23
20
750 750 µA
±1 ±1 µA
±5 ±5 µA
UNITS NOTES
t
mA
mA
mA
mA
mA
mA
mA
mA
= 20ns
AVAV
t
= 25ns
AVAV
t
= 35ns
AVAV
t
= 45ns
AVAV
W ≥ (VCC– 0.2V)
All Others Cycling, CMOS Levels
t
= 20ns, E≥ V
AVAV
t
= 25ns, E ≥ V
AVAV
t
= 35ns, E≥ V
AVAV
t
= 45ns, E≥ V
AVAV
E ≥ (VCC - 0.2V)
All Others V
VCC= max
V
= VSS to V
IN
VCC= max
V
= VSS to VCC, E orG ≥ V
IN
=– 4mA
OUT
= 8mA
OUT
IH
IH
IH
IH
≤ 0.2V or ≥ (VCC – 0.2V)
IN
CC
IH
b
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
CAPACITANCE
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
C
OUT
Input capacitance 8 pF ∆V = 0 to 3V
Output Capacitance 7 pF ∆V = 0 to 3V
f
(TA = 25°C, f = 1.0MHz)
Note f: These parameters are guaranteed but not tested.
June 1999 4-22
OUTPUT
5.0V
480 Ohms
30 pF
255 Ohms
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
STK11C68
SRAM READ CYCLES #1 & #2 (V
NO.
SYMBOLS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1t
ELQV
2t
AVAV
3t
AVQV
4t
GLQV
5t
AXQX
6t
ELQX
7t
EHQZ
8t
GLQX
9t
GHQZ
10 t
ELICCH
11 t
EHICCL
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes
Note i: Measured ± 200mV from steady state output voltage.
t
ACS
g
t
RC
h
t
AA
t
OE
h
t
OH
t
LZ
i
t
HZ
t
OLZ
i
t
OHZ
f
t
PA
e, f
t
PS
E, G < VILand W > VIH; device is continuously selected.
PARAMETER
Chip Enable Access Time 20 25 35 45 ns
Read Cycle Time 20 25 35 45 ns
Address Access Time 22 25 35 45 ns
Output Enable to Data Valid 8 10 15 20 ns
Output Hold after Address Change 5555ns
Chip Enable to Output Active 5555ns
Chip Disable to Output Inactive 7 10 13 15 ns
Output Enable to Output Active 0000ns
Output Disable to Output Inactive 7 10 13 15 ns
Chip Enable to Power Active 0000ns
Chip Disable to Power Standby 25 25 35 45 ns
SRAM READ CYCLE #1: Address Controlled
ADDRESS
t
DQ (DATA OUT)
t
AXQX
5
STK11C68-20 STK11C68-25 STK11C68-35 STK11C68-45
g, h
2
t
AVAV
3
AVQV
DATA VALID
= 5.0V + 10%)
CC
b
UNITS
SRAM READ CYCLE #2: E Controlled
ADDRESS
E
t
ELQX
6
g
t
AVAV
2
t
ELQV
1
G
4
t
GLQV
8
t
GLQX
DQ (DATA OUT)
10
t
ELICCH
I
CC
STANDBY
ACTIVE
June 1999 4-23
DATA VALID
t
GHQZ
11
t
EHICCL
7
t
EHQZ
9
Loading...