SIMTEK STK11C68-5C45M, STK11C68-5C35M, STK11C68-5L55M, STK11C68-5L45M, STK11C68-5K55M Datasheet
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STK11C68-M
4-31
STK11C68-M
CMOS nvSRAM
High Performance
8K x 8 Nonvolatile Static RAM
MIL-STD-883/SMD # 5962-92324
LOGIC BLOCK DIAGRAM PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A
A
A
A
A
A
A
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
V
W
NC
A
A
G
A
E
SS
7
6
5
4
3
2
1
0
0
1
2
8
9
10
7
6
5
4
3
CC
A
11
A
12
28 - 300 C-DIP
28 - LCC
PIN NAMES
A
A
A
A
A
A
4
5
6
7
8
EEPROM ARRAY
256 x 256
STORE
RECALL
STATIC RAM
ARRAY
256 x 256
ROW DECODER
STORE/
RECALL
CONTROL
AAAAA
0
1210
12
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
1
2
3
4
5
6
7
G
E
W
COLUMN I/O
COLUMN DECODER
INPUT BUFFERS
AA
011
A
3
A
9
12
A0 - A
12
Address Inputs
W Write Enable
DQ0 - DQ7Data In/Out
E Chip Enable
G Output Enable
V
CC
Power (+5V)
V
SS
Ground
DESCRIPTION
The Simtek STK11C68-M is a fast static RAM (35, 45
and 55ns), with a nonvolatile electrically-erasable PROM
(EEPROM) element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent nonvolatile data
resides in EEPROM. Data transfers from the SRAM to
the EEPROM (
STORE
), or from the EEPROM to the
SRAM (
RECALL
) are initiated through software sequences. It combines the high performance and ease
of use of a fast SRAM with nonvolatile data integrity.
The STK11C68-M is pin compatible with industry standard SRAMs and is available in a 28-pin 300 mil
ceramic DIP or 28-pad LCC package. Commercial and
industrial devices are also available.
FEATURES
• 35, 45 and 55ns Access Times
• 17, 20 and 25ns Output Enable Access
• Unlimited Read and Write to SRAM
• Software
STORE
Initiation
• Automatic
STORE
Timing
• 100,000
STORE
cycles to EEPROM
• 10 year data retention in EEPROM
• Automatic
RECALL
on Power Up
• Software
RECALL
Initiation
• Unlimited
RECALL
cycles from EEPROM
• Single 5V ± 10% Operation
• Available in multiple standard packages
A
A
A
A
A
A
A
A
A
A
A
A
DQ
DQ
DQDQDQ
DQ
DQ
G
A
E
DQ
Vss
NC
Vcc
W
NC
7
12
6
5
4
3
2
1
0
0
1
8
9
11
10
7
6
234
5
TOP VIEW
4
5
6
7
8
9
10
11
12
32128 27
26
25
24
23
22
21
20
19
18
1716151413
STK11C68-M
4-32
I
CC
b
Average VCC Current 90 mA t
AVAV
= 35ns
85 mA t
AVAV
= 45ns
80 mA t
AVAV
= 55ns
I
CC
d
Average VCC Current 50 mA E ≥ (VCC – 0.2V)
during STORE cycle all others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
I
SB
c
Average VCC Current 27 mA t
AVAV
= 35ns
(Standby, Cycling TTL Input Levels) 23 mA t
AVAV
= 45ns
20 mA t
AVAV
= 55ns
E ≥ VIH; all others cycling
I
SB
c
Average VCC Current 2 mA E ≥ (VCC – 0.2V)
(Standby, Stable CMOS Input Levels) all others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
I
ILK
Input Leakage Current (Any Input) ±1 µAVCC = max
VIN = VSS to V
CC
I
OLK
Off State Output Leakage Current ±5 µAVCC = max
VIN = VSS to V
CC
V
IH
Input Logic "1" Voltage 2.2 VCC+.5 V All Inputs
V
IL
Input Logic "0" Voltage VSS–.5 0.8 V All Inputs
V
OH
Output Logic "1" Voltage 2.4 V I
OUT
= –4mA
V
OL
Output Logic "0" Voltage 0.4 V I
OUT
= 8mA
T
A
Operating Temperature –55 125 °C
ABSOLUTE MAXIMUM RATINGS
a
Voltage on typical input relative to VSS. . . . . . . . . . . . . –0.6V to 7.0V
Voltage on DQ
0-7
and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V)
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
Note a: Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
(One output at a time, one second duration)
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCEe (T
A
=25°C, f=1.0MHz)
Note e: These parameters are guaranteed but not tested. Figure 1: AC Output Loading
5.0V
Output
480 Ohms
30pF
INCLUDING
SCOPE
AND FIXTURE
255 Ohms
C
IN
Input Capacitance 5 pF ∆V = 0 to 3V
C
OUT
Output Capacitance 7 pF ∆V = 0 to 3V
SYMBOL PARAMETER MAX UNITS CONDITIONS
1
2
1
2
SYMBOL PARAMETER MIN MAX UNITS NOTES
Note b: ICC is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: I
CC
is the average current required for the duration of the store cycle (t
STORE
) after the sequence (tWC) that initiates the cycle.
2
1
STK11C68-M
4-33
#1, #2 Alt. MIN MAX MIN MAX MIN MAX
NO. PARAMETER UNITS
(VCC = 5.0V ± 10%)
Note c: Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note g: For READ CYCLE #1 and #2, W must be high for entire cycle.
Note h: Device is continuously selected with E low and G low.
Note i: Measured ± 200mV from steady state output voltage.
READ CYCLE #1
g,h
W
DQ (Data Out)
ADDRESS
DATA VALID
5
t
AXQX
11A
t
WHQV
2
t
AVAV
3
t
AVQV
READ CYCLE #2
g
ADDRESS
E
G
DQ (Data Out)
DATA VALID
I
CC
W
2
t
AVAV
1
t
ELQV
6
t
ELQX
4
t
GLQV
8
t
GLQX
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
10
t
ELICCH
11A
t
WHQV
ACTIVE
STANDBY
READ CYCLES #1 & #2
1t
ELQV
t
ACS
Chip Enable Access Time 35 45 55 ns
2t
AVAV
g
t
RC
Read Cycle Time 35 45 55 ns
3t
AVQV
h
t
AA
Address Access Time 35 45 55 ns
4t
GLQV
t
OE
Output Enable to Data Valid 20 25 25 ns
5t
AXQX
t
OH
Output Hold After Address Change 5 5 5 ns
6t
ELQX
t
LZ
Chip Enable to Output Active 5 5 5 ns
7t
EHQZ
i
t
HZ
Chip Disable to Output Inactive 17 20 25 ns
8t
GLQX
t
OLZ
Output Enable to Output Active 0 0 0 ns
9t
GHQZ
i
t
OHZ
Output Disable to Output Inactive 17 20 25 ns
10 t
ELICCH
e
t
PA
Chip Enable to Power Active 0 0 0 ns
11 t
EHICCL
c,e
t
PS
Chip Disable to Power Standby 35 45 55 ns
11A t
WHQV
t
WR
Write Recovery Time 45 55 65 ns
SYMBOLS STK11C68-35M STK11C68-45M STK11C68-55M
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