SIMTEK STK11C48-S45I, STK11C48-S35I, STK11C48-S45, STK11C48-S35, STK11C48-S25I Datasheet
...
July 1999 3-11
STK11C48
2K x 8 nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• 20ns, 25ns, 35ns and 45ns Access Times
• STORE to EEPROM Initiated by Software
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA T ypical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to EEPROM
• 100-Year Data Retention in EEPROM
• Commercial and Industrial Temperatures
• 28-Pin 300 mil PDIP, 300 mil SOIC and
350 mil SOIC Packages
DESCRIPTION
The Simtek STK11C48 is a fast static RAM with a
nonvolatile, electrically erasable
PROM element
incorporated in each static memory cell. The
SRAM
can be read and written an unlimited number of
times, while independent, nonvolatile data resides in
the
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation), or from EEPROM to
SRAM (the RECALL operation), take place using a
software sequence. Transfers from the
EEPROM to
the
SRAM (the RECALL operation) also take place
automatically on restoration of power.
BLOCK DIAGRAM
COLUMN I/O
COLUMN DEC
STATIC RAM
ARRAY
32 x 512
ROW DECODER
INPUT BUFFERS
EEPROM ARRAY
32 x 512
STORE/
RECALL
CONTROL
STORE
RECALL
A
5
A
6
A
9
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
SOFTWARE
DETECT
A0 - A
10
G
E
W
A
8
A
7
A
10
A3A
2
A0A
1
A
4
PIN CONFIGURATIONS
NC
NC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
V
CC
NC
A
8
A
9
NC
G
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - 300 PDIP
28 - 300 SOIC
28 - 350 SOIC
PIN NAMES
A0 - A
10
Address Inputs
W Write Enable
DQ0 - DQ
7
Data In/Out
E Chip Enable
G Output Enable
V
CC
Power (+ 5V)
V
SS
Ground
STK11C48
July 1999 3-12
ABSOLUTE MAXIMUM RATINGS
a
Volt age on Input Relati ve to VSS. . . . . . . . . . –0.6V to (VCC + 0.5V)
Volt age on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
b
Note b: The STK11C48-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
CC
1
and I
CC
3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note d: I
CC
2
is the average current required for the duration of the STORE cycle (t
STORE
).
Note e: E
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
CAPACITANCE
f
(TA = 25°C, f = 1.0MHz)
Note f: These parameters are guaranteed but not tested.
SYMBOL PARAMETER
COMMERCIAL INDUSTRIAL
UNITS NOTES
MIN MAX MIN MAX
I
CC
1
c
Average VCC Current 95
85
75
65
N/A
90
75
65
mA
mA
mA
mA
t
AVAV
= 20ns
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
I
CC
2
d
Average VCC Current during STORE 33mAAll Inputs Don’t Care, V
CC
= max
I
CC
3
c
Average VCC Current at t
AVAV
= 200ns
5V, 25°C, Typical
10 10 mA
W
≥ (V
CC
– 0.2V)
All Others Cycling, CMOS Levels
I
SB
1
e
Average VCC Current
(Standby, Cycling TTL Input Levels)
30
25
21
18
N/A
26
22
19
mA
mA
mA
mA
t
AVAV
= 20ns, E ≥ V
IH
t
AVAV
= 25ns, E ≥ V
IH
t
AVAV
= 35ns, E ≥ V
IH
t
AVAV
= 45ns, E ≥ V
IH
I
SB
2
e
VCC Standby Current
(Standby, Stab le CMOS Input Levels)
750 750 µA
E
≥ (VCC - 0.2V)
All Others V
IN
≤ 0.2V or ≥ (VCC – 0.2V)
I
ILK
Input Leakage Current
±1 ±1 µA
V
CC
= max
V
IN
= VSS to V
CC
I
OLK
Off-State Output Leakage Current
±5 ±5 µA
V
CC
= max
V
IN
= VSS to VCC, E or G ≥ VIH
V
IH
Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs
V
IL
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
V
OH
Output Logic “1” Voltage 2.4 2.4 V I
OUT
= – 4mA
V
OL
Output Logic “0” Voltage 0.4 0.4 V I
OUT
= 8mA
T
A
Operating Temperature 0 70 –40 85 °C
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
Input Capacitance 8 pF ∆V = 0 to 3V
C
OUT
Output Capacitance 7 pF ∆V = 0 to 3V
Figure 1: AC Output Loading
480 Ohms
30 pF
255 Ohms
5.0V
INCLUDING
OUTPUT
SCOPE AND
FIXTURE
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
STK11C48
July 1999 3-13
SRAM READ CYCLES #1 & #2 (V
CC
= 5.0V + 10%)
b
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E
, G < V
IL
and W > VIH; device is continuously selected.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
g, h
SRAM READ CYCLE #2: E Controlledg
NO.
SYMBOLS
PARAMETER
STK11C48-20 STK11C48-25 STK11C48-35 STK1 1C48-45
UNITS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1t
ELQV
t
ACS
Chip Enable Access Time 20 25 35 45 ns
2t
AVAV
g
t
RC
Read Cycle Time 20 25 35 45 ns
3t
AVQV
h
t
AA
Address Access Time 22 25 35 45 ns
4t
GLQV
t
OE
Output Enable to Data Valid 8 10 15 20 ns
5t
AXQX
h
t
OH
Output Hol d after Address Change 5 5 5 5 ns
6t
ELQX
t
LZ
Chip Enable to Output Active 5 5 5 5 ns
7t
EHQZ
i
t
HZ
Chip Disable to Output Inactive 7 10 13 15 ns
8t
GLQX
t
OLZ
Output Enable to Output Active 0 0 0 0 ns
9t
GHQZ
i
t
OHZ
Output Disable to Output Inactive 7 10 13 15 ns
10 t
ELICCH
f
t
PA
Chip Enable to Power Active 0 0 0 0 ns
11 t
EHICCL
e, f
t
PS
Chip Disable to Power Standby 25 25 35 45 ns
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
6
t
ELQX
STANDBY
DATA VALID
8
t
GLQX
4
t
GLQV
DQ (DATA OUT)
E
ADDRESS
2
t
AVAV
G
I
CC
ACTIVE
1
t
ELQV
10
t
ELICCH
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
STK11C48
July 1999 3-14
SRAM WRITE CYC LES #1 & #2 (VCC = 5.0V + 10%)
b
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E
or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlled
k
SRAM WRITE CYCLE #2: E Controlled
k
NO.
SYMBOLS
PARAMETER
STK11C48-20 STK11C48-25 STK11C48-35 STK11C48-45
UNITS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
12 t
AVAV
t
AVAV
t
WC
Write Cycle Time 20 25 35 45 ns
13 t
WLWH
t
WLEH
t
WP
Write Pulse Width 15 20 25 3 0 ns
14 t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write 15 20 25 30 ns
15 t
DVWH
t
DVEH
t
DW
Data Set-up to End of Write 8 10 12 15 ns
16 t
WHDX
t
EHDX
t
DH
Data Hold after End of Write 0 0 0 0 ns
17 t
AVWH
t
AVEH
t
AW
Address Set-up to End of Write 15 20 25 30 ns
18 t
AVWL
t
AVEL
t
AS
Address Set-up to Start of Write 0 0 0 0 ns
19 t
WHAX
t
EHAX
t
WR
Address Hold after End of Write 0 0 0 0 ns
20 t
WLQZ
i, j
t
WZ
Write Enable to Output Disable 7 10 13 15 ns
21 t
WHQX
t
OW
Output Active after End of Write 5 5 5 5 ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
t
AVAV
W
16
t
WHDX
DATA IN
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVWH
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
DATA OUT
E
ADDRESS
12
t
AVAV
W
DATA IN
13
t
WLEH
17
t
AVEH
DATA VALID
HIGH IMPEDANCE
14
t
ELEH
18
t
AVEL
15
t
DVEH
19
t
EHAX
16
t
EHDX
STK11C48
July 1999 3-15
STORE INHIBIT/POWER-UP RECALL (VCC = 5.0V + 10%)
b
Note l: t
RESTORE
starts from the time VCC rises above V
SWITCH
.
STORE INHIBIT/POWER-UP RECALL
NO.
SYMBOLS
PARAMETER
STK11C48
UNITS NOTES
Standard MIN MAX
22 t
RESTORE
Power-up RECALL Duration 550 µsl
23 t
STORE
STORE Cycle Duration 10 ms
24 V
SWITCH
Low Voltage Trigger Level 4.0 4.5 V
25 V
RESET
Low Voltage Reset Level 3.9 V
V
CC
V
SWITCH
V
RESET
OWER-UP RECALL
DQ (DATA OUT)
STORE INHIBIT
5V
22
t
RESTORE
24
25
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
STORE INHIBIT
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
STORE INHIBI T
RECALL WHEN
V
CC
RETURNS
ABOVE V
SWITCH
STK11C48
July 1999 3-16
SOFTW ARE ST ORE/RECALL MODE SELECTION
Note m: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
SOFTW ARE ST ORE/RECALL CYCLE
n, o
(VCC = 5.0V ± 10%)
b
Note n: The software sequence is clocked with E controlled reads.
Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL
Mode Selection Table: (000, 555, 2AA, 7FF, 0F0,
70F) for a STORE cycle or (000, 555, 2AA, 7FF, 0F0, 70E) for a RECALL cycle. W
must be high during all six consecutive cycles.
SOFTW ARE STORE/RECALL CYCLE: E Controlled
o
E W A10 - A0 (hex) MODE I/O NOTES
LH
000
555
2AA
7FF
0F0
70F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
m
LH
000
555
2AA
7FF
0F0
70E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
m
NO. SYMBOLS PARAMETER
STK11C48-20 STK11C48-25 STK11C48-35 STK11C48-45
UNITS
MIN MAX MIN MAX MIN MAX MIN MAX
26 t
AVAV
STORE/RECALL Initiation Cycle Time 20 25 35 45 ns
27 t
AVEL
n
Address Set-up Time 0000ns
28 t
ELEH
n
Clock Pulse Width 15202530ns
29 t
ELAX
n
Address Hold Time 15 20 20 20 ns
30 t
RECALL
n
RECALL Dura t i on 20 20 20 20 µs
HIGH IMPEDANCE
ADDRESS #6ADDRESS #1
DATA VALID
26
t
AVAV
DATA VALID
DQ (DATA OUT)
E
ADDRESS
23 30
t
STORE
/ t
RECALL
26
t
AVAV
27
t
AVEL
28
t
ELEH
29
t
ELAX
STK11C48
July 1999 3-17
The STK11C48 is a versatile memory chip that provides several modes of operation. The STK11C48
can operate as a standard 8K x 8
SRAM. It has an
8K x 8
EEPROM shadow to which the SRAM informa-
tion can be copied or from which the
SRAM can be
updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK11C48 is a high-speed memory
and so must have a high-frequency bypass capacitor of approximately 0.1µF connected between V
cc
and Vss, using leads and traces that are as short as
possible. As with all high-speed
CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK11C48 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A
0-10
determines which of the 2,048 data
bytes will be accessed. When the
READ is initiated
by an address transition, the outputs will be valid
after a delay of
t
AVQV
(READ cycle #1). If the READ is
initiated by E
or G, the outputs will be valid at t
ELQV
or
at
t
GLQV
, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the t
AVQV
access time without the need for transitions on any control input pins, and will remain valid
until another address change or until E
or G is
brought high.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the
WRITE cycle and must remain stable
until either E
or W goes high at the end of the cycle.
The data on the common I/O pins DQ
0-7
will be writ-
ten into the memory if it is valid t
DVWH
before the end
of a W
controlled WRITE or t
DVEH
before the end of an
E
controlled WRITE.
It is recommended that G
be kept high during the
entire
WRITE cycle to avoid data bus contention on
the common I/ O li nes. If G
is left low, internal circuitry
will turn off the output buffers t
WLQZ
after W goes low.
SOFTWARE NONVOLATILE STORE
The STK11C48 software STORE cycle is initiated by
executing sequential
READ cycles from six specific
address locations. During the
STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the
SRAM data into
nonvolatile memory. Once a
STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of
READs from specific
addresses is used for
STORE initiation, it is impor-
tant that no other
READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no
STORE or RECALL will take place.
To initiate the software
STORE cycle, the following
READ sequence must be performed:
1. Read address 000 (hex) Va lid READ
2. Read address 555 (hex) Va lid READ
3. Read address 2AA (hex) Valid READ
4. Read address 7FF (hex) Valid READ
5. Read address 0F0 (hex) Valid READ
6. Read address 70F (hex) Initiate STORE cycle
The software sequence must be clocked with E controlled
READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that
READ cycles
and not
WRITE cycles be used in the sequence,
although it is not necessary that G
be low for the
sequence to be valid. After the t
STORE
cycle time has
been fulfilled, the
SRAM will again be activated for
READ and WRITE operation.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of
READ operations in a manner similar to the soft-
ware
STORE initiation. To initiate the RECALL cycle,
the following sequence of
READ operations must be
performed:
1. Read address 000 (hex) Va lid READ
2. Read address 555 (hex) Va lid READ
3. Read address 2AA (hex) Valid READ
4. Read address 7FF (hex) Valid READ
5. Read address 0F0 (hex) Valid READ
6. Read address 70E (hex) Initiate RECALL cycle
DEVICE OPERATION
STK11C48
July 1999 3-18
Internally, RECALL is a two-step procedure. First,
the
SRAM data is cleared, and second, the nonvola-
tile information is transferred into the
SRAM cells.
After the t
RECALL
cycle time the SRAM will once again
be ready for
READ and WRITE operations. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled
an unlimited number of times.
POWER-UP RECALL
During power up, or after any low-power condition
(V
CC
< V
RESET
), an internal RECALL request will be
latched. When V
CC
once again exceeds the sense
voltage of V
SWITCH
, a RECALL cycle will automatically
be initiated and will take t
RESTORE
to complete.
If the STK11C48 is in a
WRITE state at the end of
power-up
RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W
and system
V
CC
or between E and system VCC.
HARDWARE PROTECT
The STK11C48 offers hardware protection against
inadvertent
STORE operation during low-voltage
conditions. When V
CC
< V
SWITCH
, all software STORE
operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C48 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
CC
and READ cycle
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
perature range, V
CC
= 5.5V, 100% duty cycle on
chip enable). Figure 3 shows the same relationship
for
WRITE cycles. If the chip enable duty cycle is
less than 100%, only standby current is drawn
when the chip is disabled. The overall average current drawn by the STK11C48 depends on the following items: 1)
CMOS vs. TTL input levels; 2) the
duty cycle of chip enable; 3) the overall cycle rate
for accesses; 4) the ratio of
READs to WRITEs; 5)
the operating temperature; 6) the V
cc
level; and 7) I/
O loading.
Figure 2: I
CC
(max) Reads
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
Figure 3: ICC (max) Writes
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
STK11C48
July 1999 3-19
ORDERING INFORM ATION
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C
)
Access Time
20 = 20ns (Commercial only)
25 = 25ns
35 = 35ns
45 = 45ns
Package
P = Plastic 28-pin 300 mil DIP
N = Plastic 28-pin 300 mil SOIC
S = Plastic 28-pin 350 mil SOIC
- P 25 I
STK11C48
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