SIMTEK STK10C68-5L55M, STK10C68-5L35M, STK10C68-5L45M, STK10C68-5K55M, STK10C68-5K45M Datasheet
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STK10C68-M
A
A
A
A
A
A
A
A
A
A
A
A
DQ
DQ
DQDQDQ
DQ
DQ
G
A
E
DQ
Vss
NE
Vcc
W
NC
7
12
6
5
4
3
2
1
0
0
1
8
9
11
10
7
6
2
3
4
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TOP VIEW
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32128 27
26
25
24
23
22
21
20
19
18
1716151413
STK10C68-M
CMOS nvSRAM
High Performance
8K x 8 Nonvolatile Static RAM
MIL-STD-833/SMD 5962 - 93056
FEATURES
• 35, 45 and 55ns Access Times
• 20 and 25ns Output Enable Access
• Unlimited Read and Write to SRAM
• Hardware
• Automatic
• 100,000
STORE
STORE
STORE
Initiation
Timing
cycles to EEPROM
• 10 year data retention in EEPROM
• Automatic
• Hardware
• Unlimited
RECALL
RECALL
RECALL
on Power Up
Initiation
cycles from EEPROM
• Single 5V±10% Operation
• Available in multiple standard packages
LOGIC BLOCK DIAGRAM
EEPROM ARRAY
256 x 256
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
ROW DECODER
INPUT BUFFERS
STATIC RAM
ARRAY
256 x 256
COLUMN I/O
COLUMN DECODER
AAAAA
0 1 2 10 11
STORE
RECALL
DESCRIPTION
The Simtek STK10C68-M is a fast static RAM (35, 45
and 55ns), with a nonvolatile electrically-erasable PROM
(EEPROM) element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent nonvolatile data
resides in EEPROM. Data may easily be transferred
from the SRAM to the EEPROM (
EEPROM to the SRAM (
RECALL
STORE
), or from the
) using the NE pin. It
combines the high performance and ease of use of a
fast SRAM with nonvolatile data integrity.
The STK10C68 features industry standard pinout for
nonvolatile RAMs in a 28-pin 300 mil ceramic DIP, and
28-pad LCC packages. Commercial and industrial
temperature devices are also available.
PIN CONFIGURATIONS
1
28
2
27
26
3
7
25
4
6
24
5
5
23
6
4
7
22
3
8
21
2
9
20
1
10
19
0
18
11
0
17
12
1
16
13
2
15
14
28-300 CDIP
STORE/
RECALL
CONTROL
28-LCC
PIN NAMES
A0 - A
W Write Enable
12
Address Inputs
NE
A
12
A
A
A
A
A
A
A
A
DQ
DQ
DQ
V
SS
DQ0 - DQ7Data In/Out
E Chip Enable
G
NE
G Output Enable
NE Nonvolatile Enable
V
E
W
CC
V
SS
Power (+5V)
Ground
4-11
V
CC
W
NC
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
STK10C68-M
ABSOLUTE MAXIMUM RATINGS
Voltage on typical input relative to V
Voltage on DQ
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V)
0-7
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
. . . . . . . . . . . . . –0.6V to 7.0V
SS
a
Note a: Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
(One output at a time, one second duration)
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
SYMBOL PARAMETER MIN MAX UNITS NOTES
b
I
CC
I
CC
I
SB
I
SB
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note b: ICC is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: I
Average VCC Current 90 mA t
1
d
Average VCC Current 50 mA E ≥ (VCC – 0.2V)
2
during
STORE
c
Average VCC Current 27 mA t
1
(Standby, Cycling TTL Input Levels) 23 mA t
c
Average VCC Current 2 mA E ≥ (VCC – 0.2V)
2
(Standby, Stable CMOS Input Levels) all others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
Input Leakage Current (Any Input) ±1 µAVCC = max
Off State Output Leakage Current ±5 µAVCC = max
Input Logic "1" Voltage 2.2 VCC+.5 V All Inputs
Input Logic "0" Voltage VSS–.5 0.8 V All Inputs
Output Logic "1" Voltage 2.4 V I
Output Logic "0" Voltage 0.4 V I
Operating Temperature –55 125 °C
1
is the average current required for the duration of the store cycle (t
CC
2
cycle all others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
STORE
85 mA t
80 mA t
20 mA t
) after the sequence (tWC) that initiates the cycle.
= 35ns
AVAV
= 45ns
AVAV
= 55ns
AVAV
= 35ns
AVAV
= 45ns
AVAV
= 55ns
AVAV
E ≥ VIH; all others cycling
VIN = VSS to V
VIN = VSS to V
= –4mA
OUT
= 8mA
OUT
CC
CC
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCEe (T
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
C
Note e: These parameters are guaranteed but not tested.
Input Capacitance 5 pF ∆V = 0 to 3V
IN
Output Capacitance 7 pF ∆V = 0 to 3V
OUT
=25°C, f=1.0MHz)
A
4-12
Output
255 Ohms
Figure 1: AC Output Loading
5.0V
480 Ohms
INCLUDING
AND FIXTURE
30pF
SCOPE
STK10C68-M
READ CYCLES #1 & #2
NO. PARAMETER UNITS
1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
11A t
SYMBOLS STK10C68-35M STK10C68-45M STK10C68-55M
#1, #2 Alt. MIN MAX MIN MAX MIN MAX
t
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
WHQV
g
h
i
i
e
c,e
Chip Enable Access Time 35 45 55 ns
ACS
t
Read Cycle Time 35 45 55 ns
RC
t
Address Access Time 35 45 55 ns
AA
t
Output Enable to Data Valid 20 25 25 ns
OE
t
Output Hold After Address Change 5 5 5 ns
OH
t
Chip Enable to Output Active 5 5 5 ns
LZ
t
Chip Disable to Output Inactive 17 20 25 ns
HZ
t
Output Enable to Output Active 0 0 0 ns
OLZ
t
Output Disable to Output Inactive 17 20 25 ns
OHZ
t
Chip Enable to Power Active 0 0 0 ns
PA
t
Chip Disable to Power Standby 35 45 55 ns
PS
t
Write Recovery Time 45 55 65 ns
WR
(VCC = 5.0V ± 10%)
Note c: Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note f: NE must be high during entire cycle.
Note g: For READ CYCLE #1 and #2, W and NE must be high for entire cycle.
Note h: Device is continuously selected with E low and G low.
Note i: Measured ± 200mV from steady state output voltage.
f,g,h
READ CYCLE #1
2
t
AVAV
ADDRESS
3
t
AVQV
DATA VALID
DQ (Data Out)
t
AXQX
5
W
READ CYCLE #2
ADDRESS
E
G
DQ (Data Out)
I
ACTIVE
STANDBY
CC
W
f,g
10
t
ELICCH
11A
t
WHQV
t
ELQX
2
t
AVAV
1
t
11A
WHQV
t
GLQX
8
t
GLQV
ELQV
4
t
GHQZ
DATA VALID
9
6
t
t
EHQZ
11
t
EHICCL
7
4-13
STK10C68-M
WRITE CYCLES #1 & #2; G high
NO. PARAMETER UNITS
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
SYMBOLS STK10C68-35M STK10C68-45M STK10C68-55M
#1 #2 Alt. MIN MAX MIN MAX MIN MAX
AVAVtAVAVtWC
WLWHtWLEHtWP
ELWHtELEHtCW
DVWHtDVEHtDW
WHDXtEHDXtDH
AVWHtAVEHtAW
AVWLtAVELtAS
WHAXtEHAXtWR
Write Cycle Time 35 45 55 ns
Write Pulse Width 30 35 45 ns
Chip Enable to End of Write 30 35 45 ns
Data Set-up to End of Write 18 20 30 ns
Data Hold After End of Write 0 0 0 ns
Address Set-up to End of Write 30 35 45 ns
Address Set-up to Start of Write 0 0 0 ns
Address Hold After End of Write 0 0 0 ns
WRITE CYCLES #1 & #2; G low
NO. PARAMETER UNITS
12 t
13 t
14 t
15 t
16 t
17 t
18 t
19 t
20 t
21 t
SYMBOLS STK10C68-35M STK10C68-45M STK10C68-55M
#1 #2 Alt. MIN MAX MIN MAX MIN MAX
AVAVtAVAVtWC
WLWHtWLEHtWP
ELWHtELEHtCW
DVWHtDVEHtDW
WHDXtEHDXtDH
AVWHtAVEHtAW
AVWLtAVELtAS
WHAXtEHAXtWR
i,m
WLQZ
WHQX
Write Cycle Time 45 45 55 ns
Write Pulse Width 35 35 45 ns
Chip Enable to End of Write 35 35 45 ns
Data Set-up to End of Write 30 30 30 ns
Data Hold After End of Write 0 0 0 ns
Address Set-up to End of Write 35 35 45 ns
Address Set-up to Start of Write 0 0 0 ns
Address Hold After End of Write 0 0 0 ns
tWZWrite Enable to Output Disable 35 35 35 ns
tOWOutput Active After End of Write 5 5 5 ns
(VCC = 5.0V ± 10%)
(VCC = 5.0V ± 10%)
Note f: NE must be ≥ VIH during entire cycle.
Note i: Measured
Note k: E or W must be ≥ V
Note m: If W is low when E goes low, the outputs remain in the high impedance state.
+ 200mV from steady state output voltage.
during address transitions.
IH
4-14
STK10C68-M
WRITE CYCLE #1: W CONTROLLED
ADDRESS
E
18
t
W
AVWL
DATA IN
DATA OUT
PREVIOUS DATA
WRITE CYCLE #2: E CONTROLLED
ADDRESS
18
t
E
W
DATA IN
AVEL
f,k
f,k
t
17
t
AVWH
20
WLQZ
t
AVEH
12
t
AVAV
14
t
ELWH
13
t
WLWH
15
t
DVWH
DATA VALID
HIGH IMPEDANCE
12
t
AVAV
14
t
ELEH
17
13
t
WLEH
15
t
DVEH
DATA VALID
16
t
WHDX
t
EHDX
t
WHAX
21
t
WHQX
t
EHAX
16
19
19
DATA OUT
HIGH IMPEDANCE
4-15
STK10C68-M
NONVOLATILE MEMORY OPERATION
MODE SELECTION
E W G NE MODE POWER
H X X X Not Selected Standby
L H L H Read RAM Active
L L X H Write RAM Active
L H L L Nonvolatile
L L H L Nonvolatile
LLLL No operation Active
LHHX
RECALL
STORE
n
Active
I
CC
2
STORE CYCLES #1 & #2
NO. PARAMETER MIN MAX UNITS
22 t
23 t
24 t
25 t
26 t
27 t
28 t
Note n: An automatic
VCC must not drop below 4.0V once it has been exceeded for the
Note o: If E is low for any period of time in which W is high and G and NE are low, then a
Note p: Measured with W and NE both returned high, and G returned low. Note that
Note q: Once tWC has been satisfied by NE, G, W and E, the
STORE CYCLE #1: W CONTROLLED
DQ (Data Out)
SYMBOLS
#1 #2 Alt.
p
t
WLQX
WLNH
GHNL
NLWLtNLEL
ELWL
ELQXS
q
t
ELNHStWC
GHEL
WLEL
RECALL
STORE
initiation cycle.
NE
G
W
E
t
also takes place at power up, starting when VCC exceeds 4.0V, and taking t
STORE
STORE
Cycle Time 12 ms
STORE
Initiation Cycle Time 35 ns
Output Disable Set-up to NE Fall 0 ns
Output Disable Set-up to E Fall 0 ns
NE Set-up 0ns
Chip Enable Set-up 0 ns
Write Enable Set-up 0 ns
RECALL
to function properly.
RECALL
STORE
STORE
cycle is completed automatically. Any of NE, G, W or E may be used to terminate the
cycle may be initiated.
cycles are inhibited/aborted by V
o
t
GHNL
24
t
ELWL
26
t
NLWL
27
HIGH IMPEDANCE
t
WLNH
23
t
WLQX
from the time at which VCC exceeds 4.5V.
RECALL
22
(VCC = 5.0V ± 10%)
< 4.0V (
STORE
CC
inhibit).
STORE CYCLE #2: E CONTROLLED
NE
25
t
GHEL
G
W
E
DQ (Data Out)
28
t
WLEL
HIGH IMPEDANCE
o
t
NLEL
26
23
t
ELNHS
22
t
ELQXS
4-16
STK10C68-M
RECALL CYCLES #1, #2 & #3
NO. PARAMETER MIN MAX UNITS
29 t
30 t
31 t
32 t
33 t
34 t
35 t
SYMBOLS
#1 #2 #3
r
t
NLQX
NLNH
GLNLtGLEL
WHNLtWHELtWHGL
NLQZ
s
ELNL
ELQXRtGLQXR
t
ELNHRtGLNH
NLELtNLGL
t
ELGL
RECALL
Cycle Time 25 µs
RECALL
Initiation Cycle Time 35 ns
NE Set-up 0ns
Output Enable Set-up 0 ns
Write Enable Set-up 0 ns
Chip Enable Set-up 0 ns
NE Fall to Outputs Inactive 35 ns
(VCC = 5.0V ± 10%)
Note r: Measured with W and NE both high, and G and E low.
Note s: Once t
RECALL
Note t: If W is low at any point in which both E and NE are low and G is high, then a
RECALL CYCLE #1: NE CONTROLLED
DQ (Data Out)
has been satisfied by NE, G, W and E, the
NLNH
initiation cycle.
NE
G
W
E
t
ELNL
t
WHNL
34
RECALL
cycle is completed automatically. Any of NE, G or E may be used to terminate the
STORE
cycle will be initiated instead of a
RECALL
.
o
30
t
NLNH
32
t
GLNL
33
29
t
t
NLQZ
35
NLQX
HIGH IMPEDANCE
RECALL CYCLE #2: E CONTROLLED
31
t
t
GLEL
NLEL
32
33
t
WHEL
NE
G
W
E
DQ (Data Out)
HIGH IMPEDANCE
RECALL CYCLE #3: G CONTROLLED
31
t
t
WHGL
34
t
ELGL
HIGH IMPEDANCE
NLGL
33
NE
G
W
E
DQ (Data Out)
o
o,t
4-17
30
t
ELNHR
t
30
GLNH
29
t
ELQXR
29
t
GLQXR
STK10C68-M
DEVICE OPERATION
The STK10C68-M has two modes of operation: SRAM
mode and nonvolatile mode, determined by the state of
the NE pin. When in SRAM mode, the memory
operates as a standard fast static RAM. While in
nonvolatile mode, data is transferred in parallel from
SRAM to EEPROM or from EEPROM to SRAM.
SRAM READ
The STK10C68-M performs a
and G are
specified on pins A
LOW and NE and W are HIGH. The address
0-12
data bytes will be accessed. When the
READ cycle whenever E
determines which of the 8192
READ is initiated
by an address transition, the outputs will be valid after
a delay of t
initiated by E or G, the outputs will be valid at t
at t
, whichever is later (READ CYCLE #2). The data
GLQV
(READ CYCLE #1). If the READ is
AVQV
ELQV
or
outputs will repeatedly respond to address changes
within the t
access time without the need for
AVQV
transitions on any control input pins, and will remain
valid until another address change or until E or G is
brought
HIGH or W or NE is brought LOW.
The STK10C68-M is a high speed memory and therefore must have a high frequency bypass capacitor of
approximately 0.1µF connected between DUT V
CC
and VSS using leads and traces that are as short as
possible. As with all high speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
LOW and G is HIGH. While any sequence to achieve
this state will initiate a
CYCLE #1) and E initiation (
practical without risking an unintentional
that would disturb SRAM data. During a
previous nonvolatile data is erased and the
STORE
, only W initiation (
STORE
STORE
CYCLE #2) are
SRAM WRITE
STORE
cycle,
SRAM
contents are then programmed into nonvolatile elements. Once a
and output is disabled and the DQ
STORE
cycle is initiated, further input
pins are tri-stated
0-7
until the cycle is completed.
If E and G are LOW and W and NE are HIGH at the end
of the cycle, a
will go active, signaling the end of the
READ will be performed and the outputs
STORE
.
HARDWARE PROTECT
The STK10C68-M offers two levels of protection to
suppress inadvertent
signals (E, G, W, and NE) remain in the
condition at the end of a
cycle will
not
be started. The
STORE
cycles. If the control
STORE
cycle, a second
STORE
(or
STORE
STORE
RECALL
) will
be initiated only after a transition on any one of these
signals to the required state. In addition to multi-trigger
protection, the STK10C68-M offers hardware protection through V
initiated, and one in progress will discontinue, if V
Sense. A
CC
STORE
cycle will not be
CC
goes below 4.0V. 4.0V is a typical, characterized
value.
SRAM WRITE
A write cycle is performed whenever E and W are
LOW
and NE is HIGH. The address inputs must be stable
prior to entering the
stable until either E or W go
cycle. The data on pins DQ
memory if it is valid t
controlled
controlled
WRITE or t
WRITE.
It is recommended that G be kept
WRITE cycle to avoid data bus contention on common
I/O lines. If G is left
the output buffers t
WRITE cycle and must remain
HIGH at the end of the
will be written into the
0-7
before the end of a W
DVWH
before the end of an E
DVEH
HIGH during the entire
LOW, internal circuitry will turn off
after W goes LOW.
WLQZ
NONVOLATILE STORE
STORE
A
cycle is performed when NE, E and W are
NONVOLATILE RECALL
A
RECALL
LOW and W is HIGH. Like the
cycle is performed when E, G, and NE are
STORE
cycle,
initiated when the last of the four clock signals goes to
the
RECALL
take t
ignored. When the
WRITE state on the input pins will take effect.
Internally,
SRAM data is cleared and second, the nonvolatile
information is transferred into the
RECALL
state. Once initiated, the
to complete, during which all inputs are
NLQX
RECALL
RECALL
is a two step procedure. First, the
completes, any READ or
RECALL
SRAM cells. The
operation in no way alters the data in the
nonvolatile cells. The nonvolatile data can be recalled
an unlimited number of times.
4-18
RECALL
cycle will
is
STK10C68-M
Like the
STORE
cycle, a transition must occur on some
control pin to cause a recall, preventing inadvertent
multi-triggering. On power-up, once V
V
sense voltage of 4.0V, a
CC
RECALL
cally initiated. The voltage on the V
exceeds the
CC
cycle is automati-
pin must not drop
CC
below 4.0V once it has risen above it in order for the
RECALL
to operate properly. Due to this automatic
RECALL
, SRAM operation cannot commence until t
NLQX
after VCC exceeds 4.0V. 4.0V is a typical, characterized value.
If the STK10C68-M is in a WRITE state at the end of
power-up
RECALL
, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor should
be connected between W and system VCC.
4-19
STK10C68-M
STK10C68 - 5 C 35 M
ORDERING INFORMATION
Temperature Range
M = Military (-55 to 125 degrees C)
Access Time
35 = 35ns
45 = 45ns
55 = 55ns
Package
C = Ceramic 28 pin 300-mil DIP with gold lead finish
K = Ceramic 28 pin 300-mil DIP with solder DIP finish
L = Ceramic 28 pin LCC
5962-93056 04 MX X
Retention / Endurance
10 years / 100,000 cycles
Lead Finish
A =Solder DIP lead finish
C =Gold lead DIP finish
X =Lead finish "A" or "C" is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP
MY = Ceramic 28 pin LCC
Access Time
04 = 55ns
05 = 45ns
06 = 35ns
4-20
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