SIMTEK STK10C68-5L55M, STK10C68-5L35M, STK10C68-5L45M, STK10C68-5K55M, STK10C68-5K45M Datasheet

STK10C68-M

A
A
A
A
A
A

A

A
A
A

A

A

DQ

DQ

DQDQDQ

DQ
DQ

G

A
E

DQ

Vss

NE

Vcc

W

NC

7

12

6
5
4
3
2
1
0
0
1

8
9

11

10

7
6

2

3

4

5

TOP VIEW

4
5
6
7
8

9
10
11
12

32128 27

26
25
24
23
22
21
20
19
18

1716151413

STK10C68-M

CMOS nvSRAM

High Performance

8K x 8 Nonvolatile Static RAM

MIL-STD-833/SMD 5962 - 93056

FEATURES

• 35, 45 and 55ns Access Times

• 20 and 25ns Output Enable Access

• Unlimited Read and Write to SRAM

• Hardware

• Automatic

• 100,000

STORE

STORE

STORE

Initiation

Timing

cycles to EEPROM

• 10 year data retention in EEPROM

• Automatic

• Hardware

• Unlimited

RECALL
RECALL
RECALL

on Power Up
Initiation
cycles from EEPROM

• Single 5V±10% Operation

• Available in multiple standard packages

LOGIC BLOCK DIAGRAM

EEPROM ARRAY

256 x 256

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

12

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

DQ

7

ROW DECODER

INPUT BUFFERS

STATIC RAM

ARRAY

256 x 256

COLUMN I/O

COLUMN DECODER

AAAAA

0 1 2 10 11

STORE

RECALL

DESCRIPTION

The Simtek STK10C68-M is a fast static RAM (35, 45
and 55ns), with a nonvolatile electrically-erasable PROM
(EEPROM) element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent nonvolatile data
resides in EEPROM. Data may easily be transferred
from the SRAM to the EEPROM (

EEPROM to the SRAM (

RECALL

STORE

), or from the

) using the NE pin. It
combines the high performance and ease of use of a
fast SRAM with nonvolatile data integrity.

The STK10C68 features industry standard pinout for
nonvolatile RAMs in a 28-pin 300 mil ceramic DIP, and
28-pad LCC packages. Commercial and industrial
temperature devices are also available.

PIN CONFIGURATIONS

1

28

2

27
26

3

7

25

4

6

24

5

5

23

6

4

7

22

3

8

21

2

9

20

1

10

19

0

18

11

0

17

12

1

16

13

2

15

14

28-300 CDIP

STORE/
RECALL

CONTROL

28-LCC

PIN NAMES

A0 - A
W Write Enable

12

Address Inputs

NE
A

12

A
A
A
A
A
A
A

A
DQ
DQ
DQ

V

SS

DQ0 - DQ7Data In/Out
E Chip Enable

G

NE

G Output Enable
NE Nonvolatile Enable
V

E
W

CC

V

SS

Power (+5V)
Ground

4-11

V

CC

W
NC
A

8

A

9

A

11

G
A

10

E
DQ

7

DQ

6

DQ

5

DQ

4

DQ

3

STK10C68-M

ABSOLUTE MAXIMUM RATINGS

Voltage on typical input relative to V
Voltage on DQ

Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V)

0-7

Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W

DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA

. . . . . . . . . . . . . –0.6V to 7.0V

SS

a

Note a: Stresses greater than those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

(One output at a time, one second duration)
DC CHARACTERISTICS (VCC = 5.0V ± 10%)

SYMBOL PARAMETER MIN MAX UNITS NOTES

b

I

CC

I

CC

I

SB

I

SB

I

ILK

I

OLK

V

IH

V

IL

V

OH

V

OL

T

A

Note b: ICC is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: I

Average VCC Current 90 mA t

1

d

Average VCC Current 50 mA E ≥ (VCC – 0.2V)

2

during

STORE

c

Average VCC Current 27 mA t

1

(Standby, Cycling TTL Input Levels) 23 mA t

c

Average VCC Current 2 mA E ≥ (VCC – 0.2V)

2

(Standby, Stable CMOS Input Levels) all others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
Input Leakage Current (Any Input) ±1 µAVCC = max

Off State Output Leakage Current ±5 µAVCC = max

Input Logic "1" Voltage 2.2 VCC+.5 V All Inputs
Input Logic "0" Voltage VSS–.5 0.8 V All Inputs
Output Logic "1" Voltage 2.4 V I
Output Logic "0" Voltage 0.4 V I
Operating Temperature –55 125 °C

1

is the average current required for the duration of the store cycle (t

CC

2

cycle all others VIN ≤ 0.2V or ≥ (VCC – 0.2V)

STORE

85 mA t
80 mA t

20 mA t

) after the sequence (tWC) that initiates the cycle.

= 35ns

AVAV

= 45ns

AVAV

= 55ns

AVAV

= 35ns

AVAV

= 45ns

AVAV

= 55ns

AVAV

E ≥ VIH; all others cycling

VIN = VSS to V

VIN = VSS to V

= –4mA

OUT

= 8mA

OUT

CC

CC

AC TEST CONDITIONS

Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V

Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V

Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

CAPACITANCEe (T

SYMBOL PARAMETER MAX UNITS CONDITIONS

C
C

Note e: These parameters are guaranteed but not tested.

Input Capacitance 5 pF ∆V = 0 to 3V

IN

Output Capacitance 7 pF ∆V = 0 to 3V

OUT

=25°C, f=1.0MHz)

A

4-12

Output

255 Ohms

Figure 1: AC Output Loading

5.0V

480 Ohms

INCLUDING

AND FIXTURE

30pF

SCOPE

STK10C68-M

READ CYCLES #1 & #2

NO. PARAMETER UNITS

1t
2t
3t
4t
5t
6t
7t
8t

9t
10 t
11 t

11A t

SYMBOLS STK10C68-35M STK10C68-45M STK10C68-55M

#1, #2 Alt. MIN MAX MIN MAX MIN MAX

t

ELQV

AVAV

AVQV

GLQV

AXQX

ELQX

EHQZ

GLQX

GHQZ

ELICCH

EHICCL

WHQV

g

h

i

i

e

c,e

Chip Enable Access Time 35 45 55 ns

ACS

t

Read Cycle Time 35 45 55 ns

RC

t

Address Access Time 35 45 55 ns

AA

t

Output Enable to Data Valid 20 25 25 ns

OE

t

Output Hold After Address Change 5 5 5 ns

OH

t

Chip Enable to Output Active 5 5 5 ns

LZ

t

Chip Disable to Output Inactive 17 20 25 ns

HZ

t

Output Enable to Output Active 0 0 0 ns

OLZ

t

Output Disable to Output Inactive 17 20 25 ns

OHZ

t

Chip Enable to Power Active 0 0 0 ns

PA

t

Chip Disable to Power Standby 35 45 55 ns

PS

t

Write Recovery Time 45 55 65 ns

WR

(VCC = 5.0V ± 10%)

Note c: Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note f: NE must be high during entire cycle.
Note g: For READ CYCLE #1 and #2, W and NE must be high for entire cycle.
Note h: Device is continuously selected with E low and G low.
Note i: Measured ± 200mV from steady state output voltage.

f,g,h

READ CYCLE #1

2

t

AVAV

ADDRESS

3

t

AVQV

DATA VALID

DQ (Data Out)

t

AXQX

5

W

READ CYCLE #2

ADDRESS

E

G

DQ (Data Out)

I

ACTIVE
STANDBY

CC

W

f,g

10

t

ELICCH

11A

t

WHQV

t

ELQX

2

t

AVAV

1

t

11A

WHQV

t

GLQX

8

t

GLQV

ELQV

4

t

GHQZ

DATA VALID

9

6

t

t

EHQZ

11

t

EHICCL

7

4-13